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1. 发明授权

US07067868B2 Double gate device having a heterojunction source/drain and strained channel 有权
公开(公告)号：US07067868B2
公开(公告)日：2006-06-27
申请号：US10952676
申请日：2004-09-29
申请人： Voon-Yew Thean , Mariam G. Sadaka , Ted R. White , Alexander L. Barr , Venkat R. Kolagunta , Bich-Yen Nguyen , Victor H. Vartanian , Da Zhang
发明人： Voon-Yew Thean , Mariam G. Sadaka , Ted R. White , Alexander L. Barr , Venkat R. Kolagunta , Bich-Yen Nguyen , Victor H. Vartanian , Da Zhang
IPC分类号： H01L27/108
CPC分类号： H01L29/785 , H01L29/42392 , H01L29/66628 , H01L29/66742 , H01L29/7842 , H01L29/78621 , H01L29/78648 , H01L29/78687
摘要： A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.

2. 发明授权

US07018901B1 Method for forming a semiconductor device having a strained channel and a heterojunction source/drain 失效
标题翻译：用于形成具有应变通道和异质结源极/漏极的半导体器件的方法
公开(公告)号：US07018901B1
公开(公告)日：2006-03-28
申请号：US10954121
申请日：2004-09-29
申请人： Voon-Yew Thean , Mariam G. Sadaka , Ted R. White , Alexander L. Barr , Venkat R. Kolagunta , Bich-Yen Nguyen , Victor H. Vartanian , Da Zhang
发明人： Voon-Yew Thean , Mariam G. Sadaka , Ted R. White , Alexander L. Barr , Venkat R. Kolagunta , Bich-Yen Nguyen , Victor H. Vartanian , Da Zhang
IPC分类号： H01L21/336
CPC分类号： H01L21/2254 , H01L29/665 , H01L29/66787 , H01L29/7848 , H01L29/785 , H01L29/78648
摘要： A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.
摘要翻译：半导体器件（10）通过将覆盖在优选硅的半导体层（16）上的栅极（22）定位而形成。例如仅SiGe或Ge的半导体材料（26）形成在半导体层上方的栅极和源极/漏极区域附近。热处理将应力源材料扩散到半导体层。发生横向扩散以形成应变通道（17），其中应力材料层（30）紧邻应变通道。延伸植入物从应力源材料层的第一部分产生源和漏植入物。应力源材料层的第二部分保留在应变通道和源极和漏极植入物之间的通道中。因此，在应变通道中形成异质结。在另一种形式中，发生应力源材料的氧化而不是延伸植入物以形成应变通道。

3. 发明授权

US07560318B2 Process for forming an electronic device including semiconductor layers having different stresses 有权
标题翻译：用于形成包括具有不同应力的半导体层的电子器件的工艺
公开(公告)号：US07560318B2
公开(公告)日：2009-07-14
申请号：US11374372
申请日：2006-03-13
申请人： Mariam G. Sadaka , Venkat R. Kolagunta , William J. Taylor , Victor H. Vartanian
发明人： Mariam G. Sadaka , Venkat R. Kolagunta , William J. Taylor , Victor H. Vartanian
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L21/76256 , H01L27/1203 , H01L29/7842 , H01L29/785 , H01L29/78687
摘要： An electronic device can have an insulating layer lying between a first semiconductor layer and a base layer. A second semiconductor layer, having a different composition and stress as compared to the first semiconductor layer, can overlie at least a portion of the first semiconductor layer. In one embodiment, a first electronic component can include a first active region that includes a first portion of the first and the second semiconductor layers. A second electronic component can include a second active region that can include a second portion of the first semiconductor layer. Different processes can be used to form the electronic device. In another embodiment, annealing a workpiece can be performed and the stress of at least one of the semiconductor layers can be changed. In a different embodiment, annealing the workpiece can be performed either before or after the formation of the second semiconductor layer.
摘要翻译：电子设备可以具有位于第一半导体层和基底层之间的绝缘层。与第一半导体层相比具有不同组成和应力的第二半导体层可以覆盖在第一半导体层的至少一部分上。在一个实施例中，第一电子部件可以包括第一有源区，其包括第一和第二半导体层的第一部分。第二电子部件可以包括可以包括第一半导体层的第二部分的第二有源区。可以使用不同的过程来形成电子设备。在另一个实施例中，可以执行退火工件，并且可以改变至少一个半导体层的应力。在不同的实施例中，退火工件可以在第二半导体层的形成之前或之后进行。

4. 发明授权

US07514313B2 Process of forming an electronic device including a seed layer and a semiconductor layer selectively formed over the seed layer 失效
标题翻译：形成包括种子层和选择性地形成在种子层上的半导体层的电子器件的工艺
公开(公告)号：US07514313B2
公开(公告)日：2009-04-07
申请号：US11400945
申请日：2006-04-10
申请人： Omar Zia , Da Zhang , Venkat R. Kolagunta , Narayanan C. Ramani , Bich-Yen Nguyen
发明人： Omar Zia , Da Zhang , Venkat R. Kolagunta , Narayanan C. Ramani , Bich-Yen Nguyen
IPC分类号： H01L21/98 , H01L21/8238
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7843 , H01L29/7848
摘要： A process of forming an electronic device can include forming an insulating layer over first and second active regions, and a field isolation region. The process can also include forming a seed layer and exposing the first active region. The process can further include selectively forming a first and second semiconductor layer over the first active region and the seed layer, respectively. The first and second semiconductor layers can be spaced-apart from each other. In one aspect, the process can include selectively forming the first and second semiconductor layers simultaneously at a substantially same point in time. In another aspect, an electronic device can include first and second transistor structures separated by a field isolation region and electrically connected by a conductive member. A semiconductor island, designed to be electrically floating, can lie between the conductive member and the base layer.
摘要翻译：形成电子器件的工艺可以包括在第一和第二有源区上形成绝缘层和场隔离区。该方法还可以包括形成种子层并暴露第一有源区。该方法还可以包括分别在第一有源区和种子层上选择性地形成第一和第二半导体层。第一和第二半导体层可以彼此间隔开。在一个方面，该方法可以包括在基本相同的时间点同时选择性地形成第一和第二半导体层。在另一方面，电子设备可以包括由场隔离区分隔开并由导电构件电连接的第一和第二晶体管结构。设计为电浮置的半导体岛可以位于导电构件和基底层之间。

5. 发明申请

US20080261362A1 METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A STRESSOR 失效
标题翻译：使用压力器制造半导体器件的方法
公开(公告)号：US20080261362A1
公开(公告)日：2008-10-23
申请号：US11737496
申请日：2007-04-19
申请人： Da Zhang , Xiangzheng Bo , Venkat R. Kolagunta
发明人： Da Zhang , Xiangzheng Bo , Venkat R. Kolagunta
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/84 , H01L29/665 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： A method for forming a semiconductor device includes providing a substrate and forming a p-channel device and an n-channel device, each of the p-channel device and the n-channel device comprising a source, a drain, and a gate, the p-channel device having a first sidewall spacer and the n-channel device having a second sidewall spacer. The method further includes forming a liner and forming a tensile stressor layer over the liner and removing a portion of the tensile stressor layer from a region overlying the p-channel device. The method further includes transferring a stress characteristic of an overlying portion of a remaining portion of the tensile stressor layer to a channel of the n-channel device. The method further includes using the remaining portion of the tensile stressor layer as a hard mask, forming a first recess and a second recess adjacent the gate of the p-channel device.
摘要翻译：一种用于形成半导体器件的方法包括提供衬底并形成p沟道器件和n沟道器件，每个p沟道器件和n沟道器件包括源极，漏极和栅极， p沟道器件具有第一侧壁间隔物，并且所述n沟道器件具有第二侧壁间隔物。该方法还包括形成衬套并在衬套上形成拉伸应力层，并从覆盖p沟道器件的区域去除拉伸应力层的一部分。该方法还包括将拉伸应力层的剩余部分的上覆部分的应力特性转移到n沟道器件的通道。该方法还包括使用拉伸应力层的剩余部分作为硬掩模，形成邻近p沟道器件的栅极的第一凹槽和第二凹槽。

6. 发明授权

US07727870B2 Method of making a semiconductor device using a stressor 失效
标题翻译：使用压力源制造半导体器件的方法
公开(公告)号：US07727870B2
公开(公告)日：2010-06-01
申请号：US11737496
申请日：2007-04-19
申请人： Da Zhang , Xiangzheng Bo , Venkat R. Kolagunta
发明人： Da Zhang , Xiangzheng Bo , Venkat R. Kolagunta
IPC分类号： H01L21/3205
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/84 , H01L29/665 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： A method for forming a semiconductor device includes providing a substrate and forming a p-channel device and an n-channel device, each of the p-channel device and the n-channel device comprising a source, a drain, and a gate, the p-channel device having a first sidewall spacer and the n-channel device having a second sidewall spacer. The method further includes forming a liner and forming a tensile stressor layer over the liner and removing a portion of the tensile stressor layer from a region overlying the p-channel device. The method further includes transferring a stress characteristic of an overlying portion of a remaining portion of the tensile stressor layer to a channel of the n-channel device. The method further includes using the remaining portion of the tensile stressor layer as a hard mask, forming a first recess and a second recess adjacent the gate of the p-channel device.
摘要翻译：一种用于形成半导体器件的方法包括提供衬底并形成p沟道器件和n沟道器件，每个p沟道器件和n沟道器件包括源极，漏极和栅极， p沟道器件具有第一侧壁间隔物，并且所述n沟道器件具有第二侧壁间隔物。该方法还包括形成衬套并在衬套上形成拉伸应力层，并从覆盖p沟道器件的区域去除拉伸应力层的一部分。该方法还包括将拉伸应力层的剩余部分的上覆部分的应力特性转移到n沟道器件的通道。该方法还包括使用拉伸应力层的剩余部分作为硬掩模，形成邻近p沟道器件的栅极的第一凹槽和第二凹槽。

7. 发明申请

US20120302022A1 METHOD FOR FORMING AN ASYMMETRIC SEMICONDUCTOR DEVICE 审中-公开
标题翻译：形成不对称半导体器件的方法
公开(公告)号：US20120302022A1
公开(公告)日：2012-11-29
申请号：US13117191
申请日：2011-05-27
申请人： Venkat R. Kolagunta
发明人： Venkat R. Kolagunta
IPC分类号： H01L21/8234
CPC分类号： H01L21/823857 , H01L21/82385
摘要： A method for fabricating at least three different types of devices on a semiconductor substrate comprises forming a first electrode region and a second electrode region for a first semiconductor device at the same time as forming a first electrode region of a asymmetrical semiconductor device, and forming a first electrode region and a second electrode region for a second semiconductor device at the same time as forming a second electrode region of the asymmetrical semiconductor device.
摘要翻译：一种用于在半导体衬底上制造至少三种不同类型的器件的方法包括在形成第一半导体器件的第一电极区域和第二电极区域的同时形成非对称半导体器件的第一电极区域，并形成第一电极区域和用于第二半导体器件的第二电极区域，同时形成非对称半导体器件的第二电极区域。

8. 发明申请

US20110003444A1 PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING INSULATING LAYERS HAVING DIFFERENT STRAINS 有权
标题翻译：形成电子装置的方法，包括具有不同应变的绝缘层
公开(公告)号：US20110003444A1
公开(公告)日：2011-01-06
申请号：US12883096
申请日：2010-09-15
申请人： Paul A. Grudowski , Venkat R. Kolagunta , Mehul D. Shroff
发明人： Paul A. Grudowski , Venkat R. Kolagunta , Mehul D. Shroff
IPC分类号： H01L21/8238
CPC分类号： H01L27/1203 , H01L21/0214 , H01L21/0217 , H01L21/02266 , H01L21/0228 , H01L21/31105 , H01L21/3143 , H01L21/3185 , H01L21/76264 , H01L21/84 , H01L29/78 , H01L29/7843
摘要： An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies entirely within the field isolation region. The electronic device can also include a second insulating layer having a second strain different from the first strain and including an opening. From a top view, the portion of the first insulating layer can lie within the opening in the second insulating layer. In one embodiment, the field isolation region can include a dummy structure and the portion of the first insulating layer can overlie the dummy structure. A process of forming the electronic device can include forming an island portion of an insulating layer wherein from a top view, the island portion lies entirely within the field isolation region.
摘要翻译：电子设备可以包括场隔离区域和具有第一应变的第一绝缘层，并且具有从顶视图完全位于场隔离区域内的部分。电子器件还可以包括具有不同于第一应变的第二应变并且包括开口的第二绝缘层。从顶视图，第一绝缘层的部分可以位于第二绝缘层的开口内。在一个实施例中，场隔离区域可以包括虚拟结构，并且第一绝缘层的部分可以覆盖虚拟结构。形成电子器件的过程可以包括形成绝缘层的岛部，其中从顶视图看，岛部完全位于场隔离区内。

9. 发明授权

US07714318B2 Electronic device including a transistor structure having an active region adjacent to a stressor layer 有权
标题翻译：电子器件包括具有与应力层相邻的有源区的晶体管结构
公开(公告)号：US07714318B2
公开(公告)日：2010-05-11
申请号：US12180818
申请日：2008-07-28
申请人： Vance H. Adams , Paul A. Grudowski , Venkat R. Kolagunta , Brian A. Winstead
发明人： Vance H. Adams , Paul A. Grudowski , Venkat R. Kolagunta , Brian A. Winstead
IPC分类号： H01L29/06
CPC分类号： H01L21/84 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/045 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/7843
摘要： An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.
摘要翻译：电子器件可以包括第一导电类型的晶体管结构，场隔离区域和覆盖场隔离区域的第一应力类型的层。例如，晶体管结构可以是p沟道晶体管结构，并且第一应力类型可以是拉伸的，或者晶体管结构可以是n沟道晶体管结构，并且第一应力类型可以是压缩的。晶体管结构可以包括位于有源区内的沟道区。有源区域的边缘包括沟道区域和场隔离区域之间的界面。从顶视图，该层可以包括位于活动区域边缘附近的边缘。边缘之间的位置关系可以影响晶体管结构的沟道区内的载流子迁移率。

10. 发明授权

US07843011B2 Electronic device including insulating layers having different strains 有权
标题翻译：电子器件包括具有不同应变的绝缘层
公开(公告)号：US07843011B2
公开(公告)日：2010-11-30
申请号：US11669794
申请日：2007-01-31
申请人： Paul A. Grudowski , Venkat R. Kolagunta , Mehul D. Shroff
发明人： Paul A. Grudowski , Venkat R. Kolagunta , Mehul D. Shroff
IPC分类号： H01L27/092
CPC分类号： H01L27/1203 , H01L21/0214 , H01L21/0217 , H01L21/02266 , H01L21/0228 , H01L21/31105 , H01L21/3143 , H01L21/3185 , H01L21/76264 , H01L21/84 , H01L29/78 , H01L29/7843
摘要： An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies entirely within the field isolation region. The electronic device can also include a second insulating layer having a second strain different from the first strain and including an opening. From a top view, the portion of the first insulating layer can lie within the opening in the second insulating layer. In one embodiment, the field isolation region can include a dummy structure and the portion of the first insulating layer can overlie the dummy structure. A process of forming the electronic device can include forming an island portion of an insulating layer wherein from a top view, the island portion lies entirely within the field isolation region.
摘要翻译：电子设备可以包括场隔离区域和具有第一应变的第一绝缘层，并且具有从顶视图完全位于场隔离区域内的部分。电子器件还可以包括具有不同于第一应变的第二应变并且包括开口的第二绝缘层。从顶视图，第一绝缘层的部分可以位于第二绝缘层的开口内。在一个实施例中，场隔离区域可以包括虚拟结构，并且第一绝缘层的部分可以覆盖虚拟结构。形成电子器件的过程可以包括形成绝缘层的岛部，其中从顶视图看，岛部完全位于场隔离区内。

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