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1. 发明申请

US20060148196A1 SEMICONDUCTOR FABRICATION PROCESS INCLUDING RECESSED SOURCE/DRAIN REGIONS IN AN SOI WAFER 有权
标题翻译：半导体制造工艺，包括SOI WAFER中的残留源/漏区
公开(公告)号：US20060148196A1
公开(公告)日：2006-07-06
申请号：US11028811
申请日：2005-01-03
申请人： Voon-Yew Thean , Brian Goolsby , Bich-Yen Nguyen , Thien Nguyen , Tab Stephens
发明人： Voon-Yew Thean , Brian Goolsby , Bich-Yen Nguyen , Thien Nguyen , Tab Stephens
IPC分类号： H01L21/76
CPC分类号： H01L29/66636 , H01L29/66772 , H01L29/78639
摘要： A method of forming a transistor with recessed source/drains in an silicon-on-insulator (SOI) wafer includes forming isolation structures in an active layer of the wafer, where the isolation structures preferably extend through the active layer to a BOX layer of the wafer. An upper portion of the active layer is removed to form a transistor channel structure. A gate dielectric is formed on the channel structure and a gate structure is formed on the gate dielectric. Etching through exposed portions of the gate dielectric, channel structure, and BOX layer is performed and source/drain structures are then grown epitaxially from exposed portions of the substrate bulk. The isolation structure and the BOX layer are both comprised primarily of silicon oxide and the thickness of the isolation structure prevents portions of the BOX layer from being etched.
摘要翻译：在绝缘体上硅（SOI）晶片中形成具有凹陷源/漏极的晶体管的方法包括在晶片的有源层中形成隔离结构，其中隔离结构优选地延伸穿过有源层到BOX层的BOX层晶圆。去除有源层的上部以形成晶体管沟道结构。在沟道结构上形成栅极电介质，在栅极电介质上形成栅极结构。执行蚀刻通过栅介质，沟道结构和BOX层的暴露部分，然后从衬底体的暴露部分外延生长源极/漏极结构。隔离结构和BOX层主要由氧化硅组成，并且隔离结构的厚度防止BOX层的部分被蚀刻。

2. 发明申请

US20060063364A1 Method of forming a semiconductor device having a metal layer 有权
标题翻译：形成具有金属层的半导体器件的方法
公开(公告)号：US20060063364A1
公开(公告)日：2006-03-23
申请号：US10943383
申请日：2004-09-17
申请人： Tab Stephens , Brian Goolsby , Bich-Yen Nguyen , Voon-Yew Thean
发明人： Tab Stephens , Brian Goolsby , Bich-Yen Nguyen , Voon-Yew Thean
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28088 , H01L21/32136 , H01L21/32137 , H01L29/4908 , H01L29/4966 , H01L29/517 , H01L29/785 , Y10S438/963
摘要： A metal layer is formed over a metal oxide, where the metal oxide is formed over a semiconductor substrate. A predetermined critical dimension of the metal layer is determined. A first etch is performed to etch the metal layer down to the metal oxide and form footings at the sidewalls of the metal layer. A second etch to remove the footings to target a predetermined critical dimension, wherein the second etch is selective to the metal oxide. In one embodiment, a conductive layer is formed over the metal layer. The bulk of the conductive layer may be etched leaving a portion in contact with the metal layer. Next, the portion left in contact with the metal layer may be etched using chemistry selective to the metal layer.
摘要翻译：在金属氧化物之上形成金属层，其中在半导体衬底上形成金属氧化物。确定金属层的预定临界尺寸。执行第一蚀刻以将金属层向下蚀刻到金属氧化物并在金属层的侧壁处形成基脚。用于移除基脚以靶向预定临界尺寸的第二蚀刻，其中第二蚀刻对金属氧化物是选择性的。在一个实施例中，在金属层上形成导电层。可以蚀刻导电层的主体，留下与金属层接触的部分。接下来，可以使用化学选择性地蚀刻与金属层接触的部分。

3. 发明申请

US20070272952A1 ELECTRONIC DEVICES INCLUDING A SEMICONDUCTOR LAYER 有权
标题翻译：包括半导体层的电子器件
公开(公告)号：US20070272952A1
公开(公告)日：2007-11-29
申请号：US11836844
申请日：2007-08-10
申请人： Voon-Yew Thean , Brian Goolsby , Linda McCormick , Bich-Yen Nguyen , Colita Parker , Mariam Sadaka , Victor Vartanian , Ted White , Melissa Zavala
发明人： Voon-Yew Thean , Brian Goolsby , Linda McCormick , Bich-Yen Nguyen , Colita Parker , Mariam Sadaka , Victor Vartanian , Ted White , Melissa Zavala
IPC分类号： H01L29/80
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823878 , H01L27/1203
摘要： An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.
摘要翻译：电子设备可以包括第一半导体部分和第二半导体部分，其中第一半导体部分和第二半导体部分的组成彼此不同。在一个实施例中，第一和第二半导体部分可以具有彼此不同的应力。在一个实施例中，可以通过在第一半导体部分上形成氧化掩模来形成电子器件。可以在第一半导体层的第二半导体部分上形成第二半导体层，并且与第一半导体层相比具有不同的组成。可以进行氧化，并且可以增加第一半导体层的第二部分内的半导体元素（例如锗）的浓度。在另一个实施例中，可以执行选择性冷凝，并且可以在第一半导体层的第一和第二部分之间形成场隔离区。

4. 发明申请

US20070108481A1 Electronic devices including a semiconductor layer and a process for forming the same 有权
公开(公告)号：US20070108481A1
公开(公告)日：2007-05-17
申请号：US11273092
申请日：2005-11-14
申请人： Voon-Yew Thean , Brian Goolsby , Linda McCormick , Bich-Yen Nguyen , Colita Parker , Mariam Sadaka , Victor Vartanian , Ted White , Melissa Zavala
发明人： Voon-Yew Thean , Brian Goolsby , Linda McCormick , Bich-Yen Nguyen , Colita Parker , Mariam Sadaka , Victor Vartanian , Ted White , Melissa Zavala
IPC分类号： H01L29/76
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823878 , H01L27/1203
摘要： An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.

5. 发明申请

US20060030093A1 Strained semiconductor devices and method for forming at least a portion thereof 审中-公开
标题翻译：应变半导体器件及其至少一部分的形成方法
公开(公告)号：US20060030093A1
公开(公告)日：2006-02-09
申请号：US10913099
申请日：2004-08-06
申请人： Da Zhang , Brian Goolsby , Eric Luckowski , Bich-Yen Nguyen , Mariam Sadaka , Voon-Yew Thean , Ted White
发明人： Da Zhang , Brian Goolsby , Eric Luckowski , Bich-Yen Nguyen , Mariam Sadaka , Voon-Yew Thean , Ted White
IPC分类号： H01L21/8234
CPC分类号： H01L29/7842 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/66651 , H01L29/66742 , H01L29/7834 , H01L29/7848 , H01L29/78687
摘要： A method for forming at least a portion of a semiconductor device includes providing a substrate and epitaxially forming an etch stop layer over the substrate. A first layer is provided over the etch stop layer, wherein the first layer is selectively etchable with regard to the etch stop layer. A structure is provided over a region of the first layer, wherein the region is not all of the first layer. In addition, the method includes etching at least a portion of the first layer that is outside of the region, wherein the etch stop layer is used an as etch stop. A strained layer is epitaxially grown in the etch-recessed region.
摘要翻译：用于形成半导体器件的至少一部分的方法包括提供衬底并在衬底上外延地形成蚀刻停止层。第一层设置在蚀刻停止层上方，其中第一层相对于蚀刻停止层可选择性地蚀刻。在第一层的区域上提供结构，其中该区域不是全部第一层。此外，该方法包括蚀刻位于该区域之外的第一层的至少一部分，其中蚀刻停止层用作蚀刻停止。在蚀刻凹陷区域中外延生长应变层。

6. 发明申请

US20070032003A1 Method for forming uniaxially strained devices 有权
标题翻译：形成单轴应变装置的方法
公开(公告)号：US20070032003A1
公开(公告)日：2007-02-08
申请号：US11195510
申请日：2005-08-02
申请人： Da Zhang , Veer Dhandapani , Brian Goolsby , Bich-Yen Nguyen
发明人： Da Zhang , Veer Dhandapani , Brian Goolsby , Bich-Yen Nguyen
IPC分类号： H01L21/8234
CPC分类号： H01L29/66636 , H01L29/165 , H01L29/517 , H01L29/518 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7848
摘要： A method for making a semiconductor device is provided herein. In accordance with the method, a semiconductor structure is provided which comprises a substrate (201) with a gate structure (209) disposed thereon, wherein the gate structure comprises a gate electrode (227) and at least one spacer structure (215, 217), and wherein the substrate comprises a first semiconductor material. A first trench (231) is created in the substrate adjacent to the gate structure through the use of a first etch. The gate electrode is then etched with a second etch. Preferably, the minimum cumulative reduction in thickness of the gate electrode from the first and second etches is dg, the maximum depth of the first and second trenches after the first and second etches is dt, and dg≧dt.
摘要翻译：本发明提供制造半导体器件的方法。根据该方法，提供一种半导体结构，其包括其上设置有栅极结构（209）的衬底（201），其中栅极结构包括栅电极（227）和至少一个间隔结构（215,217），并且其中所述衬底包括第一半导体材料。通过使用第一蚀刻，在邻近栅极结构的衬底中形成第一沟槽（231）。然后用第二蚀刻蚀刻栅电极。优选地，来自第一和第二蚀刻的栅电极的厚度的最小累积减小为d 1，第一和第二蚀刻之后的第一和第二沟槽的最大深度为d t 和d = d 。

7. 发明授权

US07238561B2 Method for forming uniaxially strained devices 有权
公开(公告)号：US07238561B2
公开(公告)日：2007-07-03
申请号：US11195510
申请日：2005-08-02
申请人： Da Zhang , Veer Dhandapani , Brian Goolsby , Bich-Yen Nguyen
发明人： Da Zhang , Veer Dhandapani , Brian Goolsby , Bich-Yen Nguyen
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L29/165 , H01L29/517 , H01L29/518 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7848
摘要： A method for making a semiconductor device is provided herein. In accordance with the method, a semiconductor structure is provided which comprises a substrate (201) with a gate structure (209) disposed thereon, wherein the gate structure comprises a gate electrode (227) and at least one spacer structure (215, 217), and wherein the substrate comprises a first semiconductor material. A first trench (231) is created in the substrate adjacent to the gate structure through the use of a first etch. The gate electrode is then etched with a second etch. Preferably, the minimum cumulative reduction in thickness of the gate electrode from the first and second etches is dg, the maximum depth of the first and second trenches after the first and second etches is dt, and dg≧dt.

8. 发明申请

US20060286736A1 Method for forming an electronic device 有权
标题翻译：电子设备的形成方法
公开(公告)号：US20060286736A1
公开(公告)日：2006-12-21
申请号：US11152931
申请日：2005-06-15
申请人： Marius Orlowski , Brian Goolsby
发明人： Marius Orlowski , Brian Goolsby
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/823418
摘要： An electronic device is formed by forming a first and second layer overlying a plurality of transistor locations. An etch is performed to remove portions of the first and second layers to expose a portion of the plurality of transistor locations, while other portions of the first and second layer remain to protect other transistor locations. Subsequently, source/drain locations of the exposed transistor locations are etched along with the remaining portion of the second layer. The etch is substantially terminated by removing the portion of the second layer using an end-point detection technique involving the first layer. Subsequently an epitaxial layer is formed in the source/drain recesses to provide stress on a channel region of the transistor locations.
摘要翻译：通过形成覆盖多个晶体管位置的第一和第二层来形成电子器件。执行蚀刻以去除第一层和第二层的部分以暴露多个晶体管位置的一部分，而第一层和第二层的其它部分保留以保护其他晶体管位置。随后，暴露的晶体管位置的源极/漏极位置与第二层的剩余部分一起被蚀刻。通过使用涉及第一层的端点检测技术去除第二层的部分来基本上终止蚀刻。随后在源极/漏极凹槽中形成外延层，以在晶体管位置的沟道区上提供应力。

9. 发明申请

US20060292773A1 Method of making a metal gate semiconductor device 有权
标题翻译：制造金属栅极半导体器件的方法
公开(公告)号：US20060292773A1
公开(公告)日：2006-12-28
申请号：US11166138
申请日：2005-06-24
申请人： Brian Goolsby , Bruce White
发明人： Brian Goolsby , Bruce White
IPC分类号： H01L21/336
CPC分类号： H01L29/4966 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： A patterned polysilicon gate is over a metal layer that is over a gate dielectric layer, which in turn is over a semiconductor substrate. A thin layer of material is conformally deposited over the polysilicon gate and the exposed metal layer and then etched back to form a sidewall spacer on the polysilicon gate and to re-expose the previously exposed portion of the metal layer. The re-exposed metal layer is etched using an etchant that is selective to the gate dielectric material and the sidewall spacer. Even though this etch is substantially anisotropic, it has an isotropic component that would etch the sidewall of the polysilicon gate but for the protection provided by the sidewall spacer. After the re-exposed metal has been removed, a transistor is formed in which the metal layer sets the work function of the gate of the transistor.
摘要翻译：图案化多晶硅栅极位于栅极电介质层上方的金属层上，栅极电介质层又在半导体衬底上。材料的薄层共形沉积在多晶硅栅极和暴露的金属层上，然后被回蚀刻以在多晶硅栅极上形成侧壁间隔物并且重新暴露金属层的先前暴露的部分。使用对栅极电介质材料和侧壁间隔物选择性的蚀刻剂蚀刻再曝光的金属层。尽管这种蚀刻基本上是各向异性的，但是它具有各向同性的成分，其蚀刻多晶硅栅极的侧壁，但是用于由侧壁间隔物提供的保护。在再暴露的金属被去除之后，形成晶体管，其中金属层设置晶体管的栅极的功函数。

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