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61. 发明授权

US07405588B2 Device and data processing method employing the device 失效
标题翻译：使用该设备的设备和数据处理方法
公开(公告)号：US07405588B2
公开(公告)日：2008-07-29
申请号：US10933272
申请日：2004-09-03
申请人： Takayuki Kawahara , Masayuki Miyazaki , Yasushi Goto , Natsuki Yokoyama , Takahiro Onai
发明人： Takayuki Kawahara , Masayuki Miyazaki , Yasushi Goto , Natsuki Yokoyama , Takahiro Onai
IPC分类号： H03K19/173
CPC分类号： G11C23/00 , H03K19/1776 , H03K19/1778
摘要： The present invention relates to an LSI in which functions can be changed, and realizes, particularly, a system LSI in which functions are changed by changing connections of the circuit by use of MEMS switches. A bistable MEMS switch which can maintain states, and exhibits optimal stitching property, i.e., the switch has a very small resistance of several Ω or less in an on-state, and has an infinite resistance in an off-state; is employed. An element in which functions can be changed during operation, is produced by utilizing a wiring layer of a CMOS semiconductor to form the MEMS switch. A semiconductor device exhibiting high-degree of freedom for changing functions, high-speed, and having small area, is realized.
摘要翻译：本发明涉及可以改变功能的LSI，特别是实现通过使用MEMS开关改变电路的连接来改变功能的系统LSI。可以保持状态并且表现出最佳缝合性能的双稳态MEMS开关，即开关在导通状态下具有几欧姆或更小的非常小的电阻，并且在断开状态下具有无限电阻; 被雇用。通过使用CMOS半导体的布线层来形成功能可以在操作期间改变的元件来形成MEMS开关。实现了具有高自由度，高速度，小面积化的高自由度的半导体装置。

62. 发明申请

US20080116934A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20080116934A1
公开(公告)日：2008-05-22
申请号：US11970370
申请日：2008-01-07
申请人： Hiroyuki Mizuno , Koichiro Ishibashi , Masayuki Miyazaki
发明人： Hiroyuki Mizuno , Koichiro Ishibashi , Masayuki Miyazaki
IPC分类号： H03K3/01
CPC分类号： H01L27/0207 , H01L27/092 , H01L27/105 , H03K3/011 , H03K3/0315 , H03K19/0016
摘要： A semiconductor device which includes a frequency-variable oscillation circuit including plural inverters, each of which features a PMOS transistor and a NMOS transistor, a first substrate bias generator including a first phase/frequency compare circuit that compares an output signal from the frequency-variable oscillation circuit with a reference clock signal and generating a first substrate bias voltage in response thereto, the first substrate bias voltage being supplied to substrates of the PMOS transistors in the oscillation circuit, and a second substrate bias generator including a second phase/frequency compare circuit that compares the output signal from the frequency-variable oscillation circuit with the reference clock and generating a second substrate bias voltage in response thereto, the second substrate bias voltage being supplied to substrates of the NMOS transistors in the oscillation circuit.
摘要翻译：一种半导体器件，包括具有多个反相器的频率可变振荡电路，每个反相器具有PMOS晶体管和NMOS晶体管，第一衬底偏置发生器包括第一相位/频率比较电路，其比较来自频率变量具有参考时钟信号的振荡电路，并响应于此产生第一衬底偏置电压，第一衬底偏置电压被提供给振荡电路中的PMOS晶体管的衬底，第二衬底偏置发生器包括第二相/频率比较电路其将来自频率可变振荡电路的输出信号与参考时钟进行比较，并响应于此产生第二衬底偏置电压，第二衬底偏置电压被提供给振荡电路中的NMOS晶体管的衬底。

63. 发明授权

US07330647B2 Autofocus system 有权
标题翻译：自动对焦系统
公开(公告)号：US07330647B2
公开(公告)日：2008-02-12
申请号：US11099573
申请日：2005-04-06
申请人： Tadashi Sasaki , Masayuki Miyazaki , Masao Wada , Tomohisa Koizumi
发明人： Tadashi Sasaki , Masayuki Miyazaki , Masao Wada , Tomohisa Koizumi
IPC分类号： G03B3/10 , G03B13/36
CPC分类号： G02B7/102 , G02B7/365 , H04N5/23212
摘要： In a lens system in which a momentary mode in which AF is operated when an AF switch SW2 is pressed and a continuous mode in which the AF is continuously operated can be selected, a CPU uses the AF switch SW2 for use in the momentary mode as an AF stop switch, and stops an AF process when the AF switch SW2 is pressed (turned on) in the continuous mode.
摘要翻译：在可以选择在按下AF开关SW 2时进行AF操作的瞬时模式和连续操作AF的连续模式的透镜系统中，CPU使用AF开关SW 2用于瞬时模式作为AF停止开关，并且在连续模式下按下（开启）AF开关SW 2时，停止AF处理。

64. 发明申请

US20070286102A1 Wireless Communication System Capable of Switching Protocol 审中-公开
标题翻译：无线通信系统能够开关协议
公开(公告)号：US20070286102A1
公开(公告)日：2007-12-13
申请号：US10587181
申请日：2004-03-05
申请人： Isao Shimokawa , Masayuki Miyazaki , Akira Maeki , Masaaki Shida
发明人： Isao Shimokawa , Masayuki Miyazaki , Akira Maeki , Masaaki Shida
IPC分类号： H04B7/00
CPC分类号： H04W74/08 , H04W36/14 , H04W48/18 , H04W52/0206 , H04W52/0216 , H04W52/0219 , H04W74/006 , H04W80/00 , H04W88/06 , H04W92/10
摘要： A wireless communication system comprising a management server, base stations, and a plurality of node terminals, wherein a wireless communication protocol to be applied is switched dynamically based on such indices as but error, packet error rate, the number of times of retransmitting packets, throughput/power consumption that may occur between each base station and nodes.
摘要翻译：一种无线通信系统，包括管理服务器，基站和多个节点终端，其中，基于诸如错误，分组错误率，重传分组的次数等指标动态地切换要应用的无线通信协议，每个基站和节点之间可能发生的吞吐量/功耗。

65. 发明申请

US20070063735A1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20070063735A1
公开(公告)日：2007-03-22
申请号：US11526612
申请日：2006-09-26
申请人： Hiroyuki Mizuno , Masataka Minami , Koichiro Ishibashi , Masayuki Miyazaki
发明人： Hiroyuki Mizuno , Masataka Minami , Koichiro Ishibashi , Masayuki Miyazaki
IPC分类号： H03K19/0175
CPC分类号： H01L27/0207 , H01L27/092 , H01L27/105 , H03K3/011 , H03K3/0315 , H03K19/0016
摘要： A semiconductor integrated circuit device which includes a logical circuit containing a MIS transistor on a semiconductor substrate, a control circuit for controlling a threshold voltage of the MIS transistor in the logical circuit, an oscillation circuit containing a MIS transistor on the semiconductor substrate, and a buffer circuit, the control circuit compares the frequency of the oscillation output and frequency of a clock signal to output a first control signal, the first control signal controls a threshold voltage of the MIS transistor of the oscillation circuit, and the buffer circuit is inputted with the first control signal to output a second control signal corresponding to the first control signal, the second control signal controlling the threshold voltage of the MIS transistor of the logical circuit.
摘要翻译：一种半导体集成电路器件，包括在半导体衬底上包含MIS晶体管的逻辑电路，用于控制逻辑电路中的MIS晶体管的阈值电压的控制电路，在半导体衬底上包含MIS晶体管的振荡电路，以及缓冲电路，控制电路比较振荡输出的频率和时钟信号的频率，输出第一控制信号，第一控制信号控制振荡电路的MIS晶体管的阈值电压，缓冲电路输入所述第一控制信号输出对应于所述第一控制信号的第二控制信号，所述第二控制信号控制所述逻辑电路的所述MIS晶体管的阈值电压。

66. 发明授权

US07112999B2 Semiconductor integrated circuit device 失效
公开(公告)号：US07112999B2
公开(公告)日：2006-09-26
申请号：US11124060
申请日：2005-05-09
申请人： Hiroyuki Mizuno , Masataka Minami , Koichiro Ishibashi , Masayuki Miyazaki
发明人： Hiroyuki Mizuno , Masataka Minami , Koichiro Ishibashi , Masayuki Miyazaki
IPC分类号： H03K3/01
CPC分类号： H01L27/0207 , H01L27/092 , H01L27/105 , H03K3/011 , H03K3/0315 , H03K19/0016
摘要： A semiconductor integrated circuit device comprising a logical circuit including a MIS transistor formed on a semiconductor substrate, a control circuit for controlling a threshold voltage of the MIS transistor forming the logical circuit, an oscillation circuit including a MIS transistor formed on the semiconductor substrate, the oscillation circuit being constructed so that the frequency of an oscillation output thereof can be made variable, and a buffer circuit, in which the control circuit is supplied with a clock signal having a predetermined frequency and the oscillation output of the oscillation circuit so that the control circuit compares the frequency of the oscillation output and the frequency of the clock signal to output a first control signal, the oscillation circuit is controlled by the first control signal so that the frequency of the oscillation output corresponds to the frequency of the clock signal, the control of the frequency of the oscillation output being performed in such a manner that the first control signal controls a threshold voltage of the MIS transistor forming the oscillation circuit, and the buffer circuit is constructed so that it is inputted with the first control signal to output a second control signal corresponding to the first control signal, the second control signal controlling the threshold voltage of the MIS transistor forming the logical circuit.

67. 发明申请

US20060120441A1 Receiver 有权
标题翻译：接收器
公开(公告)号：US20060120441A1
公开(公告)日：2006-06-08
申请号：US11288349
申请日：2005-11-29
申请人： Tatsuo Nakagawa , Ryosuke Fujiwara , Masayuki Miyazaki , Goichi Ono
发明人： Tatsuo Nakagawa , Ryosuke Fujiwara , Masayuki Miyazaki , Goichi Ono
IPC分类号： H04B1/707 , H04L27/22
CPC分类号： H04B1/71637
摘要： With the objective of enhancing receiving performance of a receiver with respect to pulse signals spread by spread codes, the receiver comprises an RF front-end section which performs amplification, an AD converter section which AD-converts signals outputted from the RF front-end section, a baseband section which inversely spreads the output of the AD converter section and performs signal detection and demodulation thereon, a reception environment measuring section which measures reception environment using the input signals of the baseband section, and a parameter setting section which sets parameters for respective parts on the basis of signals outputted from the reception environment measuring section. The parameter setting section sets the parameters for the respective parts to the optimum according to the environmental condition measured by the reception environment measuring section.
摘要翻译：为了提高接收机相对于由扩展码扩展的脉冲信号的接收性能，接收机包括执行放大的RF前端部分，对从RF前端部分输出的信号进行AD转换的AD转换器部分基带部分，其对AD转换器部分的输出进行反扩频并对其进行信号检测和解调;接收环境测量部分，其使用基带部分的输入信号测量接收环境;以及参数设置部分，其设置各自的参数基于从接收环境测量部输出的信号。参数设定部根据由接收环境测定部测定的环境条件，将各部分的参数设定为最佳。

68. 发明申请

US20050007183A1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US20050007183A1
公开(公告)日：2005-01-13
申请号：US10911664
申请日：2004-08-05
申请人： Masayuki Miyazaki , Koichiro Ishibashi , Hiroyuki Mizuno
发明人： Masayuki Miyazaki , Koichiro Ishibashi , Hiroyuki Mizuno
IPC分类号： H03K3/01 , H03K19/003 , H03K19/0185
CPC分类号： H03K19/00323 , H03K19/00384 , H03K19/018585
摘要： A semiconductor integrated circuit device includes a logic circuit to perform a predetermined process, a clock generator to supply a clock signal to the logic circuit, and a speed controller to control the operation speed of the logic circuit. The clock generator changes the frequency of the clock signal by a frequency control signal during a time when the logic circuit is operating, and the speed controller controls the operating speed of the logic circuit in accordance with a change in the clock signal.
摘要翻译：半导体集成电路器件包括执行预定处理的逻辑电路，向逻辑电路提供时钟信号的时钟发生器以及控制逻辑电路的操作速度的速度控制器。在逻辑电路工作时，时钟发生器通过频率控制信号来改变时钟信号的频率，速度控制器根据时钟信号的变化来控制逻辑电路的工作速度。

69. 发明授权

US06778002B2 Semiconductor integrated circuit device including a substrate bias controller and a current limiting circuit 有权
标题翻译：包括衬底偏置控制器和限流电路的半导体集成电路器件
公开(公告)号：US06778002B2
公开(公告)日：2004-08-17
申请号：US10207903
申请日：2002-07-31
申请人： Masayuki Miyazaki , Koichiro Ishibashi , Goichi Ono
发明人： Masayuki Miyazaki , Koichiro Ishibashi , Goichi Ono
IPC分类号： H03K301
CPC分类号： G05F3/205
摘要： In a semiconductor integrated circuit device, for realizing high speed, as well as superior product yield rate and usability, while reducing circuit scale and improving on product yield rate and reliability thereof, a main circuit, constructed with CMOS elements, is coupled to a speed monitor circuit for forming a speed signal corresponding to an operating speed thereof and to a substrate bias controller for supplying corresponding substrate bias voltages to the main circuit in response to the speed monitor circuit. A current limiting circuit is also provided in conjunction with the substrate bias controller to prevent an overflow of current due to bias voltage.
摘要翻译：在半导体集成电路装置中，为了实现高速化以及优异的产品成品率和可用性，在减小电路规模并提高产品产率和可靠性的同时，将由CMOS元件构成的主电路耦合到速度用于形成对应于其工作速度的速度信号的监视器电路和用于响应速度监视电路向主电路提供相应衬底偏置电压的衬底偏置控制器。还结合衬底偏置控制器提供限流电路，以防止由于偏置电压引起的电流溢出。

70. 发明授权

US06774705B2 Semiconductor integrated circuit device in which operating frequency, supply voltage and substrate bias voltage are controllable to reduce power consumption 有权
公开(公告)号：US06774705B2
公开(公告)日：2004-08-10
申请号：US09811387
申请日：2001-03-20
申请人： Masayuki Miyazaki , Koichiro Ishibashi
发明人： Masayuki Miyazaki , Koichiro Ishibashi
IPC分类号： H03K301
CPC分类号： H03K19/00384
摘要： A semiconductor integrated circuit device includes control circuits FRQCNT, VDDCNT and VBBCNT that generate the optimum clock signal, supply voltage and substrate bias respectively and then supply them to a main circuit LSI. This operation makes it possible to suppress the variations of a CMOS circuit characteristic, thereby improving the circuit performance. Further, the low power consumption is realized without degrading the operating speed of the CMOS circuit or increasing the power consumption of the CMOS circuit.

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