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61. 发明申请

US20120104470A1 REPLACEMENT GATE MOSFET WITH RAISED SOURCE AND DRAIN 有权
标题翻译：替代栅极MOSFET，具有提高的源和漏极
公开(公告)号：US20120104470A1
公开(公告)日：2012-05-03
申请号：US12913922
申请日：2010-10-28
申请人： Shom Ponoth , David V. Horak , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Chih-Chao Yang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78 , H01L29/66545 , H01L29/66553 , H01L29/66628 , H01L29/7834
摘要： A disposable dielectric spacer is formed on sidewalls of a disposable material stack. Raised source/drain regions are formed on planar source/drain regions by selective epitaxy. The disposable dielectric spacer is removed to expose portions of a semiconductor layer between the disposable material stack and the source/drain regions including the raised source/drain regions. Dopant ions are implanted to form source/drain extension regions in the exposed portions of the semiconductor layer. A gate-level dielectric layer is deposited and planarized. The disposable material stack is removed and a gate stack including a gate dielectric and a gate electrode fill a cavity formed by removal of the disposable material stack. Optionally, an inner dielectric spacer may be formed on sidewalls of the gate-level dielectric layer within the cavity prior to formation of the gate stack to tailor a gate length of a field effect transistor.
摘要翻译：一次性介电隔离件形成在一次性材料堆叠的侧壁上。通过选择性外延在平坦的源极/漏极区域上形成升高的源极/漏极区域。去除一次性电介质间隔物以暴露一次性材料堆叠和包括升高的源极/漏极区域的源极/漏极区域之间的半导体层的部分。注入掺杂离子以在半导体层的暴露部分中形成源极/漏极延伸区域。沉积栅平电介质层并进行平面化。去除一次性材料堆叠并且包括栅极电介质和栅电极的栅极堆叠填充通过去除一次性材料堆而形成的空腔。可选地，可以在形成栅极叠层之前在腔内的栅极级介电层的侧壁上形成内部电介质间隔物，以调整场效应晶体管的栅极长度。

62. 发明授权

US08008669B2 Programmable anti-fuse structure with DLC dielectric layer 失效
标题翻译：具有DLC介质层的可编程反熔丝结构
公开(公告)号：US08008669B2
公开(公告)日：2011-08-30
申请号：US12509892
申请日：2009-07-27
申请人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
IPC分类号： H01L29/15
CPC分类号： H01L23/5252 , H01L23/53276 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment an anti-fuse structure is provided that includes a first dielectric material having at least a first anti-fuse region and a second anti-fuse region, wherein at least one of the anti-fuse regions includes a conductive region embedded within the first dielectric material. The anti-fuse structure further includes a first diamond like carbon layer having a first conductivity located on at least the first dielectric material in the first anti-fuse region and a second diamond like carbon layer having a second conductivity located on at least the first dielectric material in the second anti-fuse region. In this embodiment, the second conductivity is different from the first conductivity and the first diamond like carbon layer and the second diamond like carbon layer have the same thickness. The anti-fuse structure also includes a second dielectric material located atop the first and second diamond like carbon layers. The second dielectric material includes at least one conductively filled region embedded therein.
摘要翻译：在一个实施例中，提供了一种抗熔丝结构，其包括具有至少第一抗熔融区域和第二抗熔融区域的第一电介质材料，其中至少一个反熔丝区域包括嵌入在该熔断区域内的导电区域第一电介质材料。反熔丝结构还包括第一金刚石碳层，其具有位于第一抗熔融区域中的至少第一电介质材料上的第一导电性，第二类金刚石碳层具有位于至少第一电介质上的第二导电性材料在第二个反熔丝区域。在本实施例中，第二导电率不同于第一导电性，第一类金刚石碳层和第二类金刚石碳层具有相同的厚度。反熔丝结构还包括位于第一和第二金刚石状碳层顶上的第二电介质材料。第二电介质材料包括嵌入其中的至少一个导电填充区域。

63. 发明申请

US20110163450A1 INTEGRATED CIRCUIT LINE WITH ELECTROMIGRATION BARRIERS 失效
标题翻译：集成电路与电气障碍
公开(公告)号：US20110163450A1
公开(公告)日：2011-07-07
申请号：US12652485
申请日：2010-01-05
申请人： David V. Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
发明人： David V. Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L23/50 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76847 , H01L21/76852 , H01L21/76885 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating an integrated circuit comprising an electromigration barrier in a line of the integrated circuit includes forming a spacer; forming a segmented line adjacent to opposing sides of the spacer, the segmented line formed from a first conductive material; removing the spacer to form an empty line break; and filling the empty line break with a second conductive material to form an electromigration barrier that isolates electromigration effects within individual segments of the segmented line. An integrated circuit comprising an electromigration barrier includes a line, the line comprising a first conductive material, the line further comprising a plurality of line segments separated by one or more electromigration barriers, wherein the one or more electromigration barriers comprise a second conductive material that isolates electromigration effects within individual segments of the line.
摘要翻译：一种用于制造集成电路的集成电路的方法，包括：集成电路的一行中的电迁移势垒包括形成间隔物; 形成与所述间隔物的相对侧相邻的分段线，所述分段线由第一导电材料形成; 移除间隔物以形成空线断裂; 并用第二导电材料填充空线断裂以形成电隔离屏蔽，其隔离分段线的各个段内的电迁移效应。包括电迁移屏障的集成电路包括线，该线包括第一导电材料，该线还包括由一个或多个电迁移屏障隔开的多个线段，其中所述一个或多个电迁移屏障包括隔离的第二导电材料线路各部分的电迁移效应。

64. 发明授权

US07892968B2 Via gouging methods and related semiconductor structure 有权
标题翻译：通过沟槽方法和相关的半导体结构
公开(公告)号：US07892968B2
公开(公告)日：2011-02-22
申请号：US12017141
申请日：2008-01-21
申请人： Shyng-Tsong Chen , Steven J. Holmes , David V. Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
发明人： Shyng-Tsong Chen , Steven J. Holmes , David V. Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/32139 , H01L21/31144 , H01L21/76805 , H01L21/76814 , H01L21/76831 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Methods for via gouging and a related semiconductor structure are disclosed. In one embodiment, the method includes forming a via opening in a dielectric material, the via opening aligned with a conductor; forming a protective coating over the dielectric material and in the via opening; performing via gouging; and removing the protective coating over horizontal surfaces of the dielectric material. A semiconductor structure may include a via having an interface with a conductor, the interface including a three-dimensionally shaped region extending into and past a surface of the conductor, wherein an outer edge of the three-dimensionally shaped region is distanced from an outermost surface of the via.
摘要翻译：公开了通孔沟槽的方法和相关的半导体结构。在一个实施例中，该方法包括在电介质材料中形成通孔，通孔与导体对准; 在介电材料和通孔开口上形成保护涂层; 通过刨花进行; 并且在电介质材料的水平表面上去除保护涂层。半导体结构可以包括与导体具有界面的通孔，所述界面包括延伸到导体表面中并经过导体表面的三维成形区域，其中三维成形区域的外边缘与最外表面的通道。

65. 发明授权

US08735279B2 Air-dielectric for subtractive etch line and via metallization 有权
标题翻译：用于减法蚀刻线和通孔金属化的空气电介质
公开(公告)号：US08735279B2
公开(公告)日：2014-05-27
申请号：US13013108
申请日：2011-01-25
申请人： David V Horak , Elbert Huang , Charles W Koburger , Shom Ponoth , Chih-Chao Yang
发明人： David V Horak , Elbert Huang , Charles W Koburger , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L23/522 , H01L21/76802 , H01L21/7682 , H01L21/76885 , H01L21/76897 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method and structure is disclosed whereby multiple interconnect layers having effective air gaps positioned in regions most susceptible to capacitive coupling can be formed. The method includes providing a layer of conductive features, the layer including at least two line members disposed on a substrate and spaced from one another by less than or equal to an effective distance, and at least one such line member also having a via member extending away from the substrate, depositing a poorly conformal dielectric coating to form an air gap between such line members, and exposing a top end of the via.
摘要翻译：公开了一种方法和结构，其中可以形成具有位于最容易受电容耦合的区域中的有效气隙的多个互连层。该方法包括提供导电特征层，所述层包括设置在基底上并彼此隔开小于或等于有效距离的至少两个线构件，以及至少一个这样的线构件，其还具有延伸的通孔构件离开基板，沉积不良共形介电涂层以在这些线构件之间形成气隙，并露出通孔的顶端。

66. 发明授权

US08703604B2 Creation of vias and trenches with different depths 有权
标题翻译：创造不同深度的通道和沟渠
公开(公告)号：US08703604B2
公开(公告)日：2014-04-22
申请号：US13415164
申请日：2012-03-08
申请人： Shom Ponoth , David V. Horak , Takeshi Nogami , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Takeshi Nogami , Chih-Chao Yang
IPC分类号： H01L21/311 , H01L21/3065
CPC分类号： H01L23/5226 , H01L21/31116 , H01L21/768 , H01L21/76816 , H01L21/76829 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.
摘要翻译：本发明的实施例提供了一种创建具有不同长度的通孔和沟槽的方法。该方法包括在半导体结构的顶部上沉积多个电介质层，多个电介质层被至少一个蚀刻停止层隔开; 通过非选择性蚀刻工艺从所述多个电介质层的顶表面形成多个开口到多个介电层中，其中所述多个开口中的至少一个具有在所述蚀刻步骤层下方的深度; 以及通过选择性蚀刻工艺继续蚀刻多个开口，直到位于蚀刻停止层上方的多个开口的一个或多个开口到达和暴露蚀刻停止层。也提供了由此制成的半导体结构。

67. 发明授权

US08476160B2 Sublithographic patterning employing image transfer of a controllably damaged dielectric sidewall 失效
标题翻译：使用可控制损坏的电介质侧壁的图像转印的光刻图案
公开(公告)号：US08476160B2
公开(公告)日：2013-07-02
申请号：US12913116
申请日：2010-10-27
申请人： Shom Ponoth , David V. Horak , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Chih-Chao Yang
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L23/5226 , H01L21/02126 , H01L21/3105 , H01L21/31144 , H01L21/76802 , H01L21/76807 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A first low dielectric constant (low-k) dielectric material layer is lithographically patterned to form a recessed region having expose substantially vertical sidewalls, which are subsequently damaged to de-carbonize a surface portion at the sidewalls having a sublithographic width. A second low-k dielectric material layer is deposited to fill the recessed region and planarized to exposed top surfaces of the damaged low-k dielectric material portion. The damaged low-k dielectric material portion is removed selective to the first and second low-k dielectric material layers to form a trench with a sublithographic width. A portion of the pattern of the sublithographic-width trench is transferred into a metallic layer and optionally to an underlying dielectric masking material layer to define a trench with a sublithographic width, which can be employed as a template to confine the widths of via holes and line trenches to be subsequently formed in an interconnect-level dielectric material layer.
摘要翻译：第一低介电常数（低k）电介质材料层被光刻图案化以形成具有暴露基本上垂直侧壁的凹陷区域，其随后被损坏以使具有亚光刻宽度的侧壁处的表面部分脱碳。沉积第二低k电介质材料层以填充凹陷区域并平坦化到损坏的低k电介质材料部分的暴露的顶表面。选择性地去除损坏的低k电介质材料部分到第一和第二低k电介质材料层以形成具有亚光刻宽度的沟槽。亚光刻宽度沟槽的图案的一部分被转移到金属层中，并且可选地转移到下面的介电掩模材料层以限定具有亚光刻宽度的沟槽，其可以用作模板以限制通孔的宽度和随后在互连级介电材料层中形成线沟槽。

68. 发明授权

US08227339B2 Creation of vias and trenches with different depths 失效
标题翻译：创造不同深度的通道和沟渠
公开(公告)号：US08227339B2
公开(公告)日：2012-07-24
申请号：US12610624
申请日：2009-11-02
申请人： Shom Ponoth , David V. Horak , Takeshi Nogami , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Takeshi Nogami , Chih-Chao Yang
IPC分类号： H01L21/311 , H01L21/3065
CPC分类号： H01L23/5226 , H01L21/31116 , H01L21/768 , H01L21/76816 , H01L21/76829 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.
摘要翻译：本发明的实施例提供了一种创建具有不同长度的通孔和沟槽的方法。该方法包括在半导体结构的顶部上沉积多个电介质层，多个电介质层被至少一个蚀刻停止层隔开; 通过非选择性蚀刻工艺从所述多个电介质层的顶表面形成多个开口到多个介电层中，其中所述多个开口中的至少一个具有在所述蚀刻步骤层下方的深度; 以及通过选择性蚀刻工艺继续蚀刻多个开口，直到位于蚀刻停止层上方的多个开口的一个或多个开口到达和暴露蚀刻停止层。还提供了由此制成的半导体结构。

69. 发明授权

US08211776B2 Integrated circuit line with electromigration barriers 失效
标题翻译：集成电路线与电迁移障碍
公开(公告)号：US08211776B2
公开(公告)日：2012-07-03
申请号：US12652485
申请日：2010-01-05
申请人： David V. Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
发明人： David V. Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76847 , H01L21/76852 , H01L21/76885 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating an integrated circuit comprising an electromigration barrier in a line of the integrated circuit includes forming a spacer; forming a segmented line adjacent to opposing sides of the spacer, the segmented line formed from a first conductive material; removing the spacer to form an empty line break; and filling the empty line break with a second conductive material to form an electromigration barrier that isolates electromigration effects within individual segments of the segmented line. An integrated circuit comprising an electromigration barrier includes a line, the line comprising a first conductive material, the line further comprising a plurality of line segments separated by one or more electromigration barriers, wherein the one or more electromigration barriers comprise a second conductive material that isolates electromigration effects within individual segments of the line.
摘要翻译：一种用于制造集成电路的集成电路的方法，包括：集成电路的一行中的电迁移势垒包括形成间隔物; 形成与所述间隔物的相对侧相邻的分段线，所述分段线由第一导电材料形成; 移除间隔物以形成空线断裂; 并用第二导电材料填充空线断裂以形成电隔离屏蔽，其隔离分段线的各个段内的电迁移效应。包括电迁移屏障的集成电路包括线，该线包括第一导电材料，该线还包括由一个或多个电迁移屏障隔开的多个线段，其中所述一个或多个电迁移屏障包括隔离的第二导电材料线路各部分的电迁移效应。

70. 发明申请

US20110018093A1 PROGRAMMABLE ANTI-FUSE STRUCTURE WITH DLC DIELECTRIC LAYER 失效
标题翻译： DLC介电层可编程防结构
公开(公告)号：US20110018093A1
公开(公告)日：2011-01-27
申请号：US12509892
申请日：2009-07-27
申请人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5252 , H01L23/53276 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment an anti-fuse structure is provided that includes a first dielectric material having at least a first anti-fuse region and a second anti-fuse region, wherein at least one of the anti-fuse regions includes a conductive region embedded within the first dielectric material. The anti-fuse structure further includes a first diamond like carbon layer having a first conductivity located on at least the first dielectric material in the first anti-fuse region and a second diamond like carbon layer having a second conductivity located on at least the first dielectric material in the second anti-fuse region. In this embodiment, the second conductivity is different from the first conductivity and the first diamond like carbon layer and the second diamond like carbon layer have the same thickness. The anti-fuse structure also includes a second dielectric material located atop the first and second diamond like carbon layers. The second dielectric material includes at least one conductively filled region embedded therein.
摘要翻译：在一个实施例中，提供了一种抗熔丝结构，其包括具有至少第一抗熔融区域和第二抗熔融区域的第一电介质材料，其中至少一个反熔丝区域包括嵌入在该熔断区域内的导电区域第一电介质材料。反熔丝结构还包括第一金刚石碳层，其具有位于第一抗熔融区域中的至少第一电介质材料上的第一导电性，第二类金刚石碳层具有位于至少第一电介质上的第二导电性材料在第二个反熔丝区域。在本实施例中，第二导电率不同于第一导电性，第一类金刚石碳层和第二类金刚石碳层具有相同的厚度。反熔丝结构还包括位于第一和第二金刚石状碳层顶上的第二电介质材料。第二电介质材料包括嵌入其中的至少一个导电填充区域。

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