专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明申请

US20050062048A1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050062048A1
公开(公告)日：2005-03-24
申请号：US10947264
申请日：2004-09-23
申请人： Tetsuya Hayashi , Hideaki Tanaka , Masakatsu Hoshi , Saichirou Kaneko
发明人： Tetsuya Hayashi , Hideaki Tanaka , Masakatsu Hoshi , Saichirou Kaneko
IPC分类号： H01L21/04 , H01L29/24 , H01L29/267 , H01L29/78 , H01L21/338 , H01L31/0312
CPC分类号： H01L29/66068 , H01L29/1608 , H01L29/267 , H01L29/7828
摘要： An aspect of the present invention provides a semiconductor device that includes a first conductivity type semiconductor body, a source region in contact with the semiconductor body, whose bandgap is different from that of the semiconductor body, and which formed heterojunction with the semiconductor body, a gate insulating film in contact with a portion of junction between the source region and the semiconductor body, a gate electrode in contact with the gate insulating film, a source electrode, a low resistance region in contact with the source electrode and the source region, and connected ohmically with the source electrode, and a drain electrode connected ohmically with the semiconductor body.
摘要翻译：本发明的一个方面提供了一种半导体器件，其包括第一导电型半导体本体，与半导体本体接触的源极区域，其带隙与半导体本体的带隙不同，并且与半导体本体形成异质结，与栅极绝缘膜接触的栅电极，源电极，与源极电极和源极区域接触的低电阻区域，以及与源电极欧姆连接，以及与半导体主体欧姆连接的漏电极。

62. 发明授权

US07531396B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07531396B2
公开(公告)日：2009-05-12
申请号：US11374418
申请日：2006-03-14
申请人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka
发明人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka
IPC分类号： H01L21/338 , H01L21/066
CPC分类号： H01L29/66068 , H01L21/8213 , H01L29/0619 , H01L29/0623 , H01L29/0847 , H01L29/1608 , H01L29/267 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/7828
摘要： A method of manufacturing a semiconductor device is disclosed. The semiconductor device includes a semiconductor body of a first conductivity type, a hetero semiconductor region adjacent to one main surface of the semiconductor body and having a band gap different from that of the semiconductor body, and a gate electrode formed in a junction portion between the hetero semiconductor region and the semiconductor body through a gate insulating film. The method includes a first process of forming a predetermined trench by using a mask layer having a predetermined opening on one main surface side of the semiconductor body, a second process of forming a buried region adjacent to at least a side wall of the trench and so as to extend from the trench, a third process of forming a hetero semiconductor layer so as to adjoin the semiconductor body and the buried region, and a fourth process of forming the hetero semiconductor region by patterning the hetero semiconductor layer.
摘要翻译：公开了制造半导体器件的方法。半导体器件包括第一导电类型的半导体本体，与半导体本体的一个主表面相邻且具有与半导体本体不同的带隙的异质半导体区域，以及形成在该半导体器件之间的接合部分中的栅电极异质半导体区域和半导体本体通过栅极绝缘膜。该方法包括通过使用在半导体主体的一个主表面侧上具有预定开口的掩模层来形成预定沟槽的第一工艺，形成与沟槽的至少侧壁相邻的掩埋区域的第二工艺从沟槽延伸，形成与半导体本体和掩埋区相邻的异质半导体层的第三工序，以及通过图案化杂半导体层形成异质半导体区的第四工序。

63. 发明授权

US07183575B2 High reverse voltage silicon carbide diode and method of manufacturing the same high reverse voltage silicon carbide diode 有权
标题翻译：高反向电压碳化硅二极管和制造相同高反向碳化硅二极管的方法
公开(公告)号：US07183575B2
公开(公告)日：2007-02-27
申请号：US10368016
申请日：2003-02-19
申请人： Yoshio Shimoida , Saichirou Kaneko , Hideaki Tanaka , Masakatsu Hoshi , Kraisom Throngnumchai , Teruyoshi Mihara , Tetsuya Hayashi
发明人： Yoshio Shimoida , Saichirou Kaneko , Hideaki Tanaka , Masakatsu Hoshi , Kraisom Throngnumchai , Teruyoshi Mihara , Tetsuya Hayashi
IPC分类号： H01L29/15
CPC分类号： H01L29/267 , H01L29/1608 , H01L29/861
摘要： A high reverse voltage diode includes a hetero junction made up from a silicon carbide base layer, which constitutes a first semiconductor base layer, and a polycrystalline silicon layer, which constitutes a second semiconductor layer, and whose band gap is different from that of the silicon carbide base layer. A low concentration N type polycrystalline silicon layer is deposited on a first main surface side of the silicon carbide base layer, and a metal electrode is formed on a second main surface side of the silicon carbide base layer which is opposite to the first main surface side thereof.
摘要翻译：高反向电压二极管包括由构成第一半导体基底层的碳化硅基底层和构成第二半导体层的多晶硅层构成的异质结，并且其带隙与硅的带隙不同碳化物基层。在碳化硅基底层的第一主表面侧沉积低浓度N型多晶硅层，在与第一主表面侧相反的碳化硅基底层的第二主表面侧上形成金属电极其中。

64. 发明授权

US07173307B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07173307B2
公开(公告)日：2007-02-06
申请号：US10947264
申请日：2004-09-23
申请人： Tetsuya Hayashi , Hideaki Tanaka , Masakatsu Hoshi , Saichirou Kaneko
发明人： Tetsuya Hayashi , Hideaki Tanaka , Masakatsu Hoshi , Saichirou Kaneko
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/66068 , H01L29/1608 , H01L29/267 , H01L29/7828
摘要： An aspect of the present invention provides a semiconductor device that includes a first conductivity type semiconductor body, a source region in contact with the semiconductor body, whose bandgap is different from that of the semiconductor body, and which formed heterojunction with the semiconductor body, a gate insulating film in contact with a portion of junction between the source region and the semiconductor body, a gate electrode in contact with the gate insulating film, a source electrode, a low resistance region in contact with the source electrode and the source region, and connected ohmically with the source electrode, and a drain electrode connected ohmically with the semiconductor body.
摘要翻译：本发明的一个方面提供了一种半导体器件，其包括第一导电型半导体本体，与半导体本体接触的源极区域，其带隙与半导体本体的带隙不同，并且与半导体本体形成异质结，与栅极绝缘膜接触的栅电极，源电极，与源极电极和源极区域接触的低电阻区域，以及与源电极欧姆连接，以及与半导体主体欧姆连接的漏电极。

65. 发明授权

US07151280B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07151280B2
公开(公告)日：2006-12-19
申请号：US11012205
申请日：2004-12-16
申请人： Tetsuya Hayashi , Masakatsu Hoshi , Saichirou Kaneko , Hideaki Tanaka
发明人： Tetsuya Hayashi , Masakatsu Hoshi , Saichirou Kaneko , Hideaki Tanaka
IPC分类号： H01L31/0312 , H01L31/072 , H01L31/109 , H01L31/0328 , H01L31/0336
CPC分类号： H01L29/7806 , H01L29/1608 , H01L29/165 , H01L29/47 , H01L29/66068 , H01L29/7802 , H01L29/7803 , H01L29/7813 , H01L29/7817 , H01L29/782 , H01L29/7828
摘要： A semiconductor device includes a heterojunction semiconductor region 9, which forms a heterojunction with a drain region 2. The heterojunction semiconductor region 9 is connected to a source electrode 7, and has a band gap different from a band gap of a semiconductor substrate constituting the drain region 2. It is possible to set the size of an energy barrier against conduction electrons, which is formed between the drain region 2 and the heterojunction semiconductor region 9, into a desired size by changing the conductivity type or the impurity density of the heterojunction semiconductor region 9. This is a characteristic not found in a Schottky junction, in which the size of the energy barrier is inherently determined by a work function of a metal material. It is easy to achieve optimal design of a passive element in response to a withstand voltage system of a MOSFET as a switching element. It is also possible to suppress diffusion potential in a reverse conduction mode and to improve a degree of integration per unit area. As a result, it is possible to reduce the size of elements and to simplify manufacturing processes thereof.
摘要翻译：半导体器件包括异质结半导体区域9，其与漏极区域2形成异质结。异质结半导体区域9连接到源电极7，并且具有与构成漏极的半导体衬底的带隙不同的带隙可以通过改变异质结半导体的导电类型或杂质浓度来将能量势垒的大小与形成在漏极区域2和异质结半导体区域9之间的传导电子设置成所需的尺寸这是肖特基结中没有发现的特征，其中能量势垒的尺寸固有地由金属材料的功函数决定。响应MOSFET的耐压系统作为开关元件，很容易实现无源元件的最佳设计。也可以抑制反向导通模式的扩散电位，提高单位面积的积分度。结果，可以减小元件的尺寸并简化其制造工艺。

66. 发明申请

US20060208261A1 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060208261A1
公开(公告)日：2006-09-21
申请号：US11438347
申请日：2006-05-23
申请人： Saichirou Kaneko , Masakatsu Hoshi , Yoshinori Murakami , Tetsuya Hayashi , Hideaki Tanaka
发明人： Saichirou Kaneko , Masakatsu Hoshi , Yoshinori Murakami , Tetsuya Hayashi , Hideaki Tanaka
IPC分类号： H01L31/0312
CPC分类号： H01L29/1608 , H01L29/1004 , H01L29/6606 , H01L29/66068 , H01L29/66234 , H01L29/7322 , H01L29/861
摘要： A high voltage semiconductor device having a high current gain hFE is formed with a collector region (20) of a first conduction type, an emitter region (40) of the first conduction type, and a base region (30) of a second conduction type opposite to the first conduction type located between the collector region and the emitter region. The free carrier density of the base region (30) where no depletion layer is formed is smaller than the space charge density of a depletion layer formed in the base region (30).
摘要翻译：具有高电流增益hFE的高电压半导体器件由第一导电类型的集电极区域（20），第一导电类型的发射极区域（40）和第二导电类型的基极区域（30）形成与位于集电极区域和发射极区域之间的第一导电类型相反。没有形成耗尽层的基极区域（30）的自由载流子密度小于形成在基极区域（30）中的耗尽层的空间电荷密度。

67. 发明申请

US20050224838A1 Semiconductor device with heterojunction 审中-公开
标题翻译：具有异质结的半导体器件
公开(公告)号：US20050224838A1
公开(公告)日：2005-10-13
申请号：US11095528
申请日：2005-04-01
申请人： Hideaki Tanaka , Masakatsu Hoshi , Tetsuya Hayashi
发明人： Hideaki Tanaka , Masakatsu Hoshi , Tetsuya Hayashi
IPC分类号： H01L29/161 , H01L27/04 , H01L27/07 , H01L29/12 , H01L29/165 , H01L29/24 , H01L29/78 , H01L29/861 , H01L29/735
CPC分类号： H01L29/165 , H01L29/267 , H01L29/7827 , H01L29/861
摘要： An aspect of the present invention provides a semiconductor device that includes a semiconductor base essentially made of a first semiconductor material of a first conductivity type, a hetero-semiconductor region essentially made of a second semiconductor material whose band gap is different from that of the first semiconductor material, formed on the semiconductor base, and forming a heterojunction with the semiconductor base, a cathode electrode formed in contact with the semiconductor base, and an anode electrode formed in contact with the hetero-semiconductor region, wherein the first semiconductor material is a silicon-carbide (SiC) single crystal and the heterojunction is formed on a {0001-} crystal face of the silicon-carbide single crystal.
摘要翻译：本发明的一个方面提供一种半导体器件，其包括基本上由第一导电类型的第一半导体材料制成的半导体基底，基本由第二半导体材料制成的异质半导体区域，该第二半导体区域的带隙与第一半导体材料的带隙不同半导体材料形成在半导体基底上，并与半导体基底形成异质结，形成为与半导体基底接触的阴极电极以及与异质半导体区域接触形成的阳极电极，其中第一半导体材料为碳化硅（SiC）单晶，并且在碳化硅单晶的{0001-}晶面上形成异质结。

68. 发明申请

US20050199873A1 Semiconductor device with heterojunction 有权
标题翻译：具有异质结的半导体器件
公开(公告)号：US20050199873A1
公开(公告)日：2005-09-15
申请号：US11068803
申请日：2005-03-02
申请人： Hideaki Tanaka , Masakatsu Hoshi , Tetsuya Hayashi
发明人： Hideaki Tanaka , Masakatsu Hoshi , Tetsuya Hayashi
IPC分类号： H01L29/78 , H01L21/336 , H01L29/06 , H01L29/12 , H01L29/24 , H01L29/267 , H01L29/47 , H01L29/732 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/7828 , H01L29/0619 , H01L29/267 , H01L29/47 , H01L29/7813 , H01L29/7827
摘要： An aspect of the present invention provides a semiconductor device that includes a semiconductor base made of a first semiconductor material of a first conductivity type, a hetero-semiconductor region forming a heterojunction with the semiconductor base and made of a second semiconductor material having a different band gap from the first semiconductor material, a first gate electrode arranged in the vicinity of the heterojunction, a first gate insulating film configured to insulate the first gate electrode from the semiconductor base, a source electrode formed in contact with the hetero-semiconductor region, a dram electrode formed in contact with the semiconductor base, and an electric field extending region partly facing the first gate electrode, the first gate insulating film and hetero-semiconductor region interposed between the electric field extending region and the first gate electrode, the electric field extending region extending a built-in electric field into the hetero-semiconductor region.
摘要翻译：本发明的一个方面提供了一种半导体器件，其包括由第一导电类型的第一半导体材料制成的半导体基底，与半导体基底形成异质结的异质半导体区域，并由具有不同带的第二半导体材料制成与第一半导体材料的间隙，布置在异质结附近的第一栅电极，配置为使第一栅电极与半导体基底绝缘的第一栅极绝缘膜，与异半导体区域接触形成的源极，形成为与半导体基底接触的电极电极，以及部分地面对第一栅电极的电场延伸区域，插入在电场延伸区域和第一栅电极之间的第一栅极绝缘膜和异质半导体区域，电场延伸区域将内置电场扩展到异半半导体导体区域。

69. 发明授权

US07378325B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07378325B2
公开(公告)日：2008-05-27
申请号：US11438347
申请日：2006-05-23
申请人： Saichirou Kaneko , Masakatsu Hoshi , Yoshinori Murakami , Tetsuya Hayashi , Hideaki Tanaka
发明人： Saichirou Kaneko , Masakatsu Hoshi , Yoshinori Murakami , Tetsuya Hayashi , Hideaki Tanaka
IPC分类号： H01L21/331
CPC分类号： H01L29/1608 , H01L29/1004 , H01L29/6606 , H01L29/66068 , H01L29/66234 , H01L29/7322 , H01L29/861
摘要： A high voltage semiconductor device having a high current gain hFE is formed with a collector region (20) of a first conduction type, an emitter region (40) of the first conduction type, and a base region (30) of a second conduction type opposite to the first conduction type located between the collector region and the emitter region. The free carrier density of the base region (30) where no depletion layer is formed is smaller than the space charge density of a depletion layer formed in the base region (30).
摘要翻译：具有高电流增益hFE的高电压半导体器件由第一导电类型的集电极区域（20），第一导电类型的发射极区域（40）和第二导电类型的基极区域（30）形成与位于集电极区域和发射极区域之间的第一导电类型相反。没有形成耗尽层的基极区域（30）的自由载流子密度小于形成在基极区域（30）中的耗尽层的空间电荷密度。

70. 发明申请

US20070218596A1 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20070218596A1
公开(公告)日：2007-09-20
申请号：US11374418
申请日：2006-03-14
申请人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka
发明人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka
IPC分类号： H01L21/8232 , H01L21/335
CPC分类号： H01L29/66068 , H01L21/8213 , H01L29/0619 , H01L29/0623 , H01L29/0847 , H01L29/1608 , H01L29/267 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/7828
摘要： A method of manufacturing a semiconductor device is disclosed. The semiconductor device includes a semiconductor body of a first conductivity type, a hetero semiconductor region adjacent to one main surface of the semiconductor body and having a band gap different from that of the semiconductor body, and a gate electrode formed in a junction portion between the hetero semiconductor region and the semiconductor body through a gate insulating film. The method includes a first process of forming a predetermined trench by using a mask layer having a predetermined opening on one main surface side of the semiconductor body, a second process of forming a buried region adjacent to at least a side wall of the trench and so as to extend from the trench, a third process of forming a hetero semiconductor layer so as to adjoin the semiconductor body and the buried region, and a fourth process of forming the hetero semiconductor region by patterning the hetero semiconductor layer.
摘要翻译：公开了制造半导体器件的方法。半导体器件包括第一导电类型的半导体本体，与半导体本体的一个主表面相邻且具有与半导体本体不同的带隙的异质半导体区域，以及形成在该半导体器件之间的接合部分中的栅电极异质半导体区域和半导体本体通过栅极绝缘膜。该方法包括通过使用在半导体主体的一个主表面侧上具有预定开口的掩模层来形成预定沟槽的第一工艺，形成与沟槽的至少侧壁相邻的掩埋区域的第二工艺从沟槽延伸，形成与半导体本体和掩埋区相邻的异质半导体层的第三工序，以及通过图案化杂半导体层形成异质半导体区的第四工序。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式