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1. 发明申请

US20060208261A1 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060208261A1
公开(公告)日：2006-09-21
申请号：US11438347
申请日：2006-05-23
申请人： Saichirou Kaneko , Masakatsu Hoshi , Yoshinori Murakami , Tetsuya Hayashi , Hideaki Tanaka
发明人： Saichirou Kaneko , Masakatsu Hoshi , Yoshinori Murakami , Tetsuya Hayashi , Hideaki Tanaka
IPC分类号： H01L31/0312
CPC分类号： H01L29/1608 , H01L29/1004 , H01L29/6606 , H01L29/66068 , H01L29/66234 , H01L29/7322 , H01L29/861
摘要： A high voltage semiconductor device having a high current gain hFE is formed with a collector region (20) of a first conduction type, an emitter region (40) of the first conduction type, and a base region (30) of a second conduction type opposite to the first conduction type located between the collector region and the emitter region. The free carrier density of the base region (30) where no depletion layer is formed is smaller than the space charge density of a depletion layer formed in the base region (30).
摘要翻译：具有高电流增益hFE的高电压半导体器件由第一导电类型的集电极区域（20），第一导电类型的发射极区域（40）和第二导电类型的基极区域（30）形成与位于集电极区域和发射极区域之间的第一导电类型相反。没有形成耗尽层的基极区域（30）的自由载流子密度小于形成在基极区域（30）中的耗尽层的空间电荷密度。

2. 发明授权

US07378325B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07378325B2
公开(公告)日：2008-05-27
申请号：US11438347
申请日：2006-05-23
申请人： Saichirou Kaneko , Masakatsu Hoshi , Yoshinori Murakami , Tetsuya Hayashi , Hideaki Tanaka
发明人： Saichirou Kaneko , Masakatsu Hoshi , Yoshinori Murakami , Tetsuya Hayashi , Hideaki Tanaka
IPC分类号： H01L21/331
CPC分类号： H01L29/1608 , H01L29/1004 , H01L29/6606 , H01L29/66068 , H01L29/66234 , H01L29/7322 , H01L29/861
摘要： A high voltage semiconductor device having a high current gain hFE is formed with a collector region (20) of a first conduction type, an emitter region (40) of the first conduction type, and a base region (30) of a second conduction type opposite to the first conduction type located between the collector region and the emitter region. The free carrier density of the base region (30) where no depletion layer is formed is smaller than the space charge density of a depletion layer formed in the base region (30).
摘要翻译：具有高电流增益hFE的高电压半导体器件由第一导电类型的集电极区域（20），第一导电类型的发射极区域（40）和第二导电类型的基极区域（30）形成与位于集电极区域和发射极区域之间的第一导电类型相反。没有形成耗尽层的基极区域（30）的自由载流子密度小于形成在基极区域（30）中的耗尽层的空间电荷密度。

3. 发明授权

US07071536B2 Semiconductor device and manufacturing method thereof 失效
公开(公告)号：US07071536B2
公开(公告)日：2006-07-04
申请号：US10772283
申请日：2004-02-06
申请人： Saichirou Kaneko , Masakatsu Hoshi , Yoshinori Murakami , Tetsuya Hayashi , Hideaki Tanaka
发明人： Saichirou Kaneko , Masakatsu Hoshi , Yoshinori Murakami , Tetsuya Hayashi , Hideaki Tanaka
IPC分类号： H01L27/082
CPC分类号： H01L29/1608 , H01L29/1004 , H01L29/6606 , H01L29/66068 , H01L29/66234 , H01L29/7322 , H01L29/861
摘要： A high voltage semiconductor device having a high current gain hFE is formed with a collector region (20) of a first conduction type, an emitter region (40) of the first conduction type, and a base region (30) of a second conduction type opposite to the first conduction type located between the collector region and the emitter region. The free carrier density of the base region (30) where no depletion layer is formed is smaller than the space charge density of a depletion layer formed in the base region (30).

4. 发明授权

US5994754A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5994754A
公开(公告)日：1999-11-30
申请号：US3463
申请日：1998-01-05
申请人： Tetsuya Hayashi , Yoshinori Murakami
发明人： Tetsuya Hayashi , Yoshinori Murakami
IPC分类号： H01L29/06 , H01L29/70
CPC分类号： H01L29/0615
摘要： A multi guard ring structure for a reach-through type semiconductor device has at least first and second guard ring regions. The first guard ring region surrounds a main region with a predetermined first spacing. The second guard ring region surrounds the first guard ring region with a predetermined second spacing. To improve the ability to withstand reverse bias voltage, the second spacing between the first and second guard ring regions is made smaller than the first spacing between the main region and the first guard ring region in order that a maximum value of an electric field strength at a junction between the first guard ring region and the drift region may be equal to or lower than 85% of a maximum value of a field strength at the main junction at the avalanche breakdown condition of the main junction.
摘要翻译：用于到达型半导体器件的多保护环结构具有至少第一和第二保护环区域。第一保护环区域以预定的第一间隔围绕主区域。第二保护环区域以预定的第二间隔围绕第一保护环区域。为了提高抵抗反向偏置电压的能力，第一和第二保护环区域之间的第二间隔被制成小于主区域和第一保护环区域之间的第一间隔，以便使得电场强度的最大值在第一保护环区域和漂移区域之间的结点可以等于或低于主结点处的雪崩击穿条件下的主结点处的场强的最大值的85％。

5. 发明申请

US20060022307A1 Semiconductor package 失效
公开(公告)号：US20060022307A1
公开(公告)日：2006-02-02
申请号：US11189886
申请日：2005-07-27
申请人： Yoshinori Murakami
发明人： Yoshinori Murakami
IPC分类号： H01L27/108
CPC分类号： H01L23/051 , H01L23/3735 , H01L2224/291 , H01L2224/32245 , H01L2224/33181 , H01L2924/014
摘要： A semiconductor package has: a semiconductor chip having first and second main electrodes arranged on two principal surfaces being opposite to each other; a first main wiring plate connected to the first main electrode and having a first external connection terminal; a second main wiring plate connected to the second main electrode and having a second external connection terminal; a first shell connected through an insulating film to at least a part of a second principal surface of the first main wiring plate, the second principal surface of the first main wiring plate being opposite to a first principal surface of the first main wiring plate that is connected to the first electrode; and a second shell connected through an insulating film to at least a part of a second principal surface of the second main wiring plate, the second principal surface of the second main wiring plate being opposite to a first principal surface of the second main wiring plate that is connected to the second electrode. The first principal surfaces of the first and second main wiring plates are adjacent to and parallel to each other except at the locations where the first and second main wiring plates are connected to the semiconductor chip and the locations where the first and second external connection terminals are formed.

6. 发明申请

US20050259884A1 Image processing apparatus, image forming apparatus, image processing method, program, and recording medium 审中-公开
标题翻译：图像处理装置，图像形成装置，图像处理方法，程序和记录介质
公开(公告)号：US20050259884A1
公开(公告)日：2005-11-24
申请号：US11130179
申请日：2005-05-17
申请人： Yoshinori Murakami , Hitoshi Hirohata
发明人： Yoshinori Murakami , Hitoshi Hirohata
IPC分类号： G06K9/36 , H04N1/405
CPC分类号： H04N1/4052
摘要： A quantization error calculation portion calculates the difference between the pixel value of a pixel of an input image added with an accumulative error by the adder and the quantization value obtained by quantizing the pixel value in the quantization processing portion as a quantization error. The quantization error is stored in the error storage portion. The multiplier multiplies, a quantization error to be distributed to a subsequently-quantized pixel, among the quantization errors stored in the error storage portion, by the diffusion coefficient numerator value corresponding to the quantization error. The adder adds the multiplication result produced by the multiplier. The divider divides the addition result produced by the adder by the diffusion coefficient denominator value. The division result is outputted to the adder as an accumulative error for a subsequently-quantized pixel.
摘要翻译：量化误差计算部分计算由加法器添加的累积误差的输入图像的像素的像素值与通过量化量化处理部分中的像素值量化的量化值之间的差作为量化误差。量化误差被存储在错误存储部分中。通过与量化误差对应的扩散系数分子值，乘法器将存储在误差存储部分中的量化误差中的乘法器乘以要分配给后续量化像素的量化误差。加法器加上由乘法器产生的相乘结果。分频器将加法器产生的相加结果除以扩散系数分母值。分割结果作为后续量化像素的累积误差输出到加法器。

7. 发明授权

US06930333B2 Semiconductor device wiring structure 有权
公开(公告)号：US06930333B2
公开(公告)日：2005-08-16
申请号：US10883973
申请日：2004-07-06
申请人： Yoshinori Murakami
发明人： Yoshinori Murakami
IPC分类号： H01L23/00 , H01L23/48 , H01L23/495 , H01L23/498 , H01L29/417 , H01L29/74
CPC分类号： H01L23/49861 , H01L23/49562 , H01L24/45 , H01L24/48 , H01L24/49 , H01L29/41716 , H01L2224/05599 , H01L2224/16 , H01L2224/45124 , H01L2224/48091 , H01L2224/48472 , H01L2224/4903 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H01L2924/16152 , H01L2924/30107 , H01L2924/3025 , H01L2924/00 , H01L2924/00015 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device wiring structure is provided to reduce the wiring inductance and curtail the generation of interfering electromagnetic waves. A semiconductor chip having an anode electrode and a cathode electrode provided on two oppositely-facing main surfaces is sandwiched between a sheet-shaped anode wiring and a sheet-shaped cathode wiring. The anode and cathode electrodes of the semiconductor chip are connected to the anode and the cathode wirings, respectively, arranged such that the electric currents flowing there-through flow in opposite directions. A conductive substrate having a main surface with a larger width than the cathode wiring is disposed adjacent to the anode wiring. The edges of the cathode wiring protrude beyond the edges of both the anode wiring and the semiconductor chip in all locations and the dimension of the protrusion is at least one half of the distance from the edge of the cathode wiring to the metal substrate.

8. 发明申请

US20050121783A1 Semiconductor device mounting structure 失效
标题翻译：半导体器件安装结构
公开(公告)号：US20050121783A1
公开(公告)日：2005-06-09
申请号：US10998990
申请日：2004-11-30
申请人： Yoshinori Murakami
发明人： Yoshinori Murakami
IPC分类号： H01L23/34 , H01L23/367 , H01L23/538 , H02M7/04 , H02M7/48 , H01L23/495
CPC分类号： H01L23/5386 , F28D15/0233 , H01L23/367 , H01L23/3677 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device mounting structure includes a bus bar of which a first end part is connected to a high-temperature power-purpose semiconductor device and a second end is connected to another device that is required to be kept at a lower temperature than the semiconductor device. The bus bar includes a ribbonlike part zigzagging between the first and second ends. The ribbonlike part of the bus bar can improve the cooling effect by increasing the length of the path through which the heat travels in the lengthwise direction of the bus bar. Thus, the heat emitted from the semiconductor device is prevented from being transferred to a peripheral circuit element through the bus bar used for supplying electric power to the circuit element from the semiconductor device.
摘要翻译：半导体器件安装结构包括母线，第一端部连接到高温电力半导体器件，第二端连接到需要保持在比半导体器件低的温度的另一器件。母线包括在第一和第二端之间曲折的带状部分。汇流条的带状部分可以通过增加热量在汇流条的长度方向上行进的路径的长度来改善冷却效果。因此，防止从半导体器件发出的热量通过用于从半导体器件向电路元件供电的汇流条传送到外围电路元件。

9. 发明授权

US06828506B2 Wiring structure 失效
标题翻译：接线结构
公开(公告)号：US06828506B2
公开(公告)日：2004-12-07
申请号：US10445037
申请日：2003-05-27
申请人： Yoshinori Murakami
发明人： Yoshinori Murakami
IPC分类号： H01B708
CPC分类号： H05K1/0216 , H01L23/5383 , H01L25/072 , H01L2924/0002 , H05K2201/09672 , H05K2201/09727 , H01L2924/00
摘要： A wiring or electrode structure is configured to reduce the wiring inductance of the power conductors in a semiconductor power module and prevent as much as possible the emission of interference electromagnetic waves. The wiring or electrode structure has an insulation layer that faces a main surface of a conductive base layer, a first conductor that faces the surface of the insulation layer, and a second conductor through which current flows in the opposite direction as the current that flows in the first conductor. The second electrical conductor overlying the first electrical conductor such opposite longitudinal edges of the second electrical conductor extend beyond corresponding longitudinal edges of the first electrical conductor at all locations by predetermined distances.
摘要翻译：布线或电极结构被配置为减少半导体功率模块中的电力导体的布线电感，并尽可能地防止干扰电磁波的发射。布线或电极结构具有面向导电基底层的主表面的绝缘层，面向绝缘层的表面的第一导体和电流沿相反方向流动的第二导体，作为流过电流的电流第一个指挥。覆盖第一电导体的第二电导体，第二电导体的相对纵向边缘延伸超过所有位置处第一电导体的相应纵向边缘预定距离。

10. 发明授权

US06641407B2 Conductor interconnect structure connecting circuit boards 失效
标题翻译：导体互连结构连接电路板
公开(公告)号：US06641407B2
公开(公告)日：2003-11-04
申请号：US09955302
申请日：2001-09-19
申请人： Yoshinori Murakami
发明人： Yoshinori Murakami
IPC分类号： H01R1200
CPC分类号： H05K3/368 , H01L2224/48091 , H01L2224/49111 , H01L2924/13091 , H01R12/52 , H05K1/0216 , H05K1/145 , H05K1/148 , H05K1/162 , H05K3/36 , H05K2201/0792 , H05K2201/09672 , H05K2201/1028 , H05K2201/10818 , H05K2201/10893 , H01L2924/00014 , H01L2924/00
摘要： An interconnect structure has a plurality of planar interconnects (1, 2) mutually superposed with a prescribed distance therebetween and serving as interconnects between two circuit boards (A, B), each of the planar interconnects (1, 2) having at least two connection terminals (1A, 1B, 2A, 2B) at the circuit boards (1, 2). Rather than using rigid wire interconnects as done in the past to make interconnections, planar interconnects having relatively large surface areas are used to increase the line-to-line capacitance, thereby enhancing the filtering function that reduces high-frequency noise.
摘要翻译：互连结构具有多个平面互连（1,2），它们之间以规定距离相互重叠并且用作两个电路板（A，B）之间的互连，每个平面互连（1,2）具有至少两个连接电路板（1,2）上的端子（1A，1B，2A，2B）。不像以前那样使用刚性的电线互连来做互连，而是使用具有相对大的表面积的平面互连来增加线对线电容，从而增强降低高频噪声的滤波功能。

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