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61. 发明申请

US20080166878A1 Silicon nanostructures and fabrication thereof 审中-公开
标题翻译：硅纳米结构及其制造
公开(公告)号：US20080166878A1
公开(公告)日：2008-07-10
申请号：US11651242
申请日：2007-01-08
申请人： Tingkai Li , Bruce D. Ulrich , Jer-Shen Maa , Sheng Teng Hsu
发明人： Tingkai Li , Bruce D. Ulrich , Jer-Shen Maa , Sheng Teng Hsu
IPC分类号： H01L21/306
CPC分类号： H01L21/31111 , B81C1/00111 , H01L21/3065 , H01L21/31122
摘要： A method of fabricating silicon nanostructures includes preparing a silicon wafer as a substrate; forming an oxide layer hardmask directly on the silicon substrate; patterning and etching the oxide hardmask; wet etching the silicon wafer to remove oxide to reduce the size of the oxide hardmask and to form nanostructure elements; and dry etching, in one or more steps, the silicon wafer using the oxide hardmask to form a desired nanostructure having substantially parallel vertical sidewalls thereon.
摘要翻译：制造硅纳米结构的方法包括制备硅晶片作为基底; 在硅衬底上直接形成氧化层硬掩模; 图案化和蚀刻氧化物硬掩模; 湿蚀刻硅晶片以除去氧化物以减小氧化物硬掩模的尺寸并形成纳米结构元件; 以及使用氧化物硬掩模在一个或多个步骤中干蚀刻硅晶片以形成其上具有基本上平行的垂直侧壁的所需纳米结构。

62. 发明申请

US20080164577A1 Patterned silicon submicron tubes 失效
标题翻译：图案硅亚微米管
公开(公告)号：US20080164577A1
公开(公告)日：2008-07-10
申请号：US11649634
申请日：2007-01-04
申请人： Tingkai Li , Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu
发明人： Tingkai Li , Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu
IPC分类号： H01L21/3065 , H01L29/06
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/306 , H01L29/0669 , H01L29/0673 , Y10S977/743
摘要： An array of submicron silicon (Si) tubes is provided with a method for patterning submicron Si tubes. The method provides a Si substrate, and forms a silicon dioxide film overlying the Si substrate. An array of silicon dioxide rods is formed from the silicon dioxide film, and Si3N4 tubes are formed surrounding the silicon dioxide rods. The silicon dioxide rods are etched away. Then, exposed regions of the Si substrate are etched, forming Si tubes underlying the Si3N4 tubes. Finally, the Si3N4 tubes are removed.
摘要翻译：亚微米硅（Si）管的阵列具有用于构图亚微米Si管的方法。该方法提供Si衬底，并形成覆盖Si衬底的二氧化硅膜。由二氧化硅膜形成二氧化硅棒的阵列，并且在二氧化硅棒周围形成Si 3 N 4 N 4管。二氧化硅棒被蚀刻掉。然后，蚀刻Si衬底的暴露区域，形成Si 3 N 4 N 4管子下面的Si管。最后，去除Si 3 N 4 N 4管。

63. 发明授权

US07364665B2 Selective etching processes of SiO2 , Ti and In2 O3 thin films for FeRAM device applications 失效
标题翻译：用于FeRAM器件应用的SiO2，Ti和In2 O3薄膜的选择性蚀刻工艺
公开(公告)号：US07364665B2
公开(公告)日：2008-04-29
申请号：US10970885
申请日：2004-10-21
申请人： Tingkai Li , Bruce D. Ulrich , David R. Evans , Sheng Teng Hsu
发明人： Tingkai Li , Bruce D. Ulrich , David R. Evans , Sheng Teng Hsu
IPC分类号： B44C1/22 , C03C15/00 , C03C25/68 , C23F1/00
CPC分类号： H01L29/6684 , C23F4/00 , H01L21/28291 , H01L21/31116 , H01L21/32136
摘要： A method of selectively etching a three-layer structure consisting of SiO2, In2O3, and titanium, includes etching the SiO2, stopping at the titanium layer, using C3F8 in a range of between about 10 sccm to 30 sccm; argon in a range of between about 20 sccm to 40 sccm, using an RF source in a range of between about 1000 watts to 3000 watts and an RF bias in a range of between about 400 watts to 800 watts at a pressure in a range of between about 2 mtorr to 6 mtorr; and etching the titanium, stopping at the In2O3 layer, using BCl in a range of between about 10 sccm to 50 sccm; chlorine in a range of between about 40 sccm to 80 sccm, a Tcp in a range of between about 200 watts to 500 watts at an RF bias in a range of between about 100 watts to 200 watts at a pressure in a range of between about 4 mtorr to 8 mtorr.
摘要翻译：选择性地蚀刻由SiO 2，In 2 O 3 N 3和Ti构成的三层结构的方法包括蚀刻SiO _{2 ，在钛层上停止，使用C 3 3 F 8 N在约10sccm至30sccm之间; 在约20sccm至40sccm的范围内的氩气，使用在约1000瓦特至3000瓦特之间的范围内的RF源和在约400瓦特至800瓦特范围内的RF偏压，约2mtorr至6mtorr; 并且使用在约10sccm至50sccm之间的范围内的BCl蚀刻钛，停止在In 2 N 3 O 3层处; 在约40sccm至80sccm的范围内的氯，在约200瓦特至200瓦特之间的RF偏压下在约200瓦特至500瓦特之间的范围内的T cp < 在约4mtorr至8mtorr的范围内的压力。}

64. 发明授权

US07338907B2 Selective etching processes of silicon nitride and indium oxide thin films for FeRAM device applications 失效
标题翻译：用于FeRAM器件应用的氮化硅和氧化铟薄膜的选择性蚀刻工艺
公开(公告)号：US07338907B2
公开(公告)日：2008-03-04
申请号：US10958537
申请日：2004-10-04
申请人： Tingkai Li , Sheng Teng Hsu , Bruce D. Ulrich , Mark A. Burgholzer , Ray A. Hill
发明人： Tingkai Li , Sheng Teng Hsu , Bruce D. Ulrich , Mark A. Burgholzer , Ray A. Hill
IPC分类号： H01L21/311
CPC分类号： H01L21/31116 , H01L29/6684 , H01L29/78391
摘要： A dry etch process is described for selectively etching silicon nitride from conductive oxide material for use in a semiconductor fabrication process. Adding an oxidant in the etch gas mixture could increase the etch rate for the silicon nitride while reducing the etch rate for the conductive oxide, resulting in improving etch selectivity. The disclosed selective etch process is well suited for ferroelectric memory device fabrication using conductive oxide/ferroelectric interface having silicon nitride as the encapsulated material for the ferroelectric.
摘要翻译：描述了一种干蚀刻工艺，用于从用于半导体制造工艺的导电氧化物材料中选择性地蚀刻氮化硅。在蚀刻气体混合物中添加氧化剂可以增加氮化硅的蚀刻速率，同时降低导电氧化物的蚀刻速率，从而提高蚀刻选择性。所公开的选择性蚀刻工艺非常适合于使用具有氮化硅作为铁电体的封装材料的导电氧化物/铁电界面的铁电存储器件制造。

65. 发明授权

US07259055B2 Method of forming high-luminescence silicon electroluminescence device 失效
标题翻译：形成高发光硅电致发光器件的方法
公开(公告)号：US07259055B2
公开(公告)日：2007-08-21
申请号：US11066713
申请日：2005-02-24
申请人： Tingkai Li , Pooran Chandra Joshi , Wei Gao , Yoshi Ono , Sheng Teng Hsu
发明人： Tingkai Li , Pooran Chandra Joshi , Wei Gao , Yoshi Ono , Sheng Teng Hsu
IPC分类号： H01L21/8238
CPC分类号： H01L31/03046 , Y02E10/544 , Y02P70/521
摘要： A method for forming a high-luminescence Si electroluminescence (EL) phosphor is provided, with an EL device made from the Si phosphor. The method comprises: depositing a silicon-rich oxide (SRO) film, with Si nanocrystals, having a refractive index in the range of 1.5 to 2.1, and a porosity in the range of 5 to 20%; and, post-annealing the SRO film in an oxygen atmosphere. DC-sputtering or PECVD processes can be used to deposit the SRO film. In one aspect the method further comprises: HF buffered oxide etching (BOE) the SRO film; and, re-oxidizing the SRO film, to form a SiO2 layer around the Si nanocrystals in the SRO film. In one aspect, the SRO film is re-oxidized by annealing in an oxygen atmosphere. In this manner, a layer of SiO2 is formed around the Si nanocrystals having a thickness in the range of 1 to 5 nanometers (nm).
摘要翻译：提供一种用于形成高发光Si电致发光（EL）荧光体的方法，其具有由Si荧光体制成的EL器件。该方法包括：用Si纳米晶体沉积富含氧的氧化物（SRO）膜，折射率在1.5至2.1范围内，孔隙率在5至20％的范围内; 并且在氧气氛中对SRO膜进行后退火。 DC溅射或PECVD工艺可用于沉积SRO膜。在一个方面，该方法还包括：HF缓冲氧化物蚀刻（BOE）SRO膜; 并且再次氧化SRO膜，以在SRO膜中的Si纳米晶体周围形成SiO 2层。在一个方面，SRO膜通过在氧气气氛中退火再次氧化。以这种方式，在具有1至5纳米（nm）范围内的厚度的Si纳米晶体周围形成SiO 2层。

66. 发明授权

US07008801B2 Method of forming ferroelectric thin films on a high-k layer 失效
公开(公告)号：US07008801B2
公开(公告)日：2006-03-07
申请号：US10453831
申请日：2003-06-02
申请人： Tingkai Li , Sheng Teng Hsu
发明人： Tingkai Li , Sheng Teng Hsu
IPC分类号： H01L21/00
CPC分类号： H01L21/28273 , C23C16/0272 , C23C16/40 , C23C16/56 , H01L21/28194 , H01L21/28291 , H01L21/31691 , H01L28/56 , H01L29/513 , H01L29/517
摘要： A method of forming a ferroelectric thin film on a high-k layer includes preparing a silicon substrate; forming a high-k layer on the substrate; depositing a seed layer of ferroelectric material at a relatively high temperature on the high-k layer; depositing a top layer of ferroelectric material on the seed layer at a relatively low temperature; and annealing the substrate, the high-k layer and the ferroelectric layers to form a ferroelectric thin film.

67. 发明授权

US06939724B2 Method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer 有权
公开(公告)号：US06939724B2
公开(公告)日：2005-09-06
申请号：US10640770
申请日：2003-08-13
申请人： Wei-Wei Zhuang , Tingkai Li , David R. Evans , Sheng Teng Hsu , Wei Pan
发明人： Wei-Wei Zhuang , Tingkai Li , David R. Evans , Sheng Teng Hsu , Wei Pan
IPC分类号： H01L27/04 , H01L21/20 , H01L21/822 , H01L45/00 , H01L21/00
CPC分类号： G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608
摘要： A method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer includes depositing, by MOCVD, a seed layer of PCMO, in highly crystalline form, thin film, having a thickness of between about 50 Å to 300 Å, depositing a second PCMO thin film layer on the seed layer, by spin coating, having a thickness of between about 500 Å to 3000 Å, to form a combined PCMO layer; increasing the resistance of the combined PCMO film in a semiconductor device by applying a negative electric pulse of between about −4V to −5V, having a pulse width of between about 75 nsec to 1 μsec; and decreasing the resistance of the combined PCMO layer in a semiconductor device by applying a positive electric pulse of between about +2.5V to +4V, having a pulse width greater than 2.0 μsec.

68. 发明授权

US06927074B2 Asymmetric memory cell 有权
标题翻译：不对称记忆单元
公开(公告)号：US06927074B2
公开(公告)日：2005-08-09
申请号：US10442627
申请日：2003-05-21
申请人： Sheng Teng Hsu , Tingkai Li , David R. Evans
发明人： Sheng Teng Hsu , Tingkai Li , David R. Evans
IPC分类号： H01L27/10 , G11C11/15 , G11C13/00 , H01L21/8246 , H01L27/105 , H01L43/08 , H01L21/00
CPC分类号： G11C13/0007 , B82Y10/00 , G11C11/15 , G11C2213/31 , G11C2213/52 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147
摘要： An asymmetric memory cell and method for forming an asymmetric memory cell are provided. The method comprises: forming a bottom electrode having a first area; forming an electrical pulse various resistance (EPVR) material overlying the bottom electrode; forming a top electrode overlying the EPVR layer having a second area, less than the first area. In some aspects the second area is at least 20% smaller than the first area. The EPVR is a material such as colossal magnetoresistance (CMR), high temperature super conducting (HTSC), or perovskite metal oxide materials. The method further comprises: inducing an electric field between the electrodes; inducing current flow through the EPVR adjacent the top electrode; and, in response to inducing current flow through the EPVR adjacent the top electrode, modifying the resistance of the EPVR. Typically, the resistance is modified within the range of 100 ohms to 10 mega-ohms.
摘要翻译：提供了一种用于形成非对称存储单元的非对称存储单元和方法。该方法包括：形成具有第一区域的底部电极; 形成覆盖底部电极的各种电阻（EPVR）材料的电脉冲; 形成覆盖在EPVR层上的顶部电极，其具有小于第一区域的第二区域。在一些方面，第二区域比第一区域小至少20％。 EPVR是诸如巨磁阻（CMR），高温超导（HTSC）或钙钛矿金属氧化物材料的材料。该方法还包括：在电极之间引入电场; 通过邻近顶部电极的EPVR引起电流流动; 并且响应于通过与顶部电极相邻的EPVR的电流流动，修改EPVR的电阻。通常，电阻在100欧姆到10兆欧姆的范围内被修改。

69. 发明授权

US06475813B1 MOCVD and annealing processes for C-axis oriented ferroelectric thin films 有权
标题翻译： C轴取向铁电薄膜的MOCVD和退火工艺
公开(公告)号：US06475813B1
公开(公告)日：2002-11-05
申请号：US09929711
申请日：2001-08-13
申请人： Tingkai Li , Wei Pan , Sheng Teng Hsu
发明人： Tingkai Li , Wei Pan , Sheng Teng Hsu
IPC分类号： A01L2100
CPC分类号： H01L21/31691 , C23C16/40 , C30B25/02 , C30B29/30 , C30B29/32 , H01L21/31604
摘要： A method of fabricating a c-axis ferroelectric thin film includes preparing a substrate; depositing a layer of ferroelectric material by metal organic chemical vapor deposition, including using a precursor solution having a ferroelectric material concentration of about 0.1 M/L at a vaporizer temperature of between about 140° C. to 200° C.; and annealing the substrate and the ferroelectric material at a temperature between about 500° C. to 560° C. for between about 30 minutes to 120 minutes.
摘要翻译：制造c轴铁电薄膜的方法包括：制备基板; 通过金属有机化学气相沉积沉积铁电材料层，包括在蒸发器温度为约140℃至200℃之间使用铁电材料浓度为约0.1M / L的前体溶液; 以及在大约500℃至560℃之间的温度下将所述衬底和所述铁电材料退火约30分钟至120分钟。

70. 发明授权

US6048740A Ferroelectric nonvolatile transistor and method of making same 有权
标题翻译：铁电非易失性晶体管及其制造方法
公开(公告)号：US6048740A
公开(公告)日：2000-04-11
申请号：US187238
申请日：1998-11-05
申请人： Sheng Teng Hsu , Jer-shen Maa , Fengyang Zhang , Tingkai Li
发明人： Sheng Teng Hsu , Jer-shen Maa , Fengyang Zhang , Tingkai Li
IPC分类号： H01L21/8247 , H01L21/336 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L29/78 , H01L29/788 , H01L29/792 , H01L29/76
CPC分类号： H01L29/6684 , H01L29/78391
摘要： A method of fabricating a ferroelectric memory transistor using a lithographic process having an alignment tolerance of .delta., includes preparing a silicon substrate for construction of a ferroelectric gate unit; implanting boron ions to form a p- well in the substrate; isolating plural device areas on the substrate; forming a FE gate stack surround structure; etching the FE gate stack surround structure to form an opening having a width of L1 to expose the substrate in a gate region; depositing oxide to a thickness of between about 10 nm to 40 nm over the exposed substrate; forming a FE gate stack over the gate region, wherein the FE gate stack has a width of L2, wherein L2.gtoreq.L1+2.delta.; depositing a first insulating layer over the structure; implanting arsenic or phosphorous ions to form a source region and a drain region; annealing the structure; depositing a second insulating layer; and metallizing the structure. A ferroelectric memory transistor includes a silicon substrate having a p- well formed therein; a gate region, a source region and a drain region disposed along the upper surface of said substrate; a FE gate stack surround structure having an opening having a width of L1 located about said gate region; a FE gate stack formed in said FE gate stack surround structure, wherein said FE gate stack has a width of L2, wherein L2.gtoreq.L1+2.delta., wherein .delta. is the alignment tolerance of the lithographic process.
摘要翻译：使用具有三角形对准公差的光刻工艺制造铁电存储晶体管的方法包括制备用于构造铁电栅极单元的硅衬底; 注入硼离子以在衬底中形成p-阱; 隔离基板上的多个器件区域; 形成一个FE门堆栈环绕结构; 蚀刻FE栅堆叠环绕结构以形成宽度为L1的开口，以在栅极区域中露出基板; 在暴露的衬底上沉积氧化物至约10nm至40nm的厚度; 在所述栅极区域上形成FE栅极堆叠，其中所述FE栅极堆叠具有L2的宽度，其中L2> / = L1 +2δ; 在所述结构上沉积第一绝缘层; 注入砷或磷离子以形成源区和漏区; 退火结构; 沉积第二绝缘层; 并且对结构进行金属化。铁电存储晶体管包括其中形成有p-阱的硅衬底; 栅极区域，源极区域和漏极区域，沿着所述衬底的上表面设置; 具有开口的FE栅叠层环绕结构，所述开口具有围绕所述栅区的L1的宽度; 形成在所述FE栅极堆叠环绕结构中的FE栅极堆叠，其中所述FE栅极堆叠具有L2的宽度，其中L2> / = L1 +2δ，其中Δ是光刻工艺的对准公差。

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