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61. 发明授权

US6117689A Stable high-dielectric-constant material electrode and method 有权
标题翻译：稳定的高介电常数材料电极及方法
公开(公告)号：US6117689A
公开(公告)日：2000-09-12
申请号：US217758
申请日：1998-12-21
申请人： Scott R. Summerfelt
发明人： Scott R. Summerfelt
IPC分类号： H01L21/02 , H01L21/3205 , H01L21/70
CPC分类号： H01L28/60 , H01L21/32051
摘要： A structure for, and method of forming, an oxygen diffusion resistant electrode for high-dielectric-constant materials is disclosed. The electrode comprises a single grain of an oxygen stable material over a barrier layer. The single crystal oxygen stable layer is generally substantially impervious to oxygen diffusion at all relevant deposition and annealing temperatures. The disclosed structure is an integrated circuit comprising an array of microelectronic structures, with each of the microelectronic structures comprising an oxidizable layer (e.g., polysilicon 50), a barrier layer (e.g. TiN 64) overlying the oxidizable layer, a single crystal oxygen stable layer (e.g., Pt 98) overlying the barrier layer, and a high-dielectric-constant material layer (e.g., barium strontium titanate 36) overlying the oxygen stable layer. The disclosed method of fabricating an integrated circuit comprises forming an array of microelectronic structures, wherein forming each of said microelectronic structures comprises forming a barrier layer on an oxidizable layer, depositing a single crystal oxygen stable layer on the barrier layer, and depositing a high-dielectric-constant material layer on the oxygen stable layer. The single crystal oxygen stable layer prevents oxidation of the barrier layer and the oxidizable layer during subsequent processing.
摘要翻译：公开了用于高介电常数材料的氧扩散阻止电极的结构和形成方法。电极在阻挡层上包括单一的氧稳定材料晶粒。在所有相关沉积和退火温度下，单晶氧稳定层通常基本上不渗透氧气扩散。所公开的结构是包括微电子结构阵列的集成电路，其中每个微电子结构包括可氧化层（例如，多晶硅50），覆盖在可氧化层上的阻挡层（例如TiN 64），单晶氧稳定层（例如Pt 98）和覆盖在氧稳定层上的高介电常数材料层（例如，钛酸钡锶36）。所公开的制造集成电路的方法包括形成微电子结构的阵列，其中形成每个所述微电子结构包括在可氧化层上形成阻挡层，在阻挡层上沉积单晶氧稳定层，氧稳定层上的介电常数材料层。单晶氧稳定层防止在后续处理期间阻挡层和可氧化层的氧化。

62. 发明授权

US6100200A Sputtering process for the conformal deposition of a metallization or insulating layer 失效
标题翻译：用于金属化或绝缘层的共形沉积的溅射工艺
公开(公告)号：US6100200A
公开(公告)日：2000-08-08
申请号：US218563
申请日：1998-12-21
申请人： Peter C. Van Buskirk , Michael W. Russell , Daniel J. Vestyck , Scott R. Summerfelt , Theodore S. Moise
发明人： Peter C. Van Buskirk , Michael W. Russell , Daniel J. Vestyck , Scott R. Summerfelt , Theodore S. Moise
IPC分类号： C23C14/04 , C23C14/34 , H01L21/02 , H01L21/285 , H01L21/768 , H01L21/311
CPC分类号： H01L28/55 , C23C14/046 , C23C14/34 , H01L21/76877 , H01L21/76895 , H01L21/2855
摘要： The present invention is a method related to the deposition of a metallization layer in a trench in a semiconductor substrate. The focus of the invention is to sequentially perform heated deposition and etch unit processes to provide a good conformal film of metal on the inner surfaces of a via or trench. The deposition and etch steps can also be performed simultaneously.
摘要翻译：本发明是涉及在半导体衬底中的沟槽中沉积金属化层的方法。本发明的重点是依次执行加热沉积和蚀刻单元工艺以在通孔或沟槽的内表面上提供良好的金属保形膜。沉积和蚀刻步骤也可以同时进行。

63. 发明授权

US6083812A Heteroepitaxy by large surface steps 失效
标题翻译：通过大面积台阶进行异质外延
公开(公告)号：US6083812A
公开(公告)日：2000-07-04
申请号：US12556
申请日：1993-02-02
申请人： Scott R. Summerfelt
发明人： Scott R. Summerfelt
IPC分类号： C30B25/18 , C30B33/06 , H01L21/04 , H01L21/20 , H01L21/205 , H01L21/34
CPC分类号： H01L29/66969 , H01L21/02378 , H01L21/0242 , H01L21/0243 , H01L21/02433 , H01L21/02458 , H01L21/02529 , H01L21/0254 , H01L21/0262 , H01L21/02658 , H01L21/0445 , Y10S438/931
摘要： A method for heteroepitaxial growth and the device wherein a single crystal ceramic substrate, preferably Y stabilized zirconia, MgAl.sub.2 O.sub.4, A1.sub.2 O.sub.3, 3C--SiC, 6H--SiC or MgO is cut and polished at from about 1.0 to about 10 degrees off axis to produce a substantially flat surface. The atoms on the surface are redistributed on the surface to produce surface steps of at least three lattice spacings. An optional epitaxially grown ceramic buffer layer, preferably AlN or GaN, is then formed on the substrate. Then a layer of semiconductor, preferably SiC, AlN when the buffer layer is used and is not AlN or GaN is grown over the substrate and buffer layer, if used.
摘要翻译：用于异质外延生长的方法和其中将单晶陶瓷衬底，优选Y稳定的氧化锆，MgAl 2 O 4，A 12 O 3，3C-SiC，6H-SiC或MgO在离轴上约1.0至约10度切割和抛光的装置，以产生基本平坦的表面。表面上的原子重新分布在表面上以产生至少三个晶格间距的表面步骤。然后在衬底上形成任选的外延生长的陶瓷缓冲层，优选AlN或GaN。然后，如果使用缓冲层，并且不是AlN或GaN，则半导体层，优选SiC，AlN生长在衬底和缓冲层上。

64. 发明授权

US5665628A Method of forming conductive amorphous-nitride barrier layer for high-dielectric-constant material electrodes 失效
标题翻译：形成用于高介电常数材料电极的导电非晶氮化物阻挡层的方法
公开(公告)号：US5665628A
公开(公告)日：1997-09-09
申请号：US485166
申请日：1995-06-07
申请人： Scott R. Summerfelt
发明人： Scott R. Summerfelt
IPC分类号： H01G4/12 , H01G4/012 , H01G4/33 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L21/8247 , H01L27/04 , H01L27/105 , H01L27/108 , H01L29/788 , H01L29/792 , H01L21/70
CPC分类号： H01L28/55 , H01L28/60
摘要： A preferred embodiment of this invention comprises an oxidizable layer (e.g. TiN 50), an amorphous nitride barrier layer (e.g. Ti--Si--N 34) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum 36) overlying the amorphous nitride layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlying the oxygen stable layer. The amorphous nitride barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.
摘要翻译：本发明的优选实施方案包括可氧化层（例如TiN 50），覆盖在可氧化层上的无定形氮化物阻挡层（例如Ti-Si-N 34），覆盖在非晶氮化物层上的氧稳定层（例如铂36）以及覆盖氧稳定层的高介电常数材料层（例如钛酸钡锶38）。无定形氮化物阻挡层基本上抑制氧扩散到可氧化层，从而最小化可氧化层的有害氧化。

65. 发明授权

US5650646A Pb/Bi-containing high-dielectric constant oxides using a non-Pb/Bi-containing perovskite as a buffer layer 失效
标题翻译：含有Pb / Bi的高介电常数氧化物，使用非Pb / Bi的钙钛矿作为缓冲层
公开(公告)号：US5650646A
公开(公告)日：1997-07-22
申请号：US395016
申请日：1995-02-27
申请人： Scott R. Summerfelt
发明人： Scott R. Summerfelt
IPC分类号： C23C14/08 , H01L21/02 , H01L21/28 , H01L21/314 , H01L21/316 , H01L21/8242 , H01L27/108 , H01L29/51 , H05K1/03 , H01L29/76
CPC分类号： H01L21/28185 , H01L21/02197 , H01L21/02304 , H01L21/28158 , H01L21/28167 , H01L21/28194 , H01L21/314 , H01L28/56 , H01L29/513 , H01L29/517 , Y10S148/014 , Y10S148/118 , Y10S438/967
摘要： This is a method for fabricating a structure useful in semiconductor circuitry. The method comprises: growing a buffer layer of non-Pb/Bi-containing high-dielectric constant oxide layer directly or indirectly on a semiconductor substrate; and depositing a Pb/Bi-containing high-dielectric constant oxide on the buffer layer. Alternately this may be a structure useful in semiconductor circuitry, comprising: a buffer layer 26 of non-lead-containing high-dielectric constant oxide layer directly or indirectly on a semiconductor substrate 10; and a lead-containing high-dielectric constant oxide 28 on the buffer layer. Preferably a germanium layer 12 is epitaxially grown on the semiconductor substrate and the buffer layer is grown on the germanium layer. When the substrate is silicon, the non-Pb/Bi-containing high-dielectric constant oxide layer is preferably less than about 10 nm thick. A second non-Pb/Bi-containing high-dielectric constant oxide layer 30 may be grown on top of the Pb/Bi-containing high-dielectric constant oxide and a conducting layer (top electrode 32) may also be grown on the second non-Pb/Bi-containing high-dielectric constant oxide layer.
摘要翻译：这是用于制造在半导体电路中有用的结构的方法。该方法包括：在半导体衬底上直接或间接生长非Pb / Bi的高介电常数氧化物层的缓冲层; 以及在所述缓冲层上沉积含Pb / Bi的高介电常数氧化物。或者，这可以是在半导体电路中有用的结构，其包括：直接或间接地在半导体衬底10上的非含铅高介电常数氧化物层的缓冲层26; 和在缓冲层上的含铅高介电常数氧化物28。优选地，在半导体衬底上外延生长锗层12，并且在锗层上生长缓冲层。当衬底是硅时，非Pb / Bi的高介电常数氧化物层的厚度优选小于约10nm。可以在含Pb / Bi的高介电常数氧化物的顶部上生长第二非Pb / Bi的高介电常数氧化物层30，并且还可以在第二非绝缘材料上生长导电层（顶电极32） -Pb / Bi高介电常数氧化物层。

66. 发明授权

US5647946A Structure and method including dry etching techniques for forming an array of thermal sensitive elements 失效
标题翻译：包括用于形成热敏元件阵列的干蚀刻技术的结构和方法
公开(公告)号：US5647946A
公开(公告)日：1997-07-15
申请号：US463170
申请日：1995-06-05
申请人： James F. Belcher , Howard R. Beratan , Scott R. Summerfelt
发明人： James F. Belcher , Howard R. Beratan , Scott R. Summerfelt
IPC分类号： G01J1/02 , G01J5/34 , H01L21/302 , H01L21/3065 , H01L27/14 , H01L37/02 , H01L21/00
CPC分类号： H01L37/02 , G01J5/34 , Y10S438/942
摘要： An array of thermal sensor elements (16) is formed from a pyroelectric substrate (46) having an infrared absorber and common electrode assembly (18) attached thereto. A first layer of metal contacts (60) is formed to define masked (61) and unmasked (68) regions of the substrate (46). A second layer of metal contacts (62) is formed on the first layer of contacts (60). A radiation etch mask layer (66) is formed to encapsulate the exposed portions of the second layer of contacts (62). A dry-etch mask layer (74) is formed to encapsulate the exposed portions of the first layer of contacts (60) and radiation etch mask layer (66). An initial portion of each unmasked region (68) is etched using a dry-etch process. The remaining portions of the unmasked regions (68) are exposed to an etchant (70) and irradiated with electromagnetic energy to substantially increase the reactivity between the remaining portions and the etchant (70). During such irradiation, the etchant (70) etches the remaining portions substantially faster than the first layer of contacts (60) and the radiation etch mask layer (66).
摘要翻译：一组热传感器元件（16）由具有红外线吸收器和附接到其上的公共电极组件（18）的热电基片（46）形成。第一层金属触点（60）被形成以限定衬底（46）的掩模（61）和未屏蔽（68）区域。第二层金属触点（62）形成在第一层触点（60）上。形成辐射蚀刻掩模层（66）以封装第二层触点（62）的暴露部分。形成干蚀刻掩模层（74）以封装第一层触点（60）和辐射蚀刻掩模层（66）的暴露部分。使用干蚀刻工艺蚀刻每个未掩模区域（68）的初始部分。未掩蔽区域（68）的剩余部分暴露于蚀刻剂（70）并用电磁能照射，以显着增加其余部分和蚀刻剂（70）之间的反应性。在这种照射期间，蚀刻剂（70）基本上比第一层触点（60）和辐射蚀刻掩模层（66）更快地蚀刻剩余部分。

67. 发明授权

US5638599A Method of fabricating hybrid uncooled infrared detectors 失效
标题翻译：混合非制冷红外探测器的制造方法
公开(公告)号：US5638599A
公开(公告)日：1997-06-17
申请号：US412662
申请日：1995-03-29
申请人： Howard R. Beratan , Chih-Chen Cho , Scott R. Summerfelt
发明人： Howard R. Beratan , Chih-Chen Cho , Scott R. Summerfelt
IPC分类号： H01L27/146 , H01L37/02 , H01R9/00
CPC分类号： H01L27/1465 , H01L37/02 , Y10T29/49169
摘要： Thermal isolation mesas 36 comprising a porous material 64 are used to thermally insulate sensing integrated circuitry 44 from pixels 34 of an uncooled IR detector hybrid system 30. The porous material 64 is preferably a silicon-dioxide xerogel. The mesas 36 may also comprise a protective film 66.
摘要翻译：包括多孔材料64的隔热台面36用于将感测集成电路44与未经IR的IR检测器混合系统30的像素34热绝缘。多孔材料64优选为二氧化硅干凝胶。台面36还可以包括保护膜66。

68. 发明授权

US5622893A Method of forming conductive noble-metal-insulator-alloy barrier layer for high-dielectric-constant material electrodes 失效
标题翻译：形成用于高介电常数材料电极的导电贵金属 - 绝缘体 - 合金阻挡层的方法
公开(公告)号：US5622893A
公开(公告)日：1997-04-22
申请号：US283454
申请日：1994-08-01
申请人： Scott R. Summerfelt , Jason Reid , Marc Nicolet , Elzbieta Kolawa
发明人： Scott R. Summerfelt , Jason Reid , Marc Nicolet , Elzbieta Kolawa
IPC分类号： H01G4/33 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/04 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/92 , H01L21/283
CPC分类号： H01L28/60 , H01L28/55 , H01L28/75
摘要： A preferred embodiment of this invention comprises an oxidizable layer (e.g. TiN 50), an noble-metal-insulator-alloy barrier layer (e.g. Pd-Si-N 34) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum 36) overlying the noble-metal-insulator-alloy layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlying the oxygen stable layer. The noble-metal-insulator-alloy barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.
摘要翻译：本发明的优选实施方案包括可氧化层（例如TiN 50），覆盖在可氧化层上的贵金属 - 绝缘体 - 合金阻挡层（例如Pd-Si-N 34），上层的氧稳定层（例如铂36）贵金属 - 绝缘体合金层和覆盖氧稳定层的高介电常数材料层（例如钛酸钡锶38）。贵金属 - 绝缘体 - 合金阻挡层基本上抑制氧扩散到可氧化层，从而最小化可氧化层的有害氧化。

69. 发明授权

US5566045A High-dielectric-constant material electrodes comprising thin platinum layers 失效
标题翻译：包含铂层的高介电常数材料电极
公开(公告)号：US5566045A
公开(公告)日：1996-10-15
申请号：US283881
申请日：1994-08-01
申请人： Scott R. Summerfelt , Howard R. Beratan , Peter S. Kirlin , Bruce E. Gnade
发明人： Scott R. Summerfelt , Howard R. Beratan , Peter S. Kirlin , Bruce E. Gnade
IPC分类号： H01L21/02 , H01G4/10
CPC分类号： H01L28/55 , H01L28/60 , Y10T29/435
摘要： A preferred embodiment of this invention comprises a thin unreactive film (e.g. platinum 36) contacting a high-dielectric-constant material (e.g. barium strontium titanate 38) to an electrode. The thin unreactive film provides a stable conductive interface between the high-dielectric-constant material layer and the electrode base (e.g palladium 34). As opposed to a standard thin-film layer, the thin unreactive film is generally less than 50 nm thick, preferably less than 35 nm thick, more preferably between 5 nm and 25 nm thick, and most preferably between 10 nm and 20 nm thick. A thin unreactive film can benefit from the advantages of the materials used while avoiding or minimizing many of their disadvantages. A thin unreactive film would generally be substantially less expensive than a standard thin-film layer since much less material can be used while not significantly affecting the surface area of the electrode in contact with the HDC material. These structures may also be used for multilayer capacitors and other thin-film ferroelectric devices such as pyroelectric materials, non-volatile memories, thin-film piezoelectric and thin-film electro-optic oxides.
摘要翻译：本发明的优选实施方案包括使高介电常数材料（例如钛酸钡锶38）与电极接触的薄的非反应性膜（例如铂36）。薄的非反应性膜在高介电常数材料层和电极基底（例如钯34）之间提供稳定的导电界面。与标准薄膜层相反，薄的非反应性膜通常小于50nm厚，优选小于35nm厚，更优选在5nm和25nm之间，最优选在10nm和20nm之间。薄的非反应性膜可以受益于所使用的材料的优点，同时避免或最小化许多它们的缺点。薄的非反应性膜通常比标准薄膜层便宜得多，因为可以使用更少的材料，而不会显着影响与HDC材料接触的电极的表面积。这些结构也可以用于多层电容器和其他薄膜铁电体器件，例如热电材料，非易失性存储器，薄膜压电和薄膜电光氧化物。

70. 发明授权

US08907446B2 Integrated circuit structure with capacitor and resistor and method for forming 有权
标题翻译：具有电容器和电阻器的集成电路结构及其形成方法
公开(公告)号：US08907446B2
公开(公告)日：2014-12-09
申请号：US12783044
申请日：2010-05-19
申请人： Scott R. Summerfelt , Byron L. Williams , Scott K. Montgomery , James Klawinsky , Asad M. Haider
发明人： Scott R. Summerfelt , Byron L. Williams , Scott K. Montgomery , James Klawinsky , Asad M. Haider
IPC分类号： H01L29/00 , H01L49/02 , H01L23/522 , H01L27/01
CPC分类号： H01L28/40 , H01L23/5223 , H01L23/5228 , H01L27/016 , H01L28/20 , H01L28/24 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure with a metal-to-metal capacitor and a metallic device such as a resistor, effuse, or local interconnect where the bottom plate of the capacitor and the metallic device are formed with the same material layers. A process for forming a metallic device along with a metal-to-metal capacitor with no additional manufacturing steps.
摘要翻译：具有金属对金属电容器的集成电路结构和电容器，阴极或局部互连的金属器件，其中电容器的底板和金属器件形成有相同的材料层。用于与金属对金属电容器一起形成金属器件的方法，而不需要额外的制造步骤。

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