专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明申请

US20130091317A1 PCI EXPRESS ENHANCEMENTS AND EXTENSIONS 审中-公开
公开(公告)号：US20130091317A1
公开(公告)日：2013-04-11
申请号：US13691016
申请日：2012-11-30
申请人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F13/40
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

62. 发明授权

US08402222B2 Caching for heterogeneous processors 有权
标题翻译：异构处理器的缓存
公开(公告)号：US08402222B2
公开(公告)日：2013-03-19
申请号：US13405798
申请日：2012-02-27
申请人： Frank T. Hady , Mason B. Cabot , John Beck , Mark B. Rosenbluth
发明人： Frank T. Hady , Mason B. Cabot , John Beck , Mark B. Rosenbluth
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F12/0811 , G06F12/0815 , G06F12/0893 , G06F13/4022 , G06F13/4282 , G06F15/167 , G06F15/781 , G06F15/7842 , G06F15/7846 , G06F2212/283 , G06F2212/302 , G06F2212/314 , G06F2212/621
摘要： A multi-core processor providing heterogeneous processor cores and a shared cache is presented.
摘要翻译：提出了一种提供异构处理器内核和共享缓存的多核处理器。

63. 发明申请

US20080005525A1 Partitioning program memory 审中-公开
标题翻译：分区程序存储器
公开(公告)号：US20080005525A1
公开(公告)日：2008-01-03
申请号：US11478106
申请日：2006-06-29
申请人： Mark B. Rosenbluth , Jose S. Niell , Steve Zagorianakos
发明人： Mark B. Rosenbluth , Jose S. Niell , Steve Zagorianakos
IPC分类号： G06F12/00
CPC分类号： G06F12/0284 , G06F9/3802 , G06F9/3814 , G06F9/3851
摘要： A method according to one embodiment may include partitioning a memory into a first partition and a second partition; storing instructions in the first partition; providing access, by at least one thread among a plurality of threads, to instructions in the first partition; dividing the second partition into a plurality of segments; storing instructions in each respective segment corresponding to each respective thread; and providing access to each respective segment for each respective thread. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
摘要翻译：根据一个实施例的方法可以包括将存储器划分成第一分区和第二分区; 将指令存储在第一分区中; 通过多个线程中的至少一个线程向第一分区中的指令提供访问; 将所述第二分区划分成多个分段; 在每个相应的段中存储对应于每个相应线程的指令; 并且为每个相应的线程提供对各个段的访问。当然，在不偏离本实施例的情况下，可以进行许多替代，变化和修改。

64. 发明授权

US07200699B2 Scalable, two-stage round robin arbiter with re-circulation and bounded latency 有权
标题翻译：可扩展的两阶段循环仲裁器具有重新循环和有限延迟
公开(公告)号：US07200699B2
公开(公告)日：2007-04-03
申请号：US10933621
申请日：2004-09-02
申请人： Bijoy Bose , Sridhar Lakshmanamurthy , Mark B. Rosenbluth , Irwin Vaz , Alok Mathur
发明人： Bijoy Bose , Sridhar Lakshmanamurthy , Mark B. Rosenbluth , Irwin Vaz , Alok Mathur
IPC分类号： G06F13/368
CPC分类号： G06F13/4022 , G06F13/362
摘要： A scalable, two-stage round-robin arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and an chassis interconnect that may be controlled to selectively connects a given master to a given target. The chassis interconnect includes multiple sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus. A two-stage arbitration scheme is employed to arbitrate access to the command bus. The first arbitration stage is used to arbitrate between command requests issued by masters in a given cluster. The second arbitration stage is used to arbitrate between winning first stage command requests. One embodiment of the arbitration scheme employs re-circulation of second stage losers. Another embodiment employs re-prioritization of second stage losers.
摘要翻译：可扩展的两阶段循环仲裁器，具有重新循环和有限延迟，可用于多线程多处理器件。实现两级仲裁器的装置包括配置在多个集群中的多个主机，多个目标以及可被控制以选择性地将给定主机连接到给定目标的机箱互连。底盘互连包括连接在多个群集之间的多组总线，并且多个目标形成横杆互连，包括对应于命令总线的总线线。采用两阶段仲裁方案仲裁访问命令总线。第一个仲裁阶段用于在给定群集中由主人发出的命令请求之间进行仲裁。第二仲裁阶段用于在获胜的第一阶段命令请求之间进行仲裁。仲裁方案的一个实施例采用第二阶段输家的再循环。另一个实施例使用第二阶段输家的重新排序。

65. 发明授权

US06973550B2 Memory access control 失效
标题翻译：内存访问控制
公开(公告)号：US06973550B2
公开(公告)日：2005-12-06
申请号：US10264092
申请日：2002-10-02
申请人： Mark B. Rosenbluth , Gilbert M. Wolrich , Debra Bernstein , Richard Guerin
发明人： Mark B. Rosenbluth , Gilbert M. Wolrich , Debra Bernstein , Richard Guerin
IPC分类号： G06F12/00 , G06F12/06 , G06F13/16
CPC分类号： G06F13/1642
摘要： In general, in one aspect, the disclosure describes storing identification of one or more memory buckets associated with different, respective, queued write commands, and, based on the stored identification, determining whether at least one bucket associated with a read command is included in one or more buckets associated with at least one queued write command.
摘要翻译：通常，在一个方面，本公开描述了存储与不同的，相应的排队的写入命令相关联的一个或多个存储器桶的标识，并且基于所存储的标识，确定与读取命令相关联的至少一个桶是否包括在与至少一个排队的写入命令相关联的一个或多个存储桶。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式