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1. 发明申请

US20140281616A1 PLATFORM AGNOSTIC POWER MANAGEMENT 有权
标题翻译：平台电力管理
公开(公告)号：US20140281616A1
公开(公告)日：2014-09-18
申请号：US13799524
申请日：2013-03-13
申请人： Douglas Moran , Achmed Rumi Zahir , William Knolla , Hartej Singh , Vasudev Vasu Bibikar , Sanjeev Jahagirdar , Michael Klinglesmith , Irwin Vaz , Varghese George
发明人： Douglas Moran , Achmed Rumi Zahir , William Knolla , Hartej Singh , Vasudev Vasu Bibikar , Sanjeev Jahagirdar , Michael Klinglesmith , Irwin Vaz , Varghese George
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3243 , G06F1/3287 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： In an embodiment, a processor includes at least one functional block and a central power controller. The at least one functional block may include at least one block component and block power logic. The block power logic may be to: receive a first request to initiate a first reduced power mode in the at least one functional block, and in response to the first request, send a notification signal to a central power controller. The central power controller may be to, in response to the notification signal: store a first state of the at least one functional block, and initiate the first reduced power mode in the at least one functional block. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括至少一个功能块和中央功率控制器。至少一个功能块可以包括至少一个块组件和块功率逻辑。块功率逻辑可以是：接收在所述至少一个功能块中发起第一降低功率模式的第一请求，并且响应于所述第一请求，向中央功率控制器发送通知信号。中央功率控制器可以响应于通知信号：存储至少一个功能块的第一状态，并且启动至少一个功能块中的第一降低功率模式。描述和要求保护其他实施例。

2. 发明授权

US07200699B2 Scalable, two-stage round robin arbiter with re-circulation and bounded latency 有权
标题翻译：可扩展的两阶段循环仲裁器具有重新循环和有限延迟
公开(公告)号：US07200699B2
公开(公告)日：2007-04-03
申请号：US10933621
申请日：2004-09-02
申请人： Bijoy Bose , Sridhar Lakshmanamurthy , Mark B. Rosenbluth , Irwin Vaz , Alok Mathur
发明人： Bijoy Bose , Sridhar Lakshmanamurthy , Mark B. Rosenbluth , Irwin Vaz , Alok Mathur
IPC分类号： G06F13/368
CPC分类号： G06F13/4022 , G06F13/362
摘要： A scalable, two-stage round-robin arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and an chassis interconnect that may be controlled to selectively connects a given master to a given target. The chassis interconnect includes multiple sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus. A two-stage arbitration scheme is employed to arbitrate access to the command bus. The first arbitration stage is used to arbitrate between command requests issued by masters in a given cluster. The second arbitration stage is used to arbitrate between winning first stage command requests. One embodiment of the arbitration scheme employs re-circulation of second stage losers. Another embodiment employs re-prioritization of second stage losers.
摘要翻译：可扩展的两阶段循环仲裁器，具有重新循环和有限延迟，可用于多线程多处理器件。实现两级仲裁器的装置包括配置在多个集群中的多个主机，多个目标以及可被控制以选择性地将给定主机连接到给定目标的机箱互连。底盘互连包括连接在多个群集之间的多组总线，并且多个目标形成横杆互连，包括对应于命令总线的总线线。采用两阶段仲裁方案仲裁访问命令总线。第一个仲裁阶段用于在给定群集中由主人发出的命令请求之间进行仲裁。第二仲裁阶段用于在获胜的第一阶段命令请求之间进行仲裁。仲裁方案的一个实施例采用第二阶段输家的再循环。另一个实施例使用第二阶段输家的重新排序。

3. 发明授权

US07412551B2 Methods and apparatus for supporting programmable burst management schemes on pipelined buses 有权
标题翻译：在流水线总线上支持可编程突发管理方案的方法和装置
公开(公告)号：US07412551B2
公开(公告)日：2008-08-12
申请号：US10882375
申请日：2004-06-30
申请人： Bijoy Bose , Irwin Vaz , Sridhar Lakshmanamurthy , Mark B. Rosenbluth
发明人： Bijoy Bose , Irwin Vaz , Sridhar Lakshmanamurthy , Mark B. Rosenbluth
IPC分类号： G06F13/36
CPC分类号： G06F13/36 , H04L49/101 , H04L49/102 , H04L49/15 , H04L49/45
摘要： Methods and apparatus for supporting programmable burst management schemes on pipelined buses. The apparatus includes a plurality of bus masters (masters), configured in a plurality of clusters, and a plurality of target sub-groups. Each target sub-group includes one or more shared resource targets. A scalable chassis infrastructure is used to interconnect the targets with the clusters using a crossbar interconnect configuration including pipelined command, and data buses. The interconnect includes sub-group multiplexers for each sub-group and sub-group selection multiplexers coupled to each cluster. A two-stage arbiter, operatively coupled to the targets, sub-group multiplexers, and sub-group selection multiplexers, is employed to arbitrate transaction requests issued from the masters to the targets and manage transactions. The two-stage arbiter includes a provision for supporting programmable burst management, wherein selected sub-groups can be tuned for handling short or long burst traffic.
摘要翻译：在流水线总线上支持可编程突发管理方案的方法和装置。该装置包括配置在多个群集中的多个总线主站（主站）和多个目标子组。每个目标子组包括一个或多个共享资源目标。可扩展的机箱基础架构用于使用包括流水线命令和数据总线的交叉连接配置将目标与群集互连。互连包括用于每个子组的子组多路复用器和耦合到每个集群的子组选择多路复用器。使用可操作地耦合到目标的两级仲裁器，子组多路复用器和子组选择多路复用器来仲裁从主人发送到目标的事务请求并管理事务。两级仲裁器包括用于支持可编程突发管理的规定，其中可以调整所选择的子组以处理短或长突发流量。

4. 发明申请

US20060047873A1 Scalable, two-stage round robin arbiter with re-circulation and bounded latency 有权
标题翻译：可扩展的两阶段循环仲裁器具有重新循环和有限延迟
公开(公告)号：US20060047873A1
公开(公告)日：2006-03-02
申请号：US10933621
申请日：2004-09-02
申请人： Bijoy Bose , Sridhar Lakshmanamurthy , Mark Rosenbluth , Irwin Vaz , Alok Mathur
发明人： Bijoy Bose , Sridhar Lakshmanamurthy , Mark Rosenbluth , Irwin Vaz , Alok Mathur
IPC分类号： G06F13/14
CPC分类号： G06F13/4022 , G06F13/362
摘要： A scalable, two-stage round-robin arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and an chassis interconnect that may be controlled to selectively connects a given master to a given target. The chassis interconnect includes multiple sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus. A two-stage arbitration scheme is employed to arbitrate access to the command bus. The first arbitration stage is used to arbitrate between command requests issued by masters in a given cluster. The second arbitration stage is used to arbitrate between winning first stage command requests. One embodiment of the arbitration scheme employs re-circulation of second stage losers. Another embodiment employs re-prioritization of second stage losers.
摘要翻译：可扩展的两阶段循环仲裁器，具有重新循环和有限延迟，可用于多线程多处理器件。实现两级仲裁器的装置包括配置在多个集群中的多个主机，多个目标以及可被控制以选择性地将给定主机连接到给定目标的机箱互连。底盘互连包括连接在多个群集之间的多组总线，并且多个目标形成横杆互连，包括对应于命令总线的总线线。采用两阶段仲裁方案仲裁访问命令总线。第一个仲裁阶段用于在给定群集中由主人发出的命令请求之间进行仲裁。第二仲裁阶段用于在获胜的第一阶段命令请求之间进行仲裁。仲裁方案的一个实施例采用第二阶段输家的再循环。另一个实施例使用第二阶段输家的重新排序。

5. 发明申请

US20060002412A1 Methods and apparatus for supporting programmable burst management schemes on pipelined buses 有权
标题翻译：在流水线总线上支持可编程突发管理方案的方法和装置
公开(公告)号：US20060002412A1
公开(公告)日：2006-01-05
申请号：US10882375
申请日：2004-06-30
申请人： Bijoy Bose , Irwin Vaz , Sridhar Lakshmanamurthy , Mark Rosenbluth
发明人： Bijoy Bose , Irwin Vaz , Sridhar Lakshmanamurthy , Mark Rosenbluth
IPC分类号： H04L12/28
CPC分类号： G06F13/36 , H04L49/101 , H04L49/102 , H04L49/15 , H04L49/45
摘要： Methods and apparatus for supporting programmable burst management schemes on pipelined buses. The apparatus includes a plurality of bus masters (masters), configured in a plurality of clusters, and a plurality of target sub-groups. Each target sub-group includes one or more shared resource targets. A scalable chassis infrastructure is used to interconnect the targets with the clusters using a crossbar interconnect configuration including pipelined command, and data buses. The interconnect includes sub-group multiplexers for each sub-group and sub-group selection multiplexers coupled to each cluster. A two-stage arbiter, operatively coupled to the targets, sub-group multiplexers, and sub-group selection multiplexers, is employed to arbitrate transaction requests issued from the masters to the targets and manage transactions. The two-stage arbiter includes a provision for supporting programmable burst management, wherein selected sub-groups can be tuned for handling short or long burst traffic.
摘要翻译：在流水线总线上支持可编程突发管理方案的方法和装置。该装置包括配置在多个群集中的多个总线主站（主站）和多个目标子组。每个目标子组包括一个或多个共享资源目标。可扩展的机箱基础架构用于使用包括流水线命令和数据总线的交叉连接配置将目标与群集互连。互连包括用于每个子组的子组多路复用器和耦合到每个集群的子组选择多路复用器。使用可操作地耦合到目标的两级仲裁器，子组多路复用器和子组选择多路复用器来仲裁从主人发送到目标的事务请求并管理事务。两级仲裁器包括用于支持可编程突发管理的规定，其中可以调整所选择的子组以处理短或长突发流量。

6. 发明申请

US20110246688A1 MEMORY ARBITRATION TO ENSURE LOW LATENCY FOR HIGH PRIORITY MEMORY REQUESTS 审中-公开
标题翻译：存储器仲裁，以确保低优先级高优先级存储器请求
公开(公告)号：US20110246688A1
公开(公告)日：2011-10-06
申请号：US12752986
申请日：2010-04-01
申请人： IRWIN VAZ , ROHIT NATARAJAN , ALOK MATHUR , SURI MEDAPATI
发明人： IRWIN VAZ , ROHIT NATARAJAN , ALOK MATHUR , SURI MEDAPATI
IPC分类号： G06F3/00 , G06F13/14
CPC分类号： G06F13/1642
摘要： Embodiments of the invention describe arbitrating requests received from a plurality of agents for memory. Each memory request may indicate a priority level of the memory request and a size of the memory to be accessed. Said requests may be stored in a queue. Arbitration logic, coupled to the plurality of agents and the queue, may receive said memory requests and determine which requests to send to the queue based, at least in part, on the priority of each request and the size of the memory to be accessed by each memory request.
摘要翻译：本发明的实施例描述了从多个用于存储器的代理接收的仲裁请求。每个存储器请求可以指示存储器请求的优先级和要访问的存储器的大小。所述请求可以存储在队列中。至少部分地基于每个请求的优先级和要访问的存储器的大小，仲裁逻辑耦合到多个代理和队列，可以接收所述存储器请求并且确定哪些请求发送到队列每个内存请求。

7. 发明申请

US20060221980A1 Method and apparatus for a high efficiency two-stage rotating priority arbiter with predictable arbitration latency 有权
公开(公告)号：US20060221980A1
公开(公告)日：2006-10-05
申请号：US11097067
申请日：2005-03-31
申请人： Bijoy Bose , Sridhar Lakshmanamurthy , Mark Rosenbluth , Irwin Vaz , Suri Medapati , Edwin O'Yang
发明人： Bijoy Bose , Sridhar Lakshmanamurthy , Mark Rosenbluth , Irwin Vaz , Suri Medapati , Edwin O'Yang
IPC分类号： H04L12/56 , H04L12/28 , H04L12/66
CPC分类号： H04L49/101 , H04L49/254
摘要： A scalable, two-stage rotating priority arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and an chassis interconnect that may be controlled to selectively connects a given master to a given target. The chassis interconnect includes multiple sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus. A two-stage arbitration scheme is employed to arbitrate access to the command bus. The first arbitration stage is used to arbitrate between target requests issued by masters in a given cluster. The second arbitration stage is used to arbitrate between winning first-stage target requests. One embodiment of the arbitration scheme employs a rotating priority arbitration scheme at the first stage. Another embodiment employs a complementary rotating priority arbitration scheme at the second stage.

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