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61. 发明申请

US20100127614A1 ORGANIC LIGHT EMITTING DIODE DISPLAY 有权
标题翻译：有机发光二极管显示
公开(公告)号：US20100127614A1
公开(公告)日：2010-05-27
申请号：US12420755
申请日：2009-04-08
申请人： Sung-Hun Lee , Sung-Soo Lee , Seong-Min Kim
发明人： Sung-Hun Lee , Sung-Soo Lee , Seong-Min Kim
IPC分类号： H01J1/62
CPC分类号： H01L51/5265 , H01L27/322 , H01L51/5262
摘要： An organic light emitting device according to an embodiment comprises: a substrate; a transflective member disposed on the substrate; a phase control member disposed on or under the transflective member; an organic light emitting member disposed on the phase control member; and a common electrode disposed on the organic light emitting member. A changing characteristic according to wavelength of an optical constant of the phase control member is opposite to a changing characteristic according to wavelength of an optical constant of the transflective member.
摘要翻译：根据实施例的有机发光器件包括：基板; 设置在所述基板上的半透反射构件; 设置在半透反射构件上或下面的相位控制构件; 设置在所述相位控制部件上的有机发光部件; 以及设置在有机发光部件上的公共电极。根据相位控制构件的光学常数的波长的变化特性与根据半透反射构件的光学常数的波长的变化特性相反。

62. 发明申请

US20090296467A1 NONVOLATILE MEMORY DEVICE AND METHOD OF DRIVING THE SAME 有权
标题翻译：非易失性存储器件及其驱动方法
公开(公告)号：US20090296467A1
公开(公告)日：2009-12-03
申请号：US12472636
申请日：2009-05-27
申请人： Hyung-Gon Kim , Sung-Soo Lee
发明人： Hyung-Gon Kim , Sung-Soo Lee
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G11C11/5642
摘要： Disclosed is a program method of a non-volatile memory device. The program method includes performing a least significant bit (LSB) program operation, during which an LSB program number is stored, and performing a most significant bit (MSB) program operation in a threshold voltage state order determined according to the LSB program number.
摘要翻译：公开了一种非易失性存储器件的程序方法。该程序方法包括执行最低有效位（LSB）编程操作，在此期间存储一个LSB程序号，并以根据LSB程序号确定的阈值电压状态顺序执行最高有效位（MSB）编程操作。

63. 发明申请

US20090200357A1 Wire clamp and wire bonding apparatus having the same 有权
标题翻译：具有相同的线夹和引线接合装置
公开(公告)号：US20090200357A1
公开(公告)日：2009-08-13
申请号：US12320964
申请日：2009-02-10
申请人： Sung-Soo Lee , Ki-Taik Oh , Jung-Hyeon Kim
发明人： Sung-Soo Lee , Ki-Taik Oh , Jung-Hyeon Kim
IPC分类号： B23K37/04
CPC分类号： H01L24/85 , B23K20/007 , H01L24/45 , H01L24/48 , H01L24/78 , H01L2224/45144 , H01L2224/48227 , H01L2224/48463 , H01L2224/78301 , H01L2224/786 , H01L2224/851 , H01L2224/85205 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： A wire clamp includes a pair of clamp arms at a predetermined distance from each other to define an interval therebetween for a bonding wire, a clamp body coupled to the clamp arms, the clamp body configured to adjust the predetermined distance between the clamp arms with respect to a process to be performed, a clamping section in each clamp arm, the clamping section having concave portions facing the interval between the clamp arms, the concave portions being configured to contact the bonding wire when the clamp arms are brought close together, and at least one abrasion prevention member in each clamping section, the abrasion prevention members being configured to prevent abrasion during contact with the bonding wire.
摘要翻译：电线夹具包括彼此隔开预定距离的一对夹持臂，以在其间限定用于接合线的间隔，联接到夹紧臂的夹具本体，夹具主体被配置为相对于夹具臂之间的预定距离调整对于要执行的处理，每个夹持臂中的夹持部分，夹持部分具有面对夹紧臂之间的间隔的凹部，凹部被构造成在夹紧臂靠近在一起时与接合线接触，并且在每个夹紧部分中的至少一个防磨损构件，所述防磨构件被构造成防止在与所述接合线接触期间的磨损。

64. 发明申请

US20060044923A1 Programming circuits and methods for multimode non-volatile memory devices 有权
标题翻译：多模非易失性存储器件的编程电路和方法
公开(公告)号：US20060044923A1
公开(公告)日：2006-03-02
申请号：US11020517
申请日：2004-12-22
申请人： Wook-Ghee Hahn , Sung-Soo Lee , Dae-Seok Byeon
发明人： Wook-Ghee Hahn , Sung-Soo Lee , Dae-Seok Byeon
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/30 , G11C2211/5641
摘要： A non-volatile memory device includes non-volatile memory cells, a respective one of which is configured to store a single bit in a single bit mode, and to store more than one bit in a multi-bit mode. A single voltage divider is configured to generate at a least a first program voltage for the non-volatile memory cells in the single bit mode, and to generate at least a second program voltage that is different from the first program voltage, for the non-volatile memory cells in the multi-bit mode.
摘要翻译：非易失性存储器件包括非易失性存储器单元，其相应的一个被配置为以单位模式存储单个位，并且以多位模式存储多个位。单个分压器被配置为以单比特模式在非易失性存储器单元中产生至少第一编程电压，并且生成与第一编程电压不同的至少第二编程电压，多位模式下的易失性存储单元。

65. 发明申请

US20050030790A1 Nonvolatile semiconductor memory with a programming operation and the method thereof 有权
标题翻译：具有编程操作的非易失性半导体存储器及其方法
公开(公告)号：US20050030790A1
公开(公告)日：2005-02-10
申请号：US10927716
申请日：2004-08-27
申请人： Jae-Yong Jeong , Sung-Soo Lee
发明人： Jae-Yong Jeong , Sung-Soo Lee
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/24 , G11C11/34
CPC分类号： G11C16/24 , G11C16/0483 , G11C16/10
摘要： The invention provides a method of programming in a nonvolatile semiconductor memory device, having a plurality of memory cell strings connected to a plurality of bitlines and constructed of a plurality of memory cell transistors whose gates are coupled to a plurality of wordlines, and a plurality of registers corresponding to the bitlines. The method involves applying a first voltage to a first one of the bitlines and applying a second voltage to a second one of the bitline, the first bitline being adjacent to the second bitline, the first and second voltages being supplied from the registers; electrically isolating the first and second bitlines from their corresponding registers; charging the first bitline up to a third voltage higher than the first voltage and lower than the second voltage; and applying a fourth voltage to a wordline after cutting off current paths into the first and second bitlines.
摘要翻译：本发明提供了一种在非易失性半导体存储器件中进行编程的方法，该方法具有连接到多个位线的多个存储单元串，并且由多个存储单元晶体管组成，多个存储单元晶体管的栅极耦合到多个字线，与位线对应的寄存器。所述方法包括将第一电压施加到位线中的第一位置，并将第二电压施加到所述位线中的第二位置，所述第一位线与所述第二位线相邻，所述第一和第二电压从所述寄存器提供; 将第一和第二位线与其对应的寄存器电隔离; 将第一位线充电至高于第一电压并低于第二电压的第三电压; 以及在将当前路径切断到所述第一和第二位线之后，将第四电压施加到字线。

66. 发明授权

US06650566B2 Nonvolatile semiconductor memory with a programming operation and the method thereof 有权
公开(公告)号：US06650566B2
公开(公告)日：2003-11-18
申请号：US10021639
申请日：2001-12-12
申请人： Jae-Yong Jeong , Sung-Soo Lee
发明人： Jae-Yong Jeong , Sung-Soo Lee
IPC分类号： G11C1604
CPC分类号： G11C16/24 , G11C16/0483 , G11C16/10
摘要： The invention provides a method of programming in a nonvolatile semiconductor memory device, having a plurality of memory cell strings connected to a plurality of bitlines and constructed of a plurality of memory cell transistors whose gates are coupled to a plurality of wordlines, and a plurality of registers corresponding to the bitlines. The method involves applying a first voltage to a first one of the bitlines and applying a second voltage to a second one of the bitline, the first bitline being adjacent to the second bitline, the first and second voltages being supplied from the registers; electrically isolating the first and second bitlines from their corresponding registers; charging the first bitline up to a third voltage higher than the first voltage and lower than the second voltage; and applying a fourth voltage to a wordline after cutting off current paths into the first and second bitlines.

67. 发明授权

US06504450B2 Signal process apparatus for phase-shifting N number of signals inputted thereto 有权
公开(公告)号：US06504450B2
公开(公告)日：2003-01-07
申请号：US09798908
申请日：2001-03-06
申请人： Duk-Yong Kim , Yoon-Bae Lee , Gyu-Sang Hwang , In-Young Lee , Sang-Wook Bang , Chang-Yun Seo , Kyoung-Ho Lee , Sung-Soo Lee , Yoon-Yong Kim , Taek-Dong Kim
发明人： Duk-Yong Kim , Yoon-Bae Lee , Gyu-Sang Hwang , In-Young Lee , Sang-Wook Bang , Chang-Yun Seo , Kyoung-Ho Lee , Sung-Soo Lee , Yoon-Yong Kim , Taek-Dong Kim
IPC分类号： H01P118
CPC分类号： H01P1/184
摘要： A signal process apparatus of the present invention is capable of shifting phases of signals inputted thereto and attenuating the signals, simultaneously. The signal process apparatus includes a dielectric member provided with a first and a second portions, a plurality of transmission lines positioned opposite the dielectric member for transmitting the signals and means for rotating the dielectric member to an axis perpendicular to a surface of the dielectric member which is parallel to the transmission lines. In the signal process apparatus, a dielectric constant of the first portion is different from that of the second portion. Each of the signals is inputted to a corresponding transmission line. After each of the signals is passing through the corresponding transmission line, it has a phase shifted by rotating the dielectric member.

68. 发明授权

US5801989A Method and apparatus for optimizing erase and program times for a non-volatile memory device 失效
标题翻译：用于优化非易失性存储器件的擦除和编程时间的方法和装置
公开(公告)号：US5801989A
公开(公告)日：1998-09-01
申请号：US762495
申请日：1996-12-09
申请人： Sung-Soo Lee , Jin-Ki Kim
发明人： Sung-Soo Lee , Jin-Ki Kim
IPC分类号： G11C17/00 , G11C16/06 , G11C16/10 , G11C16/30 , G11C16/34 , G11C29/50 , G11C29/52 , G11C16/04
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/30 , G11C16/3454 , G11C29/028 , G11C29/50 , G11C29/50012 , G11C29/52 , G11C16/04 , G11C2029/5004
摘要： A nonvolatile semiconductor memory device optimizes the time required for erasing or programming a cell by determining an optimal initial programming voltage. The initial programming voltage is relatively low and is fixed in the device during a test mode operation. During a normal erasing or programming operation, a programming signal having the initial programming voltage level is applied to the cell. The programmed state of the cell is then checked. If the cell did not program successfully, the voltage of the programming signal is increased and another programming cycle is executed. The programming cycle is repeated until the cell is programmed properly or a maximum number of programming cycles is reached. To determine the optimal initial programming voltage, an automatic programming operation is performed using a relatively low voltage programming signal. If the time required to complete the programming operation exceeds a target programming time, the voltage of the programming signal is repetitively increased, and the programming operation is repeated until the time required for the programming operation is less than the target time. The optimal initial voltage level of the programming signal is then fixed in the memory device by selectively cutting fuses in a trimming address register in a programming circuit which also includes a loop counter for counting the number of programming cycles during a programming operation and a programming signal generator that varies the voltage of the programming signal responsive to a control signal from the loop counter.
摘要翻译：非易失性半导体存储器件通过确定最佳初始编程电压来优化擦除或编程单元所需的时间。初始编程电压相对较低，并且在测试模式操作期间固定在器件中。在正常擦除或编程操作期间，具有初始编程电压电平的编程信号被施加到单元。然后检查单元格的编程状态。如果单元没有成功编程，编程信号的电压就会增加，并执行另一个编程周期。重复编程周期，直到单元被正确编程或达到最大编程周期数。为了确定最佳初始编程电压，使用相对低电压的编程信号执行自动编程操作。如果完成编程操作所需的时间超过目标编程时间，则编程信号的电压被重复地增加，并且重复编程操作，直到编程操作所需的时间小于目标时间。编程信号的最佳初始电压电平然后通过选择性地切割编程电路中的微调地址寄存器中的熔丝固定在存储器件中，该编程电路还包括用于在编程操作期间对编程周期数进行计数的循环计数器和编程信号发生器，响应于来自循环计数器的控制信号改变编程信号的电压。

69. 发明授权

US5790458A Sense amplifier for nonvolatile semiconductor memory device 失效
标题翻译：用于非易失性半导体存储器件的感应放大器
公开(公告)号：US5790458A
公开(公告)日：1998-08-04
申请号：US680055
申请日：1996-07-15
申请人： Sung-Soo Lee , Kang-Deog Suh
发明人： Sung-Soo Lee , Kang-Deog Suh
IPC分类号： G11C17/00 , G11C7/06 , G11C16/06 , G11C17/18 , G11C7/00
CPC分类号： G11C7/067
摘要： A sense amplifier for transferring data between a data input/output line and a bit line in a nonvolatile semiconductor memory device includes two isolated current paths to prevent data collisions. A transistor transfers a bit of input data from the data input/output line to a first terminal of a two-terminal latch in response to a load control signal. The second terminal of the latch is connected to the bit line. A second transistor transfers a bit of output data from the second terminal of the latch to the data input/output line in response to a read control signal. While the bit of input data is being transferred, the second transistor isolates the second terminal of the latch from the data input/output line.
摘要翻译：用于在非易失性半导体存储器件中的数据输入/输出线和位线之间传输数据的读出放大器包括两个隔离电流路径，以防止数据冲突。晶体管响应于负载控制信号将数据输入/输出线中的一位输入数据传送到两端锁存器的第一端。锁存器的第二端子连接到位线。响应于读控制信号，第二晶体管将一位输出数据从锁存器的第二端传送到数据输入/输出线。当输入数据的位被传送时，第二晶体管将锁存器的第二端与数据输入/输出线相隔离。

70. 发明授权

US08632635B2 Vapor deposition apparatus and vapor deposition method 有权
标题翻译：蒸镀装置及气相沉积法
公开(公告)号：US08632635B2
公开(公告)日：2014-01-21
申请号：US12535568
申请日：2009-08-04
申请人： Joo-Hyeon Lee , Jin-Koo Chung , Sung-Soo Lee
发明人： Joo-Hyeon Lee , Jin-Koo Chung , Sung-Soo Lee
IPC分类号： C23C16/00
CPC分类号： C23C14/243 , C23C14/12 , C23C14/545
摘要： A vapor deposition apparatus includes a linear head including a plurality of nozzles, and an angle controller controlling an inclined angle of the linear head. The angle of inclination of the linear head can be varied so as to position different portions of the linear head at different distances from the surface of a substrate.
摘要翻译：一种气相沉积设备包括一个包括多个喷嘴的直线头，以及控制线性头部倾斜角度的角度控制器。可以改变线性头部的倾斜角度，以便将线性头部的不同部分定位在与基底表面不同的距离处。

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