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61. 发明授权

US06972249B2 Use of nitrides for flip-chip encapsulation 失效
标题翻译：使用氮化物进行倒装芯片封装
公开(公告)号：US06972249B2
公开(公告)日：2005-12-06
申请号：US10342798
申请日：2003-01-13
申请人： Salman Akram , Warren M. Farnworth
发明人： Salman Akram , Warren M. Farnworth
IPC分类号： H01L21/60 , H01L23/31 , H05K3/28 , H05K3/34 , H01L29/12 , H01L29/22
CPC分类号： H01L24/81 , H01L23/3135 , H01L23/3171 , H01L23/3185 , H01L2224/10126 , H01L2224/1191 , H01L2224/81191 , H01L2224/81815 , H01L2224/81855 , H01L2224/8192 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01072 , H01L2924/01075 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/09701 , H01L2924/12044 , H01L2924/14 , H05K3/284 , H05K3/3436 , H01L2224/29099 , H01L2924/00014
摘要： A hermetically-sealed semiconductor flip-chip and its method of manufacture are disclosed. The semiconductor flip-chip of the present invention is sealed with a silicon nitride layer on an active surface of the flip-chip. The silicon nitride layer covers the chip active surface, including bond pads and conductive connectors such as solder balls formed over the bond pads to effect electrical and mechanical connection to terminal pads of a carrier substrate. A portion of the silicon nitride layer is penetrated or removed to expose a portion of each conductive connector. The flip-chip is then attached to a substrate by contact of the exposed portions of the conductive connectors with the terminal pads of the substrate. Also included in the invention is the alternative of sealing the flip-chip, substrate and intervening connectors with a silicon nitride layer after the attachment of the flip-chip to the substrate.
摘要翻译：公开了一种密封半导体倒装芯片及其制造方法。本发明的半导体倒装芯片在倒装芯片的有源表面上用氮化硅层密封。氮化硅层覆盖芯片有源表面，包括接合焊盘和导电连接器，例如形成在接合焊盘上的焊球，以实现与载体衬底的端子焊盘的电和机械连接。氮化硅层的一部分被穿透或去除以暴露每个导电连接器的一部分。然后将倒装芯片通过导电连接器的暴露部分与衬底的端子焊盘接触而附接到衬底。本发明还包括在将倒装芯片附着到衬底之后将倒装芯片，衬底和中间连接器与氮化硅层密封的替代方案。

62. 发明授权

US06914198B2 Electrical device allowing for increased device densities 失效
标题翻译：电气设备允许增加设备密度
公开(公告)号：US06914198B2
公开(公告)日：2005-07-05
申请号：US10237579
申请日：2002-09-09
申请人： Salman Akram , Warren M. Farnworth , Alan G. Wood , J. Michael Brooks , Eugene H. Cloud
发明人： Salman Akram , Warren M. Farnworth , Alan G. Wood , J. Michael Brooks , Eugene H. Cloud
IPC分类号： H01L23/495 , H05K1/02 , H05K1/09 , H05K3/32 , H05K1/18
CPC分类号： H05K3/4007 , H01L23/4951 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H05K1/0271 , H05K1/095 , H05K3/321 , H05K3/325 , H05K3/326 , H05K2201/0133 , H05K2201/0314 , H05K2201/0367 , H05K2201/09909 , H05K2201/10454 , H05K2201/10696 , H01L2224/45015 , H01L2924/207 , H01L2924/00 , H01L2924/00012
摘要： Disclosed is a device comprising a circuit having an active side and a non-active side, a package enclosing the active side of the circuit and not enclosing a portion of the non-active side of the circuit, and a lead having a first end connected to the active side of the circuit via a lead-over-chip connection, and having a second end extending from the package. Also disclosed is a device comprising a circuit and a lead formed from a flexible conductor, with the lead having a first end connected to the circuit.
摘要翻译：公开了一种包括具有有源侧和非有源侧的电路的器件，封装电路的有源侧的封装，并且不包围电路的非有源侧的一部分，以及引线，其具有连接到第一端经由引线芯片连接到电路的有源侧，并且具有从封装延伸的第二端。还公开了一种包括由柔性导体形成的电路和引线的器件，其中引线具有连接到电路的第一端。

63. 发明授权

US06876089B2 Apparatus and methods of testing and assembling bumped devices using an anisotropically conductive layer 失效
标题翻译：使用各向异性导电层测试和组装凸起装置的装置和方法
公开(公告)号：US06876089B2
公开(公告)日：2005-04-05
申请号：US10338541
申请日：2003-01-07
申请人： Salman Akram , Alan G. Wood , Warren M. Farnworth
发明人： Salman Akram , Alan G. Wood , Warren M. Farnworth
IPC分类号： G01R1/04 , H01L21/60 , H01L23/13 , H01L23/48 , H01L23/498 , H05K3/32 , H01L23/52 , H01L29/40
CPC分类号： H01L23/13 , G01R1/0466 , G01R1/0483 , H01L23/49827 , H01L2224/05571 , H01L2224/05573 , H01L2224/131 , H01L2224/16237 , H01L2224/8114 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0781 , H01L2924/15174 , H05K3/325 , H05K3/326 , H01L2224/05599
摘要： The present invention is directed toward apparatus and methods of testing and assembling bumped die and bumped devices using an anisotropically conductive layer. In one embodiment, a semiconductor device comprises a bumped device having a plurality of conductive bumps formed thereon, a substrate having a plurality of contact pads distributed thereon and approximately aligned with the plurality of conductive bumps, and an anisotropically conductive layer disposed between and mechanically coupled to the bumped device and to the substrate. The anisotropically conductive layer electrically couples each of the conductive bumps with a corresponding one of the contact pads. In another embodiment, an apparatus for testing a bumped device having a plurality of conductive bumps includes a substrate having a plurality of contact pads distributed thereon and substantially alignable with the plurality of conductive bumps, and an anisotropically conductive layer disposed on the first surface and engageable with the plurality of conductive bumps to electrically couple each of the conductive bumps with a corresponding one of the contact pads. Alternately, the test apparatus may also include an alignment device or a bumped device handler. In another embodiment, a method of testing a bumped device includes engaging a plurality of contact pads with an anisotropically conductive layer, engaging the plurality of conductive bumps with the anisotropically conductive layer substantially opposite from and in approximate alignment with the plurality of contact pads, forming a plurality of conductive paths through the anisotropically conductive layer so that each of the conductive bumps is electrically coupled to one of the contact pads, and applying test signals through at least some of the contact pads and the conductive paths to at least some of the conductive bumps.
摘要翻译：本发明涉及使用各向异性导电层测试和组装凸模和凸起装置的装置和方法。在一个实施例中，半导体器件包括具有形成在其上的多个导电凸起的凸起器件，衬底，其上分布有多个接触焊盘并且与多个导电凸块大致对准，并且各向异性导电层设置在机械耦合到凸起的装置和衬底。各向异性导电层将每个导电凸块与对应的一个接触垫电耦合。在另一个实施例中，一种用于测试具有多个导电凸块的凸起器件的设备包括：衬底，其具有分布在其上的多个接触焊盘并且可与多个导电凸块基本对准，以及设置在第一表面上并可接合的各向异性导电层其中多个导电凸块将每个导电凸块与相应的一个接触垫电耦合。或者，测试装置还可以包括对准装置或凸起的装置处理器。在另一个实施例中，一种测试凸起装置的方法包括：将多个接触垫与各向异性导电层接合，使多个导电凸块与多个接触垫基本上相对并与其大致对准的各向异性导电层接合，形成通过各向异性导电层的多个导电路径，使得每个导电凸块电耦合到一个接触焊盘，以及将测试信号通过至少一些接触焊盘和导电路径施加到至少一些导电颠簸

64. 发明授权

US06729027B1 Method of forming recessed socket contacts 失效
标题翻译：形成凹槽插座触点的方法
公开(公告)号：US06729027B1
公开(公告)日：2004-05-04
申请号：US09652724
申请日：2000-08-31
申请人： Salman Akram , Warren M. Farnworth
发明人： Salman Akram , Warren M. Farnworth
IPC分类号： H01R4300
CPC分类号： H01R13/2421 , G01R1/0466 , G01R1/0483 , H01L2924/0002 , H01R12/714 , H01R2201/20 , H05K7/1061 , Y10T29/49117 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49139 , Y10T29/4914 , Y10T29/49144 , Y10T29/49149 , Y10T29/49151 , Y10T29/49153 , Y10T29/49155 , Y10T29/49165 , Y10T29/49174 , Y10T29/49204 , Y10T29/49222 , Y10T29/49224 , Y10T29/53174 , H01L2924/00
摘要： In a socket used to house semiconductor die during testing, a recessed socket contact is provided that avoids pinching the die's contacts and allows for smaller socket holes and therefore denser arrays of contacts. In one embodiment, semiconductor fabrication techniques are used to construct a dense array of contacts and the contacts are singulated while maintaining their alignment within the array. A metal layer may be added to the tips of the contacts for better conductivity.
摘要翻译：在用于在测试期间容纳半导体管芯的插座中，提供了凹入的插座接触件，其避免了挤压模具接触并允许较小的插座孔，并且因此具有较密集的触点阵列。在一个实施例中，使用半导体制造技术来构造密集的触点阵列，并且将触点分开，同时保持它们在阵列内的对准。可以将金属层添加到触点的尖端以获得更好的导电性。

65. 发明授权

US06687989B1 Method for fabricating interconnect having support members for preventing component flexure 有权
标题翻译：用于制造具有用于防止部件弯曲的支撑构件的互连的方法
公开(公告)号：US06687989B1
公开(公告)日：2004-02-10
申请号：US10096649
申请日：2002-03-12
申请人： Warren M. Farnworth , Mike Hess , David R. Hembree , James M. Wark , John O. Jacobson , Salman Akram
发明人： Warren M. Farnworth , Mike Hess , David R. Hembree , James M. Wark , John O. Jacobson , Salman Akram
IPC分类号： H05K310
CPC分类号： G01R1/0483 , Y10T29/49147 , Y10T29/49155 , Y10T29/49165
摘要： A test carrier and an interconnect for testing semiconductor components, such as bare dice and chip scale packages, are provided. The carrier includes a base on which the interconnect is mounted, and a force applying mechanism for biasing the component against the interconnect. The interconnect includes interconnect contacts configured to make temporary electrical connections with component contacts (e.g., bond pads, solder balls). The interconnect also includes support members configured to physically contact the component, to prevent flexure of the component due to pressure exerted by the force applying mechanism. The support members can be formed integrally with the interconnect using an etching process. In addition, the support members can include an elastomeric layer to provide cushioning and to accommodate Z-direction dimensional variations.
摘要翻译：提供了测试载体和用于测试半导体部件（例如裸芯片和芯片级封装）的互连。载体包括其上安装有互连件的基座，以及用于将部件抵靠互连件的力施加机构。互连包括被配置为与部件触点（例如，焊盘，焊球）进行临时电连接的互连触头。互连还包括被配置为物理地接触部件的支撑部件，以防止部件由于施力机构施加的压力而挠曲。支撑构件可以使用蚀刻工艺与互连一体地形成。此外，支撑构件可以包括弹性体层以提供缓冲并适应Z方向尺寸变化。

66. 发明授权

US06648654B1 Electrical connector 失效
标题翻译：电连接器
公开(公告)号：US06648654B1
公开(公告)日：2003-11-18
申请号：US09652720
申请日：2000-08-31
申请人： Salman Akram , David R. Hembree , Warren M. Farnworth
发明人： Salman Akram , David R. Hembree , Warren M. Farnworth
IPC分类号： H01R1200
CPC分类号： H01R13/2421 , G01R1/0466 , G01R1/0483 , H01L2924/0002 , H01R12/714 , H01R2201/20 , H05K7/1061 , Y10T29/49117 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49139 , Y10T29/4914 , Y10T29/49144 , Y10T29/49149 , Y10T29/49151 , Y10T29/49153 , Y10T29/49155 , Y10T29/49165 , Y10T29/49174 , Y10T29/49204 , Y10T29/49222 , Y10T29/49224 , Y10T29/53174 , H01L2924/00
摘要： In a socket to test semiconductor die, a recessed socket contact that avoids pinching the die contacts is disclosed. The socket contacts allow for smaller socket holes and allow denser contact spacing. A variety of embodiments are presented that are suitable for use depending on the spacing between the conductors. For more closely spaced conductors, the body of the socket contact comprises a head, a spring coupled to the head, and a shaft coupled to the spring. No outer shell is needed for the spring, as the nonconductive sides of the socket hole serve that function. For conductors spaced furthur apart, the body of the socket contact comprises a metal shaft having an aperture. Compression causes the shaft to close around the slit, thereby decreasing the amount of lateral buckling. For even more densely spaced contacts, semiconductor fabrication techniques are used to construct a dense array of contacts.
摘要翻译：在一个用于测试半导体管芯的插座中，公开了一种避免夹住管芯接头的凹入的插座接头。插座触点允许更小的插座孔，并允许更密集的接触间距。呈现出根据导体之间的间隔适合使用的各种实施例。对于更紧密间隔的导体，插座触头的主体包括头部，联接到头部的弹簧和联接到弹簧的轴。弹簧不需要外壳，因为插座孔的不导电侧面具有这种功能。对于间隔更远的导体，插座触头的主体包括具有孔的金属轴。压缩使轴在缝隙周围闭合，从而减少侧向屈曲的量。对于甚至更密集间隔的触点，使用半导体制造技术来构造密集的触点阵列。

67. 发明授权

US06553276B2 Method of using data regarding manufacturing procedures integrated circuits (IC's) have undergone, such as repairs, to select procedures the IC's will undergo, such as additional repairs 失效
标题翻译：集成电路（IC）使用数据的方法已经进行了修复，以选择IC将要进行的程序，例如额外修理
公开(公告)号：US06553276B2
公开(公告)日：2003-04-22
申请号：US10071961
申请日：2002-02-05
申请人： Salman Akram , Warren M. Farnworth , Derek J. Gochnour , David R. Hembree , Michael E. Hess , John O Jacobson , James M. Wark , Alan G. Wood
发明人： Salman Akram , Warren M. Farnworth , Derek J. Gochnour , David R. Hembree , Michael E. Hess , John O Jacobson , James M. Wark , Alan G. Wood
IPC分类号： G06F1900
CPC分类号： G06F11/006 , H01L2223/5444
摘要： An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on IC's at probe to determine whether any further repairs will be conducted later in the manufacturing process includes storing the data in association with a fuse ID of each of the IC's. The ID codes of the IC's are automatically read, for example, at an opens/shorts test during the manufacturing process. The data stored in association with the ID codes of the IC's is then accessed, and additional repair procedures the IC's may undergo are selected in accordance with the accessed data. Thus, for example, the accessed data may indicate that an IC is unrepairable, so the IC can proceed directly to a scrap bin without having to be queried to determine whether it is repairable, as is necessary in traditional IC manufacturing processes.
摘要翻译：一种集成电路（IC）制造过程中的发明方法，用于使用关于在探针上的IC进行的修复程序的数据，以确定是否在制造过程中稍后进行进一步的修复，包括将数据与每个的保险丝ID相关联地存储 IC的。例如，在制造过程中，IC的ID代码将自动读取，例如打开/短路测试。然后访问与IC的ID代码相关联存储的数据，并且根据访问的数据选择IC可能经历的附加修复过程。因此，例如，访问的数据可以指示IC不可修复，因此IC可以直接进入废料仓，而不必被查询以确定其是否可修复，如在传统IC制造过程中所必需的。

68. 发明授权

US06529027B1 Interposer and methods for fabricating same 失效
标题翻译：插件及其制造方法
公开(公告)号：US06529027B1
公开(公告)日：2003-03-04
申请号：US09533407
申请日：2000-03-23
申请人： Salman Akram , Alan G. Wood , Warren M. Farnworth
发明人： Salman Akram , Alan G. Wood , Warren M. Farnworth
IPC分类号： G01R3102
CPC分类号： H05K7/1061 , B33Y10/00 , B33Y30/00 , B33Y80/00 , G01R1/0408 , G01R1/0433 , G01R1/0466 , G01R1/0483 , G01R1/07378 , G01R3/00 , H01L23/32 , H01L23/49827 , H01L2224/16111 , H01L2224/16237 , H01L2224/8114 , H01L2224/81385 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01049 , H01L2924/01082 , H01L2924/12042 , H01L2924/12044 , H01L2924/15787 , H01L2924/351 , H05K1/112 , H05K1/141 , H05K3/3436 , H05K2201/049 , H05K2201/09472 , H05K2201/10378 , H05K2201/10734 , H05K2201/2018 , H05K2203/167 , Y10T29/49126 , Y10T29/4913 , Y10T29/49144 , Y10T29/49147 , Y10T29/49156 , Y10T29/49165 , Y10T29/49204 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： An interposer including a fence that receives and aligns a semiconductor device, such as a flip-chip type semiconductor device, with an interposer substrate. The fence may include edges that are configured to progressively align a semiconductor device with the interposer substrate. The fence may also include one or more laterally recessed regions to facilitate rough alignment of a semiconductor device with the interposer substrate. Methods for fabricating the fence include the use of stereolithographic and molding processes. When stereolithography is used to fabricate the fence, a machine vision system that includes at least one camera operably associated with a computer may be used to control a stereolithography apparatus and facilitates recognition of the position and orientation of interposer substrates on and around which material is to be applied in one or more layers to form the fence. As a result, the interposer substrates need not be precisely mechanically aligned.
摘要翻译：一种插入器，其包括接纳半导体器件（例如倒装芯片型半导体器件）与栅介质基板的栅栏。栅栏可以包括被配置为使半导体器件与插入器衬底逐渐对准的边缘。挡板还可以包括一个或多个侧向凹入区域，以便于半导体器件与插入器基板的粗略对准。围栏的制造方法包括使用立体光刻和成型工艺。当使用立体光刻制造栅栏时，可以使用包括与计算机可操作地相关联的至少一个照相机的机器视觉系统来控制立体光刻设备并且有助于识别材料在其上和周围的插入物基板的位置和取向应用于一层或多层以形成栅栏。结果，内插器基板不需要精确地机械对准。

69. 发明授权

US06453550B1 Method for forming modular sockets using flexible interconnects and resulting structures 失效
标题翻译：使用柔性互连和结构的结构形成模块化插座的方法
公开(公告)号：US06453550B1
公开(公告)日：2002-09-24
申请号：US09482416
申请日：2000-01-13
申请人： Warren M. Farnworth , David J. Corisis , Salman Akram
发明人： Warren M. Farnworth , David J. Corisis , Salman Akram
IPC分类号： H05K300
CPC分类号： H01L25/0657 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06593 , H01L2924/0002 , H01L2924/3011 , H01R12/57 , H01R12/7082 , H01R12/721 , H01R12/856 , H01R13/24 , H01R13/514 , H05K7/023 , Y10T29/49126 , Y10T29/4913 , Y10T29/49147 , Y10T29/49153 , Y10T29/49169 , Y10T29/49204 , Y10T29/49222 , H01L2924/00
摘要： Methods for forming a modular bare die socket assembly 10 and attaching a plurality of miniature semiconductor dice 18 to a substrate. The socket assembly 10 is comprised of a plurality of two-sided plates 14 joined vertically in a horizontal stack, wherein each plate 14 has a die socket 22 for the removable insertion of a bare semiconductor die 18. A multi-layer interconnect lead tape 50 has a plurality of lithographically formed leads bent on one end to form nodes 88 for attachment to bond pads 90 on the removably inserted semiconductor die 18, and having opposing ends 92 connectable to the substrate.
摘要翻译：用于形成模块化裸模插座组件10并将多个微型半导体裸片18附接到衬底的方法。插座组件10由在水平叠层中垂直连接的多个双面板14组成，其中每个板14具有用于可裸插入裸半导体管芯18的管芯插座22.多层互连引线带50 具有在一端弯曲的多个光刻形成的引线以形成用于附接到可移除插入的半导体管芯18上的接合焊盘90的节点88，并且具有可连接到基板的相对端92。

70. 发明授权

US06437451B1 Test interconnect for semiconductor components having bumped and planar contacts 有权
公开(公告)号：US06437451B1
公开(公告)日：2002-08-20
申请号：US09738915
申请日：2000-12-14
申请人： Warren M. Farnworth , Salman Akram
发明人： Warren M. Farnworth , Salman Akram
IPC分类号： H01L2348
摘要： An interconnect for testing semiconductor components having both bumped contacts, and planar contacts, is provided. The interconnect includes: a substrate, first contacts on the substrate for electrically engaging the bumped contacts, and second contacts on the substrate for electrically engaging the planar contacts. In illustrative embodiments the first contacts include recesses in the substrate covered with a conductive layer, or recesses formed in a compliant layer on the substrate, or conductive polymer donuts sized and shaped to retain the bumped contacts. In illustrative embodiments the second contacts include etched pillars having penetrating projections, or conductive polymer bumps having penetrating particles, or flat topped projections having a compliant layer thereon. The interconnect can be used to construct a die level test carrier for testing components in singulated form, or to construct a wafer level test carrier for testing components in wafer or panel form.

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