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61. 发明授权

US07683644B2 Extrusion failure monitor structures 失效
标题翻译：挤出破坏监测结构
公开(公告)号：US07683644B2
公开(公告)日：2010-03-23
申请号：US11834054
申请日：2007-08-06
申请人： Ronald G. Filippi , James R. Lloyd, Jr.
发明人： Ronald G. Filippi , James R. Lloyd, Jr.
IPC分类号： G01R27/26 , G01R27/08 , G01N27/60
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A structure and method for monitoring extrusion failures. The structure includes: a test wire having first and second ends; first and second vias contacting first and second ends of the test wire; a first monitor structure electrically isolated from the test wire and surrounding a periphery of the test wire; and a second monitor structure over the test wire, the second monitor structure electrically isolated from the test wire, the second monitor structure extending over at least the first end of the test wire.
摘要翻译：一种用于监测挤压失效的结构和方法。该结构包括：具有第一端和第二端的测试线; 第一和第二通孔接触测试丝的第一和第二端; 与测试线电隔离并围绕测试线周边的第一监视器结构; 以及在所述测试线上的第二监视器结构，所述第二监视器结构与所述测试线电隔离，所述第二监视器结构至少延伸到所述测试线的第一端。

62. 发明申请

US20100038790A1 RELIABILITY OF WIDE INTERCONNECTS 失效
标题翻译：宽互联的可靠性
公开(公告)号：US20100038790A1
公开(公告)日：2010-02-18
申请号：US12191534
申请日：2008-08-14
申请人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , Sujatha Sankaran , Andrew H. Simon , Theodorus Eduardus Standaert
发明人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , Sujatha Sankaran , Andrew H. Simon , Theodorus Eduardus Standaert
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76805 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit which includes a semiconductor substrate, a first metal wiring level on the semiconductor substrate which includes metal wiring lines, an interconnect wiring level on the first metal wiring level which includes a via interconnect within an interlevel dielectric, a second metal wiring level on the interconnect wiring level which includes metal wiring lines, at least one metal wiring line having a plurality of dielectric fill shapes that reduces the cross sectional area of the at least one metal wiring line, and wherein the via interconnect makes electrical contact between a metal line in the first wiring level and the at least one metal wiring line in the second wiring level, the via interconnect being adjacent to and spaced from the plurality of dielectric fill shapes. Also disclosed is a method in which a plurality of dielectric fill shapes are placed adjacent to and spaced from a via contact area in a wiring line in a second wiring level.
摘要翻译：一种集成电路，其包括半导体衬底，所述半导体衬底上的包括金属布线的第一金属布线级别，所述第一金属布线层上的互连布线级别，其包括层间电介质内的通孔布线，第二金属布线级别包括金属布线的互连布线层，至少一个具有多个介电填充形状的金属布线，其减小了所述至少一个金属布线的横截面积，并且其中所述通孔互连使金属线在第一布线级别和第二布线级中的至少一个金属布线中，通孔布线与多个介质填充形状相邻并间隔开。还公开了一种方法，其中多个介电填充形状被放置成与第二布线层中的布线中的通孔接触区域相邻并间隔开。

63. 发明申请

US20090294973A1 INTERCONNECT STRUCTURE FOR INTEGRATED CIRCUITS HAVING IMPROVED ELECTROMIGRATION CHARACTERISTICS 有权
标题翻译：具有改善电磁特性的集成电路的互连结构
公开(公告)号：US20090294973A1
公开(公告)日：2009-12-03
申请号：US12128973
申请日：2008-05-29
申请人： Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , Chao-Kun Hu , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert
发明人： Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , Chao-Kun Hu , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert
IPC分类号： H01L23/538 , H01L21/768
CPC分类号： H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure for an integrated circuit (IC) device includes an elongated, electrically conductive line comprising one or more segments formed at a first width, w1, and one or more segments formed at one or more additional widths, w2 . . . wN, with the first width being narrower than each of the one or more additional widths; wherein the relationship of the total length, L1, of the one or more conductive segments formed at the first width to the total lengths, L2 . . . LN, of the one or more conductive segments formed at the one or more additional widths is selected such that, for a given magnitude of current carried by the conductive line, a critical length with respect to an electromigration short-length effect benefit is maintained such that a total length of the conductive line, L=L1+L2+ . . . +LN, meets a minimum desired design length regardless of the critical length.
摘要翻译：用于集成电路（IC）装置的互连结构包括细长的导电线，其包括形成在第一宽度w 1处的一个或多个段以及以一个或多个附加宽度w2形成的一个或多个段。。。 wN，其中第一宽度比一个或多个附加宽度中的每一个窄; 其中形成在第一宽度处的一个或多个导电段的总长度L1与总长度L2的关系。。。选择以一个或多个附加宽度形成的一个或多个导电段的LN，使得对于给定的导电线承载的电流，相对于电迁移短长度效应益处的临界长度被保持为导线的总长度L = L1 + L2 +。。。 + LN，无论临界长度如何，满足最小设计长度。

64. 发明申请

US20090146143A1 TEST STRUCTURE FOR DETERMINING OPTIMAL SEED AND LINER LAYER THICKNESSES FOR DUAL DAMASCENE PROCESSING 失效
标题翻译：用于确定双重加工过程的最佳种子和层间厚度的测试结构
公开(公告)号：US20090146143A1
公开(公告)日：2009-06-11
申请号：US11953568
申请日：2007-12-10
申请人： Tibor Bolom , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , Paul S. McLaughlin , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert , James Werking
发明人： Tibor Bolom , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , Paul S. McLaughlin , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert , James Werking
IPC分类号： H01L23/58 , H01L21/4763
CPC分类号： H01L22/12 , H01L22/34
摘要： A test structure for integrated circuit (IC) device fabrication includes a plurality of test structure chains formed at various regions of an IC wafer, each of the plurality of test structure chains including one or more vias; each of the one or more vias in contact with a conductive line disposed thereabove, the conductive line being configured such that at least one dimension thereof varies from chain to chain so as to produce variations in seed layer and liner layer thickness from chain to chain for the same deposition process conditions.
摘要翻译：集成电路（IC）器件制造的测试结构包括形成在IC晶片的各个区域的多个测试结构链，所述多个测试结构链中的每一个包括一个或多个通孔; 所述一个或多个通孔中的每一个与设置在其上的导电线接触，所述导电线被配置为使得其至少一个尺寸从链到链变化，从而在种子层和衬层层厚度之间产生从链到链的变化，相同的沉积工艺条件。

65. 发明申请

US20090039896A1 EXTRUSION FAILURE MONITOR STRUCTURES 失效
标题翻译：挤出失效监测结构
公开(公告)号：US20090039896A1
公开(公告)日：2009-02-12
申请号：US11834054
申请日：2007-08-06
申请人： Ronald G. Filippi , James R. Lloyd, JR.
发明人： Ronald G. Filippi , James R. Lloyd, JR.
IPC分类号： G01R31/02
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A structure and method for monitoring extrusion failures. The structure includes: a test wire having first and second ends; first and second vias contacting first and second ends of the test wire; a first monitor structure electrically isolated from the test wire and surrounding a periphery of the test wire; and a second monitor structure over the test wire, the second monitor structure electrically isolated from the test wire, the second monitor structure extending over at least the first end of the test wire.
摘要翻译：一种用于监测挤压失效的结构和方法。该结构包括：具有第一端和第二端的测试线; 第一和第二通孔接触测试丝的第一和第二端; 与测试线电隔离并围绕测试线周边的第一监视器结构; 以及在所述测试线上的第二监视器结构，所述第二监视器结构与所述测试线电隔离，所述第二监视器结构至少延伸到所述测试线的第一端。

66. 发明申请

US20150137312A1 METAL FUSE STRUCTURE FOR IMPROVED PROGRAMMING CAPABILITY 有权
标题翻译：用于改进编程能力的金属保险丝结构
公开(公告)号：US20150137312A1
公开(公告)日：2015-05-21
申请号：US14580539
申请日：2014-12-23
申请人： Griselda Bonilla , Kaushik Chanda , Samuel S. Choi , Ronald G. Filippi , Stephan Grunow , Naftali Lustig , Andrew H. Simon , Junjing Bao
发明人： Griselda Bonilla , Kaushik Chanda , Samuel S. Choi , Ronald G. Filippi , Stephan Grunow , Naftali Lustig , Andrew H. Simon , Junjing Bao
IPC分类号： H01L23/525 , H01L23/528 , H01L23/522
CPC分类号： H01L23/5256 , H01H69/02 , H01H85/046 , H01H2085/0275 , H01L23/5226 , H01L23/528 , H01L2924/0002 , Y10T29/49107 , H01L2924/00
摘要： Structure providing more reliable fuse blow location, and method of making the same. A vertical metal fuse blow structure has, prior to fuse blow, an intentionally damaged portion of the fuse conductor. The damaged portion helps the fuse blow in a known location, thereby decreasing the resistance variability in post-blow circuits. At the same time, prior to fuse blow, the fuse structure is able to operate normally. The damaged portion of the fuse conductor is made by forming an opening in a cap layer above a portion of the fuse conductor, and etching the fuse conductor. Preferably, the opening is aligned such that the damaged portion is on the top corner of the fuse conductor. A cavity can be formed in the insulator adjacent to the damaged fuse conductor. The damaged fuse structure having a cavity can be easily incorporated in a process of making integrated circuits having air gaps.
摘要翻译：提供更可靠的保险丝熔断位置的结构及其制作方法。在熔断器熔断之前，垂直金属保险丝熔断结构在熔丝导体有意损坏的部分。损坏的部分有助于熔断器在已知位置中熔断，从而降低后吹回路中的电阻变化。同时，在保险丝熔断之前，保险丝结构能够正常工作。熔丝导体的损坏部分是通过在保险丝导体的一部分上方的盖层中形成开口，并蚀刻熔丝导体而制成的。优选地，开口对准，使得损坏部分在熔丝导体的顶角上。可以在与损坏的保险丝导体相邻的绝缘体中形成空腔。具有空腔的损坏的保险丝结构可以容易地结合在制造具有气隙的集成电路的过程中。

67. 发明申请

US20120326269A1 E-FUSE STRUCTURES AND METHODS OF MANUFACTURE 有权
标题翻译：电子熔断器结构和制造方法
公开(公告)号：US20120326269A1
公开(公告)日：2012-12-27
申请号：US13165087
申请日：2011-06-21
申请人： GRISELDA BONILLA , Kaushik Chanda , Samuel S. Choi , Ronald G. Filippi , Stephan Grunow , Naftali E. Lustig , Andrew H. Simon
发明人： GRISELDA BONILLA , Kaushik Chanda , Samuel S. Choi , Ronald G. Filippi , Stephan Grunow , Naftali E. Lustig , Andrew H. Simon
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5256 , H01L21/768 , H01L21/76808 , H01L21/76811 , H01L21/76813 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： E-fuse structures in back end of the line (BEOL) interconnects and methods of manufacture are provided. The method includes forming an interconnect via in a substrate in alignment with a first underlying metal wire and forming an e-fuse via in the substrate, exposing a second underlying metal wire. The method further includes forming a defect with the second underlying metal wire and filling the interconnect via with metal and in contact with the first underlying metal wire thereby forming an interconnect structure. The method further includes filling the e-fuse via with the metal and in contact with the defect and the second underlying metal wire thereby forming an e-fuse structure.
摘要翻译：提供线后端的电熔丝结构（BEOL）互连和制造方法。该方法包括在衬底中与第一底层金属线对齐形成互连通孔，并在衬底中形成电熔丝通孔，露出第二下面的金属线。该方法还包括用第二底层金属线形成缺陷并用金属填充互连通孔并与第一底层金属线接触，从而形成互连结构。该方法还包括用金属填充e熔丝通孔并与缺陷和第二下面的金属线接触，从而形成电熔丝结构。

68. 发明授权

US08298948B2 Capping of copper interconnect lines in integrated circuit devices 有权
标题翻译：在集成电路器件中封装铜互连线
公开(公告)号：US08298948B2
公开(公告)日：2012-10-30
申请号：US12613551
申请日：2009-11-06
申请人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , David L. Rath , Sujatha Sankaran , Andrew H. Simon , Theodorus Eduardus Standaert , Chih-Chao Yang
发明人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , David L. Rath , Sujatha Sankaran , Andrew H. Simon , Theodorus Eduardus Standaert , Chih-Chao Yang
IPC分类号： H01L21/44 , H01L21/302
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76849 , H01L21/76865 , H01L2924/0002 , H01L2924/00
摘要： A method for capping lines includes forming a metal film layer on a copper line by a selective deposition process, the copper line disposed in a dielectric substrate, wherein the depositing also results in the deposition of stray metal material on the surface of the dielectric substrate, and etching with an isotropic etching process to remove a portion of the metal film layer and the stray metal material on the surface of the dielectric substrate, wherein the metal film layer is deposited at an initial thickness sufficient to leave a metal film layer cap remaining on the copper line following the removal of the stray metal material.
摘要翻译：一种封盖线的方法包括通过选择性沉积工艺在铜线上形成金属膜层，铜线设置在电介质基底中，其中沉积还导致杂散金属材料沉积在介质基片的表面上，并用各向同性蚀刻工艺进行蚀刻以除去电介质基底表面上的金属膜层和杂散金属材料的一部分，其中金属膜层以足以使金属膜层盖保持在其上的初始厚度沉积铜线除去杂散金属材料。

69. 发明授权

US07639032B2 Structure for monitoring stress-induced degradation of conductive interconnects 失效
标题翻译：用于监测导电互连的应力导致退化的结构
公开(公告)号：US07639032B2
公开(公告)日：2009-12-29
申请号：US12004011
申请日：2007-12-19
申请人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
发明人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
IPC分类号： G01R31/02 , H01L23/58 , G01N25/20
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).
摘要翻译：提供了诸如芯片或微电子布线基板的微电子元件，其包括用于改善耐热应力的多个导电互连。至少一些导电互连件包括金属板，金属连接线和上金属通孔。所述金属连接线具有与所述金属板的上表面至少基本平齐的上表面，在所述周边边缘中的一个处连接到所述金属板的内端和从所述一个周边边缘水平移位的外端。金属连接线的宽度远小于金属板的一个周边边缘的宽度，并且其长度大于一个周边边缘的宽度。上金属通孔在与一个外围边缘水平位移至少约3微米（mum）的位置处具有与金属连接线接触的底端。

70. 发明授权

US06202191B1 Electromigration resistant power distribution network 失效
标题翻译：防电力配电网络
公开(公告)号：US06202191B1
公开(公告)日：2001-03-13
申请号：US09333604
申请日：1999-06-15
申请人： Ronald G. Filippi , Phillip C. Lin , Thomas M. Shaw , Richard A. Wachnik
发明人： Ronald G. Filippi , Phillip C. Lin , Thomas M. Shaw , Richard A. Wachnik
IPC分类号： G06F1750
CPC分类号： H01L21/76858 , G06F17/5077 , H01L21/76841 , H01L21/7685 , H01L23/5286 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： Method for forming a novel power grid structure for integrated circuit semiconductor chip devices that exhibits increased electromigration resistance by including diffusion blocking interlevel contacts and employing a regular array of conducting line elements with “phase shift” between adjacent tracks of segmented power busses. The novel grid structure includes a first metal layer including a first set of conducting line segments that are substantially parallel to one another and run in a first direction; a layer of diffusion blocking dielectric insulation above the first layer; a second metal layer including a second set of conducting line segments substantially parallel to each other and running in a second direction orthogonal to the first direction; and, interlevel contact studs disposed substantially vertically through the diffusion blocking dielectric insulation layer for electrically connecting aligned line segments of the first and second sets, wherein each segment of the first and second sets of line segments is limited to a predetermined length by a diffusion blocking boundary.
摘要翻译：用于形成用于集成电路半导体芯片器件的新型电网结构的方法，其通过包括扩散阻挡层间接触并采用在分段功率总线的相邻轨道之间具有“相移”的导线组件的规则阵列来表现出增加的电迁移阻力。新颖的栅格结构包括第一金属层，其包括基本上彼此平行并沿第一方向延伸的第一组导线段; 在第一层之上的一层扩散阻挡介电绝缘层; 第二金属层，包括基本上彼此平行并沿与第一方向正交的第二方向延伸的第二组导线段; 以及穿过所述扩散阻挡介电绝缘层基本垂直设置的层间接触柱，用于电连接所述第一和第二组的对准的线段，其中所述第一和第二组线段的每个段通过扩散阻挡被限制到预定长度边界。

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