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61. 发明授权

US08492210B2 Transistor, semiconductor device comprising the transistor and method for manufacturing the same 有权
标题翻译：晶体管，包括晶体管的半导体器件及其制造方法
公开(公告)号：US08492210B2
公开(公告)日：2013-07-23
申请号：US13144906
申请日：2011-02-25
申请人： Qingqing Liang , Huilong Zhu , Huicai Zhong
发明人： Qingqing Liang , Huilong Zhu , Huicai Zhong
IPC分类号： H01L21/84
CPC分类号： H01L29/78648 , H01L21/8213 , H01L21/8252 , H01L21/84 , H01L27/0605 , H01L27/1203 , H01L29/66545 , H01L29/66628
摘要： The invention relates to a transistor, a semiconductor device comprising the transistor and manufacturing methods for the transistor and the semiconductor device. The transistor according to the invention comprises: a substrate comprising at least a base layer, a first semiconductor layer, an insulating layer and a second semiconductor layer stacked sequentially; a gate stack formed on the second semiconductor layer; a source region and a drain region located on both sides of the gate stack respectively; a back gate comprising a back gate dielectric and a back gate electrode formed by the insulating layer and the first semiconductor layer, respectively; and a back gate contact formed on a portion of the back gate electrode. The back gate contact comprises an epitaxial part raised from the surface of the back gate electrode, and each of the source region and the drain region comprises an epitaxial part raised from the surface of the second semiconductor layer. As compared to a conventional transistor, the manufacturing process of the transistor of the invention is simplified and the cost of manufacture is reduced.
摘要翻译：本发明涉及晶体管，包括晶体管的半导体器件和用于晶体管和半导体器件的制造方法。根据本发明的晶体管包括：至少包括基层，第一半导体层，绝缘层和顺序层叠的第二半导体层的基板; 形成在所述第二半导体层上的栅叠层; 分别位于栅极堆叠的两侧的源极区域和漏极区域; 包括分别由所述绝缘层和所述第一半导体层形成的背栅电介质和背栅电极的背栅; 以及形成在背栅电极的一部分上的背栅极接触。背栅极触点包括从背栅电极的表面凸起的外延部分，源区和漏区中的每一个包括从第二半导体层的表面凸出的外延部。与常规晶体管相比，本发明的晶体管的制造工艺简化，制造成本降低。

62. 发明授权

US08492206B2 Semiconductor device structure and method for manufacturing the same 有权
标题翻译：半导体器件结构及其制造方法
公开(公告)号：US08492206B2
公开(公告)日：2013-07-23
申请号：US13375692
申请日：2011-08-29
申请人： Huicai Zhong , Jun Luo , Qingqing Liang , Huilong Zhu
发明人： Huicai Zhong , Jun Luo , Qingqing Liang , Huilong Zhu
IPC分类号： H01L21/335 , H01L21/70
CPC分类号： H01L21/823431 , H01L21/823475 , H01L27/0886 , H01L27/1211
摘要： A semiconductor device structure and a method for manufacturing the same are disclosed. In one embodiment, the method comprises: forming a fin in a first direction on a semiconductor substrate; forming a gate line in a second direction crossing the first direction on the semiconductor substrate, the gate line intersecting the fin via a gate dielectric layer; forming a dielectric spacer surrounding the gate line; forming a conductive spacer surrounding the dielectric spacer; and performing inter-device electrical isolation at a predetermined region, wherein isolated portions of the gate line form gate electrodes of respective unit devices, and isolated portions of the conductive spacer form contacts of the respective unit devices.
摘要翻译：公开了一种半导体器件结构及其制造方法。在一个实施例中，所述方法包括：在半导体衬底上沿第一方向形成翅片; 在半导体衬底上与第一方向交叉的第二方向上形成栅极线，栅极线经由栅极电介质层与鳍状物相交; 形成围绕所述栅极线的介电隔离层; 形成围绕所述电介质间隔物的导电间隔物; 以及在预定区域执行器件间电隔离，其中栅极线的隔离部分形成各个单元器件的栅电极，并且导电间隔物的隔离部分形成各个单元器件的接触。

63. 发明授权

US08441045B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08441045B2
公开(公告)日：2013-05-14
申请号：US13378206
申请日：2011-02-27
申请人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L27/085 , H01L29/84 , H01L29/80 , H01L31/112 , H01L29/04
CPC分类号： H01L29/165 , H01L21/30608 , H01L29/1054 , H01L29/1083 , H01L29/517 , H01L29/6653 , H01L29/66553 , H01L29/66583 , H01L29/6659 , H01L29/66651 , H01L29/7834 , H01L29/7849
摘要： The present application discloses a semiconductor device and a method of manufacturing the same. Wherein, the semiconductor device comprises: a semiconductor substrate; a stressor embedded in the semiconductor substrate; a channel region disposed on the stressor; a gate stack disposed on the channel region; a source/drain region disposed on two sides of the channel region and embedded in the semiconductor substrate; wherein, surfaces of the stressor comprise a top wall, a bottom wall, and side walls, the side walls comprising a first side wall and a second side wall, the first side wall connecting the top wall and the second side wall, the second side wall connecting the first side wall and the bottom wall, the angle between the first side wall and the second side wall being less than 180°, and the first sidewall and the second side wall being roughly symmetrical with respect to a plane parallel to the semiconductor substrate. Embodiments of the present invention are applicable to the stress engineering technology in the semiconductor device manufacturing.
摘要翻译：本申请公开了一种半导体器件及其制造方法。其中，所述半导体器件包括：半导体衬底; 嵌入在半导体衬底中的应力器; 设置在所述应力器上的通道区域; 设置在通道区域上的栅极堆叠; 源极/漏极区域，设置在沟道区域的两侧并且嵌入在半导体衬底中; 其中，所述应力器的表面包括顶壁，底壁和侧壁，所述侧壁包括第一侧壁和第二侧壁，所述第一侧壁连接所述顶壁和所述第二侧壁，所述第二侧连接第一侧壁和底壁的壁，第一侧壁和第二侧壁之间的角度小于180°，第一侧壁和第二侧壁相对于平行于半导体的平面大致对称基质。本发明的实施例可应用于半导体器件制造中的应力工程技术。

64. 发明授权

US08426920B2 MOSFET and method for manufacturing the same 有权
标题翻译： MOSFET及其制造方法
公开(公告)号：US08426920B2
公开(公告)日：2013-04-23
申请号：US13379111
申请日：2011-08-01
申请人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L27/12
CPC分类号： H01L29/78648
摘要： The present application provides a MOSFET and a method for manufacturing the same. The MOSFET comprises: a semiconductor substrate; a first buried insulating layer on the semiconductor substrate; a back gate formed in a first semiconductor layer which is on the first buried insulating layer; a second buried insulating layer on the first semiconductor layer; source/drain regions formed in a second semiconductor layer which is on the second buried insulating layer; a gate on the second semiconductor layer; and electrical contacts on the source/drain regions, the gate and the back gate, wherein the back gate is only under a channel region and one of the source/drain regions and not under the other of the source/drain regions, and a common electrical contact is formed between the back gate and the one of the source/drain regions. The MOSFET improves an effect of suppressing short channel effects by an asymmetric back gate, and reduces a footprint on a wafer by using the common conductive via.
摘要翻译：本申请提供了一种MOSFET及其制造方法。 MOSFET包括：半导体衬底; 半导体衬底上的第一掩埋绝缘层; 形成在第一掩埋绝缘层上的第一半导体层中的背栅; 在所述第一半导体层上的第二掩埋绝缘层; 源极/漏极区，形成在第二绝缘层上的第二半导体层中; 第二半导体层上的栅极; 以及源极/漏极区域，栅极和背栅极之间的电接触，其中后栅极仅在沟道区域和源极/漏极区域中的一个并且不在源极/漏极区域的另一个之下，并且具有公共在后栅极和源极/漏极区域之间形成电接触。 MOSFET改善了通过不对称背栅抑制短沟道效应的效果，并且通过使用公共导电通孔来减小晶片上的占位面积。

65. 发明申请

US20130093041A1 Semiconductor Device and Method for Manufacturing the Same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20130093041A1
公开(公告)日：2013-04-18
申请号：US13578598
申请日：2011-11-30
申请人： Qingqing Liang , Huaxiang Yin , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huaxiang Yin , Huicai Zhong , Huilong Zhu
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76224 , H01L21/26506 , H01L29/7842 , H01L29/7847
摘要： The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention may comprise: a substrate; a device region located on the substrate; and at least one stress introduction region separated from the device region by an isolation structure, with stress introduced into at least a portion of the at least one stress introduction region, wherein the stress introduced into the at least a portion of the at least one stress introduction region is produced by utilizing laser to illuminate an amorphized portion comprised in the at least one stress introduction region to recrystallize the amorphized portion. The semiconductor device according to an embodiment of the invention produces stress in a simpler manner and thereby improves the performance of the device.
摘要翻译：本发明涉及半导体器件及其制造方法。根据本发明的实施例的半导体器件可以包括：衬底; 位于所述基板上的器件区域; 以及至少一个应力引入区域，其通过隔离结构从所述器件区域分离，其中所述应力引入所述至少一个应力引入区域的至少一部分，其中所述应力引入所述至少一个应力的至少一部分引入区域通过利用激光照射包含在至少一个应力导入区域中的非晶化部分以使非晶化部分重结晶而产生。根据本发明的实施例的半导体器件以更简单的方式产生应力，从而提高器件的性能。

66. 发明申请

US20130093020A1 MOSFET AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译： MOSFET及其制造方法
公开(公告)号：US20130093020A1
公开(公告)日：2013-04-18
申请号：US13580053
申请日：2011-11-18
申请人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/66545 , H01L29/78648
摘要： The present application discloses a MOSFET and a method for manufacturing the same. The MOSFET is formed on an SOI wafer, comprising: a shallow trench isolation for defining an active region in the semiconductor layer; a gate stack on the semiconductor layer; a source region and a drain region in the semiconductor layer on both sides of the gate stack; a channel region in the semiconductor layer and sandwiched by the source region and the drain region; a back gate in the semiconductor substrate; a first dummy gate stack overlapping with a boundary between the semiconductor layer and the shallow trench isolation; and a second dummy gate stack on the shallow trench isolation, wherein the MOSFET further comprises a plurality of conductive vias which are disposed between the gate stack and the first dummy gate stack and electrically connected to the source region and the drain region respectively, and between the first dummy gate stack and the second dummy gate stack and electrically connected to the back gate. The MOSFET avoids short circuit between the back gate and the source/drain regions by the dummy gate stacks.
摘要翻译：本申请公开了一种MOSFET及其制造方法。 MOSFET形成在SOI晶片上，包括：用于限定半导体层中的有源区的浅沟槽隔离; 半导体层上的栅叠层; 栅极堆叠的两侧的半导体层中的源极区域和漏极区域; 半导体层中的沟道区，被源极区和漏极区夹持; 半导体衬底中的背栅; 与半导体层和浅沟槽隔离之间的边界重叠的第一虚拟栅极堆叠; 以及在浅沟槽隔离上的第二虚拟栅极堆叠，其中所述MOSFET还包括多个导电通孔，所述多个导电通孔设置在所述栅极堆叠和所述第一虚拟栅极堆叠之间，并分别电连接到所述源极区域和所述漏极区域之间，以及第一虚拟栅极堆叠和第二虚拟栅极堆叠并且电连接到背栅极。 MOSFET通过虚拟栅极堆叠避免了背栅极和源极/漏极区域之间的短路。

67. 发明申请

US20130093002A1 MOSFET AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译： MOSFET及其制造方法
公开(公告)号：US20130093002A1
公开(公告)日：2013-04-18
申请号：US13510407
申请日：2011-11-18
申请人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/78648 , H01L21/2652 , H01L21/2658 , H01L21/74 , H01L29/66545 , H01L29/66772
摘要： The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer comprising a semiconductor substrate, a buried insulating layer on the semiconductor substrate, and a semiconductor layer on the buried insulating layer; a gate stack on the semiconductor layer; a source region and a drain region in the semiconductor layer on both sides of the gate stack; and a channel region in the semiconductor layer and located between the source region and the drain region, wherein the MOSFET further comprises a back gate which is located in the semiconductor substrate and has a first doped region as a lower portion of the back gate and a second doped region as an upper portion of the back gate, and the second doped region of the back gate is self-aligned with the gate stack. The MOSFET can adjust a threshold voltage by changing doping type and doping concentration of the back gate.
摘要翻译：本公开公开了一种MOSFET及其制造方法，其中，所述MOSFET包括：SOI晶片，其包含半导体衬底，所述半导体衬底上的埋入绝缘层以及所述埋入绝缘层上的半导体层; 半导体层上的栅叠层; 栅极堆叠的两侧的半导体层中的源极区域和漏极区域; 以及位于所述源极区域和所述漏极区域之间的所述半导体层中的沟道区域，其中，所述MOSFET还包括位于所述半导体衬底中并具有作为所述后栅极的下部的第一掺杂区域的背栅极和第二掺杂区域作为背栅极的上部，并且后栅极的第二掺杂区域与栅极堆叠自对准。 MOSFET可以通过改变背栅的掺杂类型和掺杂浓度来调节阈值电压。

68. 发明申请

US20130069041A1 METHOD FOR MANUFACTURING GRAPHENE NANO-RIBBON, MOSFET AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：制造石墨纳米薄膜的方法，MOSFET及其制造方法
公开(公告)号：US20130069041A1
公开(公告)日：2013-03-21
申请号：US13510390
申请日：2011-11-18
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/20 , H01L21/336 , H01L29/775 , B82Y99/00 , B82Y40/00
CPC分类号： H01L21/0242 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L21/02422 , H01L21/02488 , H01L21/02491 , H01L21/02507 , H01L21/02527 , H01L21/02639 , H01L29/0673 , H01L29/1606 , H01L29/2003 , H01L29/66742 , H01L29/775 , H01L29/78684 , H01L29/78696
摘要： A MOSFET with a graphene nano-ribbon, and a method for manufacturing the same are provided. The MOSFET comprises an insulating substrate; and an oxide protection layer on the insulating substrate. At least one graphene nano-ribbon is embedded in the oxide protection layer and has a surface which is exposed at a side surface of the oxide protection layer. A channel region is provided in each of the at least one graphene nano-ribbon. A source region and a drain regions are provided in each of the at least one graphene nano-ribbon. The channel region is located between the source region and the drain region. A gate dielectric is positioned on the at least one graphene nano-ribbon. A gate conductor on the gate dielectric. A source and drain contacts contact the source region and the drain region respectively on the side surface of the oxide protection layer.
摘要翻译：提供了具有石墨烯纳米带的MOSFET及其制造方法。 MOSFET包括绝缘基板; 和绝缘基板上的氧化物保护层。至少一个石墨烯纳米带被嵌入在氧化物保护层中并且具有暴露在氧化物保护层的侧表面的表面。在所述至少一个石墨烯纳米带的每个中设置有沟道区。在所述至少一个石墨烯纳米带的每一个中设置源极区和漏极区。沟道区位于源区和漏区之间。栅电介质位于至少一个石墨烯纳米带上。栅极电介质上的栅极导体。源极和漏极触点分别在氧化物保护层的侧表面上接触源极区域和漏极区域。

69. 发明申请

US20130049125A1 SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件结构及其制造方法
公开(公告)号：US20130049125A1
公开(公告)日：2013-02-28
申请号：US13375692
申请日：2011-08-29
申请人： Huicai Zhong , Jun Luo , Qingqing Liang , Huilong Zhu
发明人： Huicai Zhong , Jun Luo , Qingqing Liang , Huilong Zhu
IPC分类号： H01L27/088 , H01L21/283
CPC分类号： H01L21/823431 , H01L21/823475 , H01L27/0886 , H01L27/1211
摘要： A semiconductor device structure and a method for manufacturing the same are disclosed. In one embodiment, the method comprises: forming a fin in a first direction on a semiconductor substrate; forming a gate line in a second direction crossing the first direction on the semiconductor substrate, the gate line intersecting the fin via a gate dielectric layer; forming a dielectric spacer surrounding the gate line; forming a conductive spacer surrounding the dielectric spacer; and performing inter-device electrical isolation at a predetermined region, wherein isolated portions of the gate line form gate electrodes of respective unit devices, and isolated portions of the conductive spacer form contacts of the respective unit devices.
摘要翻译：公开了一种半导体器件结构及其制造方法。在一个实施例中，该方法包括：在半导体衬底上沿第一方向形成翅片; 在半导体衬底上与第一方向交叉的第二方向上形成栅极线，栅极线经由栅极电介质层与鳍状物相交; 形成围绕所述栅极线的介电隔离层; 形成围绕所述电介质间隔物的导电间隔物; 以及在预定区域执行器件间电隔离，其中栅极线的隔离部分形成各个单元器件的栅电极，并且导电间隔物的隔离部分形成各个单元器件的接触。

70. 发明申请

US20130049092A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130049092A1
公开(公告)日：2013-02-28
申请号：US13501518
申请日：2011-11-18
申请人： Qingqing Liang , Miao Xu , Huilong Zhu , Huicai Zhong
发明人： Qingqing Liang , Miao Xu , Huilong Zhu , Huicai Zhong
IPC分类号： H01L29/786 , H01L29/78
CPC分类号： H01L29/78654 , H01L29/4908 , H01L29/78603 , H01L29/78648 , H01L29/78696
摘要： The present application discloses a semiconductor device comprising a source region and a drain region in an ultra-thin semiconductor layer; a channel region between the source region and the drain region in the ultra-thin semiconductor layer; a front gate stack above the channel region, the front gate comprising a front gate and a front gate dielectric between the front gate and the channel region; and a back gate stack below the channel region, the back gate stack comprising a back gate and a back gate dielectric between the back gate and the channel region, wherein the front gate is made of a high-Vt material, and the back gate is made of a low-Vt material. According to another embodiment, the front gate and the back gate are made of the same material, and the back gate is applied with a forward bias voltage during operation. The semiconductor device alleviates threshold voltage fluctuation due to varied thickness of the channel region by means of the back gate.
摘要翻译：本申请公开了一种包括超薄半导体层中的源极区域和漏极区域的半导体器件; 在超薄半导体层中的源极区域和漏极区域之间的沟道区域; 在所述沟道区域上方的前栅极堆叠，所述前栅极包括在所述前栅极和所述沟道区域之间的前栅极和前栅极电介质; 以及在沟道区域下方的背栅极堆叠，所述背栅叠层包括在所述背栅极和所述沟道区域之间的背栅极和背栅电介质，其中所述前栅极由高Vt材料制成，并且所述背栅极由低Vt材料制成。根据另一实施例，前栅极和后栅极由相同的材料制成，并且背栅在工作期间被施加正偏压。半导体器件通过后栅极减小由沟道区域的厚度变化引起的阈值电压波动。

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