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61. 发明申请

US20090273998A1 BITCELL CURRENT SENSE DEVICE AND METHOD THEREOF 有权
标题翻译： BITCELL电流检测器件及其方法
公开(公告)号：US20090273998A1
公开(公告)日：2009-11-05
申请号：US12114966
申请日：2008-05-05
申请人： Hongtau Mu , Nian Yang , Fan Wan Lai , Guowei Wang
发明人： Hongtau Mu , Nian Yang , Fan Wan Lai , Guowei Wang
IPC分类号： G11C7/06
CPC分类号： G11C7/067 , G11C7/062 , G11C7/08 , G11C2207/063
摘要： A memory device includes a sense amplifier to sense the state of a bitcell. The sense amplifier includes two input terminals connected via a switch. One of the input terminals is connected to a node, whereby a current through the node represents a difference in current drawn by a bitcell and a reference current. During a first phase, the switch between the input terminals of the sense amplifier is closed, so that a common voltage is applied to both input terminals. During a second phase, the switch is opened, and the sense amplifier senses a state of information stored at the bitcell based on the current through the node. By using the switch to connect and disconnect the inputs of the sense amplifier in the two phases, the accuracy and speed with which the state of the information stored at the bitcell can be determined is improved.
摘要翻译：存储器件包括用于感测位单元的状态的读出放大器。读出放大器包括通过开关连接的两个输入端。一个输入端子连接到一个节点，由此通过该节点的电流表示由位单元和参考电流所画出的电流差。在第一阶段期间，读出放大器的输入端之间的开关闭合，使得两个输入端施加公共电压。在第二阶段期间，开关被打开，并且感测放大器基于通过节点的电流来感测存储在位单元的信息的状态。通过使用开关来连接和断开两相中的读出放大器的输入，可以确定存储在位单元中的信息的状态的精度和速度。

62. 发明申请

US20090206386A1 DECODING SYSTEM CAPABLE OF CHARGING PROTECTION FOR FLASH MEMORY DEVICES 有权
标题翻译：适用于闪存存储器件充电保护的解码系统
公开(公告)号：US20090206386A1
公开(公告)日：2009-08-20
申请号：US12034316
申请日：2008-02-20
申请人： Nian Yang , Joon-Heong Ong , Jiani Zhang
发明人： Nian Yang , Joon-Heong Ong , Jiani Zhang
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11573 , H01L27/11565 , H01L2924/0002 , H01L2924/00
摘要： One embodiment of the present invention relates to a flash memory array. The flash memory array comprises at least two word lines of gate electrode material. At least one of the word lines is connected through a first metal level to a discharge circuit, while other word line(s) may connect to a discharge circuit through a first and second metal level. The memory array further comprises a shorting path between the word lines of the memory array. The shorting path is a high resistance layer of undoped gate electrode material. The resistance value of the gate electrode material is such that the word lines can be used to read, write, or erase without effecting each other, but that during the formation of a first metal level, as charges will build up on a first word line which requires a second metal level to connect to its discharge junction circuit, it will short the first word line to an adjacent second word line that has a connection to its junction circuit on the first metal level. Other methods and circuits are also disclosed.
摘要翻译：本发明的一个实施例涉及闪存阵列。闪存阵列包括栅电极材料的至少两个字线。至少一个字线通过第一金属电平连接到放电电路，而其它字线可以通过第一和第二金属电平连接到放电电路。存储器阵列还包括存储器阵列的字线之间的短路。短路路径是未掺杂的栅电极材料的高电阻层。栅极材料的电阻值使得字线可以用于读取，写入或擦除而不会彼此影响，但是在形成第一金属电平期间，由于电荷将在第一字线上积累这要求第二金属电平连接到其放电结电路，它将使第一字线缩短到与第一金属电平上的结电路连接的相邻第二字线。还公开了其它方法和电路。

63. 发明申请

US20080266926A1 TRANSFER OF NON-ASSOCIATED INFORMATION ON FLASH MEMORY DEVICES 有权
标题翻译：在闪存存储器件上传输非相关信息
公开(公告)号：US20080266926A1
公开(公告)日：2008-10-30
申请号：US11741996
申请日：2007-04-30
申请人： Nian Yang , Yonggang Wu , Tien-Chun Yang
发明人： Nian Yang , Yonggang Wu , Tien-Chun Yang
IPC分类号： G11C5/06
CPC分类号： G11C8/12 , G11C7/12 , G11C7/18 , G11C16/24 , G11C2207/002
摘要： Manners for transferring information within a flash memory device across a memory array are described. A controller retrieves information from a storage unit and then a decoder decodes the information. The information is set across a series of bitlines through a pass gate to a second controller. The bitlines are both associated with the storage unit as well as bitlines associated with other storage units. A series of transistors is associated with each bitline. Different transistors are active based on if the bitlines are associated with the currently used storage unit.
摘要翻译：描述了通过存储器阵列在闪速存储器件内传送信息的方式。控制器从存储单元检索信息，然后解码器解码该信息。信息通过一个通过门到一个第二个控制器的一系列位线设置。位线都与存储单元相关联，以及与其他存储单元相关联的位线。一系列晶体管与每个位线相关联。基于如果位线与当前使用的存储单元相关联，不同的晶体管是有效的。

64. 发明授权

US07443732B2 High performance flash memory device capable of high density data storage 有权
标题翻译：高性能闪存设备能够进行高密度数据存储
公开(公告)号：US07443732B2
公开(公告)日：2008-10-28
申请号：US11229527
申请日：2005-09-20
申请人： Tiao-Hua Kuo , Nancy Leong , Nian Yang , Guowei Wang , Aaron Lee , Sachit Chandra , Michael A. VanBuskirk , Johnny Chen , Darlene Hamilton , Binh Quang Le
发明人： Tiao-Hua Kuo , Nancy Leong , Nian Yang , Guowei Wang , Aaron Lee , Sachit Chandra , Michael A. VanBuskirk , Johnny Chen , Darlene Hamilton , Binh Quang Le
IPC分类号： G11C11/34
CPC分类号： G11C5/147 , G11C16/12
摘要： A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.
摘要翻译：提供了一种用于对包括存储器单元阵列的非易失性存储器阵列进行编程的方法，其中每个存储单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。该方法包括接收包含要在阵列中被编程的预定数量的位的编程窗口，并且确定在存储器阵列中哪个预定位数被编程。预定数量的位同时被编程到阵列中的对应存储器单元。同时验证阵列中预定位数的编程状态。

65. 发明申请

US20080130371A1 METHOD AND APPARATUS FOR HIGH VOLTAGE OPERATION FOR A HIGH PERFORMANCE SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20080130371A1
公开(公告)日：2008-06-05
申请号：US11950811
申请日：2007-12-05
申请人： Nian Yang , Boon-Aik Ang , Yonggang Wu , Guowei Wang , Fan Wan Lai
发明人： Nian Yang , Boon-Aik Ang , Yonggang Wu , Guowei Wang , Fan Wan Lai
IPC分类号： G11C16/12 , G11C16/28
CPC分类号： G11C7/1039 , G11C8/08 , G11C16/0475 , G11C16/0491 , G11C16/08 , G11C16/30 , G11C2207/2245
摘要： A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710). For additional improvements to program operations, the high voltage generator (106) decouples high voltages provided to the word lines (502) and the bit lines (504) by providing a current flow control device (1208) therebetween and provides a boosting voltage at a time (1104) to overcome a voltage level drop (1102) resulting from a capacitor load associated with selected bit lines (504) and/or the bit line decoder (120) precharges (1716) a second portion of the bit lines (504) while providing a high voltage level to a first portion to program (1706) a first portion of memory cells (200). For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference cells (2002) are not blank, reads selected memory cells (200) by providing identically regulated high voltage levels to the selected memory cells (200), the dynamic reference cells (2002) and the static reference cells (2004).

66. 发明申请

US20070286006A1 METHOD AND APPARATUS FOR DRAIN PUMP OPERATION 有权
标题翻译：排水泵运行方法与装置
公开(公告)号：US20070286006A1
公开(公告)日：2007-12-13
申请号：US11423645
申请日：2006-06-12
申请人： Yonggang Wu , Nian Yang , Boon-Aik Ang
发明人： Yonggang Wu , Nian Yang , Boon-Aik Ang
IPC分类号： G11C5/14
CPC分类号： G11C5/145
摘要： A method and apparatus are provided for improved noise reduction from switching on and off drain pumps (202) in a high voltage generator. The drain pumps (202) are divided into groups (204) and activation of the groups (204) of drain pumps (202) is staggered (304, 310). In addition, when drain pumps are switched on and off for power conservation or to maintain a steady state high voltage level, the groups (204) of drain pumps (202) are switched on and off in response to various predetermined high voltage levels (410, 412, 414, 416), with different voltage levels for different groups (204) of drain pumps (202).
摘要翻译：提供了一种方法和装置，用于从高压发生器中的接通和关闭排放泵（202）的开关中减少噪音。排水泵（202）被分成组（204），并且排水泵（202）的组（204）的活动是交错的（304,310）。此外，当排水泵被接通和关闭以进行节能或保持稳定状态的高电压电平时，排水泵（202）的组（204）响应于各种预定的高电压电平（410）被接通和断开，412,414,416），具有用于不同组（204）排水泵（202）的不同电压电平。

67. 发明申请

US20070064480A1 Multi-bit flash memory device having improved program rate 有权
标题翻译：具有改进的程序速率的多位闪存设备
公开(公告)号：US20070064480A1
公开(公告)日：2007-03-22
申请号：US11229519
申请日：2005-09-20
申请人： Tiao-Hua Kuo , Nancy Leong , Hounien Chen , Sachit Chandra , Nian Yang
发明人： Tiao-Hua Kuo , Nancy Leong , Hounien Chen , Sachit Chandra , Nian Yang
IPC分类号： G11C16/04
CPC分类号： G11C16/0491 , G11C16/0475 , G11C16/10
摘要： A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element having at least two charge storage areas for storing at least two independent charges, a source region and a drain region. The method includes designating at least one memory cell as a high-speed memory cell and pre-conditioning the high-speed memory cells by placing a first of the at least two charge storage areas into a programmed state, and subsequently enabling the programming on the second area with much higher rate.
摘要翻译：提供了一种用于对包括存储器单元阵列的非易失性存储器阵列进行编程的方法，其中每个存储器单元包括衬底，控制栅极，具有用于存储至少两个独立电荷的至少两个电荷存储区域的电荷存储元件，源区域和漏极区域。该方法包括将至少一个存储器单元指定为高速存储单元，并且通过将至少两个电荷存储区域中的第一个置于编程状态来预处理高速存储器单元，并且随后使能在第二个地区的利率要高得多。

68. 发明授权

US07019366B1 Electrostatic discharge performance of a silicon structure and efficient use of area with electrostatic discharge protective device under the pad approach and adjustment of via configuration thereto to control drain junction resistance 有权
标题翻译：硅结构的静电放电性能，有效利用垫下方的静电放电保护装置的面积，调整通孔配置，以控制漏极结电阻
公开(公告)号：US07019366B1
公开(公告)日：2006-03-28
申请号：US10758173
申请日：2004-01-14
申请人： Nian Yang , Hiroyuki Ogawa , Yider Wu , Kuo-Tung Chang , Yu Sun
发明人： Nian Yang , Hiroyuki Ogawa , Yider Wu , Kuo-Tung Chang , Yu Sun
IPC分类号： H01L23/62
CPC分类号： H01L27/0251
摘要： More efficient use of silicon area is achieved by incorporating an electrostatic discharge protective (ESDP) device beneath a pad area of a semiconductor structure. The pad area includes a substrate having a first metal layer above it. A second metal layer is above the first metal layer. The ESDP device resides in the substrate below the first metal layer. A layer of dielectric separates the first and second metal layers. A via within the dielectric layer electrically couples the first and second metal layers. A via connects to the ESDP component. Subsequent metal layers can be arranged between the first and second metal layers. The Ohmic value of the resistance component of the ESDP device can be set during fabrication by fixing a number of individual via components, arranged electrically in parallel, by fixing the cross sectional area of the via components, and/or by fixing the length of the via components.
摘要翻译：通过在半导体结构的焊盘区域的下方并入静电放电保护（ESDP）器件来实现硅面积的更有效的使用。焊盘区域包括在其上方具有第一金属层的基板。第二金属层位于第一金属层之上。 ESDP设备位于第一金属层下方的基板中。电介质层分离第一和第二金属层。电介质层内的通孔电耦合第一和第二金属层。 A通道连接到ESDP组件。随后的金属层可以布置在第一和第二金属层之间。 ESDP装置的电阻部件的欧姆值可以在制造期间通过固定多个单独的通孔部件，通过固定通孔部件的横截面面积和/或固定长度通过组件。

69. 发明授权

US06861696B1 Structure and method for a two-bit memory cell 有权
标题翻译： 2位存储单元的结构和方法
公开(公告)号：US06861696B1
公开(公告)日：2005-03-01
申请号：US10429140
申请日：2003-05-03
申请人： Hyeon-Seag Kim , Nian Yang , Munseork Choi
发明人： Hyeon-Seag Kim , Nian Yang , Munseork Choi
IPC分类号： H01L21/28 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/792 , H01L29/76
CPC分类号： H01L27/11568 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L29/7923
摘要： According to one exemplary embodiment, a two-bit memory cell situated over a substrate comprises a tunnel oxide layer situated over the substrate. The two-bit memory cell further comprises a first spacer and a second spacer situated over the tunnel oxide layer, where the first spacer is a first data bit storage location in the two-bit memory cell and the second spacer is a second data bit storage location in the two-bit memory cell. The first spacer and the second spacer may be, for example, silicon nitride or polycrystalline silicon. According to this exemplary embodiment, the two-bit memory cell further comprises an oxide layer situated between the first spacer and the second spacer. The two-bit memory cell further comprises a control gate situated over the oxide layer.
摘要翻译：根据一个示例性实施例，位于衬底上方的两位存储器单元包括位于衬底上方的隧道氧化物层。两位存储单元还包括位于隧道氧化物层上的第一间隔物和第二隔离物，其中第一间隔物是两位存储单元中的第一数据位存储位置，第二隔离物是第二数据位存储位置在两位存储单元中。第一间隔物和第二间隔物可以是例如氮化硅或多晶硅。根据该示例性实施例，两比特存储单元还包括位于第一间隔物和第二间隔物之间的氧化物层。两比特存储单元进一步包括位于氧化物层上方的控制栅极。

70. 发明授权

US06784682B1 Method of detecting shallow trench isolation corner thinning by electrical trapping 失效
标题翻译：通过电捕获检测浅沟槽隔离角变薄的方法
公开(公告)号：US06784682B1
公开(公告)日：2004-08-31
申请号：US10113259
申请日：2002-03-28
申请人： Tien-Chun Yang , Nian Yang , Hyeon-Seag Kim
发明人： Tien-Chun Yang , Nian Yang , Hyeon-Seag Kim
IPC分类号： G01R3126
CPC分类号： G01R31/2648
摘要： A method and apparatus for testing semiconductors comprising shallow trench isolation (STI) edge structures. An edge intensive shallow trench isolation structure (500) is coupled to a voltage source (310) and a current profile is recorded. A planar structure (600) on the same wafer is coupled to a voltage source and a current profile is recorded. A comparison of current profiles obtained for the two types of structures may indicate the presence and/or extent of STI corner effects. More specifically, a steeper slope for a normalized current versus time plot for an STI edge intensive structure (500) compared to a slope of a normalized plot of a planar structure (600) is indicative of an increased rate of electron trapping in STI corners, which may indicate that the STI corners are too thin. In this novel manner, STI corner thickness is observed in a non-destructive, electrical test process, resulting in higher quality and greater reliability of semiconductors using STI processes.
摘要翻译：一种用于测试包括浅沟槽隔离（STI）边缘结构的半导体的方法和装置。边缘密集的浅沟槽隔离结构（500）耦合到电压源（310）并且记录电流分布。在同一晶片上的平面结构（600）耦合到电压源并且记录电流分布。对于两种类型的结构获得的当前轮廓的比较可以指示STI拐角效应的存在和/或程度。更具体地，与平面结构（600）的归一化图的斜率相比，用于STI边缘密集结构（500）的归一化电流对时间图的更陡峭的斜率表示STI拐角中的电子捕获速率增加，这可能表明STI拐角太薄。以这种新颖的方式，在非破坏性电气测试过程中观察到STI拐角厚度，从而导致使用STI工艺的半导体的更高的质量和更高的可靠性。

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