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61. 发明申请

US20120110294A1 METHOD OF MEMORY MANAGEMENT FOR SERVER-SIDE SCRIPTING LANGUAGE RUNTIME SYSTEM 失效
标题翻译：服务器语言语言运行系统的内存管理方法
公开(公告)号：US20120110294A1
公开(公告)日：2012-05-03
申请号：US13344687
申请日：2012-01-06
申请人： Hiroshi Inoue , Hideaki Komatsu
发明人： Hiroshi Inoue , Hideaki Komatsu
IPC分类号： G06F12/02
CPC分类号： G06F12/0253
摘要： A method of memory management includes allocating a portion of a memory as a memory heap including a plurality of segments, each segment having a segment size; performing one or more memory allocations for objects in the memory heap; creating a free list array and class-size array in a metadata section of the memory heap, the class-size array being created such that each element of the size-class array is related a particular one of the plurality of segments and the free list array being created such that each element of the free list array is related to a different size class; and initializing the heap when it is determined that the heap may be destroyed, initializing including clearing the free list array.
摘要翻译：一种存储器管理方法包括将存储器的一部分分配为包括多个段的存储堆，每个段具有段大小; 对存储器堆中的对象执行一个或多个存储器分配; 在内存堆的元数据部分中创建自由列表数组和类大小数组，创建类大小数组，使得大小类数组的每个元素与多个片段中的特定片段和自由列表相关联数组被创建，使得自由列表数组的每个元素与不同大小的类相关; 并且当确定堆可能被破坏时初始化堆，初始化包括清除空闲列表数组。

62. 发明申请

US20120101791A1 CONTROLLING SIMULATION SYSTEMS 审中-公开
标题翻译：控制仿真系统
公开(公告)号：US20120101791A1
公开(公告)日：2012-04-26
申请号：US13246052
申请日：2011-09-27
申请人： Hideaki Komatsu , Shingo Nagai , Fumitomo Ohsawa
发明人： Hideaki Komatsu , Shingo Nagai , Fumitomo Ohsawa
IPC分类号： G06G7/48
CPC分类号： G06F17/5009 , G05B17/02 , G06F17/5095
摘要： A method for controlling a simulation system includes storing first-stage and second stage tables in which a value of a predicted time until arrival of an I/O instruction and a type of the instruction are included as entries for each program counter of an instruction set simulator, and in which a value of an earliest time until an output event from a peripheral simulator is included as an entry for each type of instruction; looking up the first-stage table to obtain the type of the instruction and the value of the predicted time until arrival of the instruction, looking up the second-stage table with reference to the obtained type of the instruction to obtain the value of the earliest time until the output event from the peripheral simulator, and returning the predicted time until arrival of the instruction and the earliest time until the output event from the peripheral simulator.
摘要翻译：一种用于控制模拟系统的方法，包括存储第一级和第二级表，其中包括I / O指令的到达之前的预测时间的值和指令的类型作为指令集的每个程序计数器的条目模拟器，并且其中包括来自外围模拟器的输出事件之前的最早时间的值作为每种类型的指令的条目; 查找第一级表以获得指令的类型和直到指令到达的预测时间的值，参考获得的指令类型来查找第二级表以获得最早的值直到来自外围模拟器的输出事件为止，并返回直到指令到达为止的预测时间和最早的时间，直到来自外围模拟器的输出事件。

63. 发明授权

US08104026B2 Compiler register allocation and compilation 失效
标题翻译：编译器寄存器分配和编译
公开(公告)号：US08104026B2
公开(公告)日：2012-01-24
申请号：US11927355
申请日：2007-10-29
申请人： Akira Koseki , Hideaki Komatsu
发明人： Akira Koseki , Hideaki Komatsu
IPC分类号： G06F9/44
CPC分类号： G06F8/441
摘要： Assigns suitable registers to a plurality of variables. A compiler converts a source program into instructions for a processor having: a simultaneously used variable acquisition section which obtains, with respect to each of a plurality of variables used in the source program, some of the other variables used simultaneously with the variable; an allocation sequence generation section which generates a plurality of allocation sequences between the plurality of variables to allocate each variable to one of the plurality of registers different from those to which some of the other variables used simultaneously with the variable are allocated; an allocation priority acquisition section which obtains allocation priorities indicating to which one of the plurality of registers each variable is allocated with priority; and a register allocation section which allocates the variables to registers in accordance with an allocation sequence selected on the basis of the allocation priorities.
摘要翻译：将适当的寄存器分配给多个变量。编译器将源程序转换为具有以下处理器的指令：具有：同时使用的变量获取部分，其针对源程序中使用的多个变量中的每一个获得与该变量同时使用的一些其它变量; 分配序列生成部，其生成所述多个变量之间的多个分配序列，以将每个变量分配给与所述变量同时使用的一些其他变量的多个寄存器中的一个不同的寄存器; 分配优先级获取部分，其优先级获得指示分配了多个寄存器中的每个变量的哪个寄存器的分配优先级; 以及寄存器分配部分，其根据基于分配优先级选择的分配序列将变量分配给寄存器。

64. 发明授权

US07979853B2 Compiler device, method, program and recording medium 失效
标题翻译：编译器装置，方法，程序和记录介质
公开(公告)号：US07979853B2
公开(公告)日：2011-07-12
申请号：US12019446
申请日：2008-01-24
申请人： Motohiro Kawahito , Hideaki Komatsu
发明人： Motohiro Kawahito , Hideaki Komatsu
IPC分类号： G06F9/45
CPC分类号： G06F8/41
摘要： Compiler device optimizes a program by changing an order of executing instructions. The device includes: a replaceability determination unit which determines whether a first instruction included in a first instruction sequence and a second instruction included in a second instruction sequence executed after the first instruction sequence can be replaced with a common processing instruction group including a common processing instruction for processing at least respective parts of processings by the first and second instructions together; a common processing instruction group generation unit which generates a common processing instruction group in the first instruction sequence, in place of the first instruction, when the replaceability determination unit determines the first and second instructions to be replaceable; and an instruction insertion unit which inserts the second instruction into a third instruction sequence that is an instruction sequence other than the first instruction sequence and is executed before the second instruction sequence.
摘要翻译：编译器设备通过更改执行指令的顺序来优化程序。该装置包括：可替换性确定单元，其确定包括在第一指令序列中的第一指令和包括在第一指令序列之后执行的第二指令序列中的第二指令是否可以被包括公共处理指令的公共处理指令组替换用于通过第一和第二指令一起处理至少相应的处理部分; 当可替换性确定单元确定可替换的第一和第二指令时，代替第一指令，生成第一指令序列中的公共处理指令组的公共处理指令组生成单元; 以及指令插入单元，其将第二指令插入作为第一指令序列以外的指令序列的第三指令序列，并且在第二指令序列之前执行。

65. 发明授权

US07950005B2 Method and apparatus for performing versioning for loop, method and apparatus for collecting array range check information in basic blocks, method for modifying array range check information, method for optimizing array range checks, method for generating codes for array range checks, method and apparatus for eliminating redundant array range checks, method for selecting array range checks, method for modifying array range checks, method for collecting array range checks, and method for determining handling of array range checks 失效
标题翻译：用于执行循环的方法和装置，用于收集基本块中的阵列范围检查信息的方法和装置，用于修改阵列范围检查信息的方法，用于优化阵列范围检查的方法，用于生成阵列范围检查的代码的方法，方法和装置消除冗余阵列范围检查，选择阵列范围检查的方法，修改阵列范围检查的方法，采集数组范围检查的方法以及确定数组范围检查处理的方法
公开(公告)号：US07950005B2
公开(公告)日：2011-05-24
申请号：US11838734
申请日：2007-08-14
申请人： Motohiro Kawahito , Toshiaki Yasue , Hideaki Komatsu
发明人： Motohiro Kawahito , Toshiaki Yasue , Hideaki Komatsu
IPC分类号： G06F9/44
CPC分类号： G06F8/437 , G06F8/4441
摘要： A system and method are provided that in one aspect eliminate redundant array range checks by performing a versioning for a loop. In another aspect, a system and method optimize array range checks by performing data-flow analysis in reverse order of the program execution. Yet in another aspect, a system and method obtains information about array ranges already checked by performing data-flow analysis in program execution order and eliminate redundant array range checks from this information.
摘要翻译：提供了一种系统和方法，其一方面通过执行循环的版本控制来消除冗余阵列范围检查。在另一方面，系统和方法通过以与程序执行相反的顺序执行数据流分析来优化阵列范围检查。另一方面，系统和方法通过以程序执行顺序执行数据流分析获得已经检查的数组范围的信息，并从该信息中消除冗余阵列范围检查。

66. 发明申请

US20110015916A1 SIMULATION METHOD, SYSTEM AND PROGRAM 有权
标题翻译：模拟方法，系统和程序
公开(公告)号：US20110015916A1
公开(公告)日：2011-01-20
申请号：US12834081
申请日：2010-07-12
申请人： Masaki Kataoka , Hideaki Komatsu , Goh Kondoh , Fumitomo Ohsawa
发明人： Masaki Kataoka , Hideaki Komatsu , Goh Kondoh , Fumitomo Ohsawa
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5095
摘要： A simulation system having multiple peripherals that communicate with each other. The system includes a weighted graph with weights set as communication times. The peripherals are represented as nodes and connection paths are represented as edges. Among the communication times in the loop, the minimum time is set as first synchronization timing. Timing with an acceptable delay added is set as second synchronization timing. Timing set by a user to be longer than the first and second timings is set as third synchronization timing. The third synchronization timing is used in a portion where the timing is usable, thus synchronizing the peripherals at the longest possible synchronization timing.
摘要翻译：具有彼此通信的多个外围设备的模拟系统。该系统包括权重设置为通信时间的加权图。外围设备表示为节点，连接路径表示为边。在循环中的通信时间中，将最小时间设置为第一同步定时。具有可接受延迟的定时被设置为第二同步定时。由用户设定为比第一和第二定时长的定时被设定为第三同步定时。第三同步定时用于定时可用的部分，从而在尽可能长的同步定时同步外设。

67. 发明申请

US20100005457A1 METHOD OF REDUCING LOGGING CODE IN A COMPUTING SYSTEM 失效
标题翻译：降低计算系统中记录码的方法
公开(公告)号：US20100005457A1
公开(公告)日：2010-01-07
申请号：US12168206
申请日：2008-07-07
申请人： Hideaki Komatsu , Takuya Nakaike , Rei Odaira
发明人： Hideaki Komatsu , Takuya Nakaike , Rei Odaira
IPC分类号： G06F9/45
CPC分类号： G06F8/4435 , G06F8/443
摘要： A computing system for reducing logging code includes a virtual machine configured to control the flow of operations in the computing system and a compiler configured to receive bytecode instructions from the virtual machine and convert the bytecode instructions into machine instructions. The computing system also includes a compilation store configured to receive and store the machine instructions from the compiler and a recompilation store configured to receive and store recompiled machine instructions from the compiler. The system also includes a software transactional memory engine configured to receive instructions from the compilation store or, in the event that the recompilation store has recompiled machine instructions stored therein, from the recompilation store.
摘要翻译：用于减少日志记录代码的计算系统包括配置成控制计算系统中的操作流的虚拟机以及被配置为从虚拟机接收字节码指令并将该字节代码指令转换为机器指令的编译器。计算系统还包括配置存储器，其被配置为从编译器接收和存储机器指令，并且重新编译存储器被配置为从编译器接收和存储重新编译的机器指令。该系统还包括被配置为从重新编译存储器接收来自编译存储器的指令的软件事务内存引擎，或者在重新编译存储器已经重新编译存储在其中的机器指令的情况下。

68. 发明申请

US20090119654A1 COMPILER FOR OPTIMIZING PROGRAM 失效
标题翻译：编译器优化程序
公开(公告)号：US20090119654A1
公开(公告)日：2009-05-07
申请号：US12259746
申请日：2008-10-28
申请人： Motohiro Kawahito , Hideaki Komatsu , Takao Moriyama
发明人： Motohiro Kawahito , Hideaki Komatsu , Takao Moriyama
IPC分类号： G06F9/45
CPC分类号： G06F8/443 , G06F8/4435
摘要： A compiler system and method for calculating a value to be assigned to a variable for optimizing a program. The apparatus includes a subrange analysis unit for analyzing, for an instruction to assign a value to a variable in the program, a range of the value being assignable to the variable by the instruction, as a subrange of the variable in a case where instruction is executed; a determination unit for determining if the execution result of the program changes if the instruction assigns any value in the subrange of the variable to the variable on the basis of the analyzed subrange of the variable; and a replacement unit for replacing the instruction to assign the value to the variable with an instruction to assign a constant value in the subrange of the variable to the variable.
摘要翻译：用于计算要分配给用于优化程序的变量的值的编译器系统和方法。该装置包括一个子范围分析单元，用于对于在程序中的变量分配值的指令，分析指令中可变量值的范围，作为在指令为执行确定单元，用于如果所述指令基于所分析的所述变量的子范围将所述变量的子范围中的任何值分配给所述变量，则确定所述程序的执行结果是否改变; 以及替换单元，用于用指令将变量的子范围中的常数值分配给变量来替换指定给变量的指令。

69. 发明授权

US07503039B2 Preprocessor to improve the performance of message-passing-based parallel programs on virtualized multi-core processors 失效
标题翻译：预处理器可以提高虚拟化多核处理器上基于消息传递的并行程序的性能
公开(公告)号：US07503039B2
公开(公告)日：2009-03-10
申请号：US11463496
申请日：2006-08-09
申请人： Hiroshi Inoue , Hideaki Komatsu , Takao Moriyama , Moriyoshi Ohara , Yukihiko Sohda
发明人： Hiroshi Inoue , Hideaki Komatsu , Takao Moriyama , Moriyoshi Ohara , Yukihiko Sohda
IPC分类号： G06F9/45 , G06F9/46
CPC分类号： G06F8/45
摘要： Provided is a complier which optimizes parallel processing. The complier records the number of execution cores, which is the number of processor cores that execute a target program. First, the compiler detects a dominant path, which is a candidate of an execution path to be consecutively executed by a single processor core, from a target program. Subsequently, the compiler selects dominant paths with the number not larger than the number of execution cores, and generates clusters of tasks to be executed by a multi-core processor in parallel or consecutively. After that, the compiler computes an execution time for which each of the generated clusters is executed by the processor cores with the number equal to one or each of a plurality natural numbers selected from the natural numbers not larger than the number of execution cores. Then, the compiler selects the number of processor cores to be assigned for execution of each of the clusters based on the computed execution time.
摘要翻译：提供了优化并行处理的编译器。编译器记录执行核心数量，即执行目标程序的处理器核心数。首先，编译器从目标程序检测作为由单个处理器核心连续执行的执行路径的候选者的主路径。随后，编译器选择不大于执行核心数量的主导路径，并且并行或连续地生成由多核处理器执行的任务集群。之后，编译器计算执行时间，其中每个生成的集群由处理器核执行，数量等于从不大于执行核心数的自然数中选择的多个自然数中的一个或每个。然后，编译器基于计算出的执行时间选择要分配用于每个簇的执行的处理器核心的数量。

70. 发明申请

US20090064112A1 TECHNIQUE FOR ALLOCATING REGISTER TO VARIABLE FOR COMPILING 失效
标题翻译：将注册分配给可编辑的变更技术
公开(公告)号：US20090064112A1
公开(公告)日：2009-03-05
申请号：US12133349
申请日：2008-06-04
申请人： Tatsushi Inagaki , Hideaki Komatsu , Takuya Nakaike , Rei Odaira
发明人： Tatsushi Inagaki , Hideaki Komatsu , Takuya Nakaike , Rei Odaira
IPC分类号： G06F9/45
CPC分类号： G06F8/441
摘要： The present invention relates to allocating registers to variables in order to compile a program. In an embodiment of the present invention a compiler apparatus stores interference information indicating an interference relationship between variables, selects a register and allocates the register to each variables in accordance with a predetermined procedure, without allocating the same register to a set of variables having interference relationships. The compiler further replaces multiple variables having the same register allocated thereto with a new variable and generates an interference relationship by merging the interference relationships each concerning one of multiple variables. The compiler further updates interference information according to the generated interference relationship and allocates to each variable in the program using the new variable a register, selected in accordance with the predetermined procedure without allocating the same register to a set of variables having the interference relationships, based on the updated interference information.
摘要翻译：本发明涉及向变量分配寄存器以便编译程序。在本发明的实施例中，编译装置存储指示变量之间的干扰关系的干扰信息，选择寄存器并根据预定的过程将寄存器分配给每个变量，而不向具有干扰关系的一组变量分配相同的寄存器。编译器进一步用新的变量代替具有与其分配的相同寄存器的多个变量，并且通过合并关于多个变量之一的干扰关系来产生干扰关系。编译器根据产生的干扰关系进一步更新干扰信息，并使用新的变量将根据预定过程选择的寄存器分配给程序中的每个变量，而不将相同的寄存器分配给具有干扰关系的一组变量，关于更新的干扰信息。

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