专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US08010716B2 Methods and apparatus for supporting multiple configurations in a multi-processor system 有权
标题翻译：在多处理器系统中支持多种配置的方法和装置
公开(公告)号：US08010716B2
公开(公告)日：2011-08-30
申请号：US12858915
申请日：2010-08-18
申请人： Takeshi Yamazaki , Scott Douglas Clark , Charles Ray Johns , James Allan Kahle
发明人： Takeshi Yamazaki , Scott Douglas Clark , Charles Ray Johns , James Allan Kahle
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F12/0815 , G06F12/0835
摘要： Methods and apparatus provide for interconnecting one or more multiprocessors and one or more external devices through one or more configurable interface circuits, which are adapted for operation in: (i) a first mode to provide a coherent symmetric interface; or (ii) a second mode to provide a non-coherent interface.
摘要翻译：方法和装置提供通过一个或多个可配置接口电路来互连一个或多个多处理器和一个或多个外部设备，其适于在以下操作中操作：（i）提供一致对称接口的第一模式; 或（ii）提供非相干界面的第二模式。

62. 发明授权

US08006000B2 Bridge, processor unit, information processing apparatus, and access control method 有权
标题翻译：桥梁，处理器单元，信息处理设备和访问控制方法
公开(公告)号：US08006000B2
公开(公告)日：2011-08-23
申请号：US11914170
申请日：2007-01-11
申请人： Hideyuki Saito , Takeshi Yamazaki , Yuji Takahashi , Hideki Mitsubayashi
发明人： Hideyuki Saito , Takeshi Yamazaki , Yuji Takahashi , Hideki Mitsubayashi
IPC分类号： G06F13/28 , G06F3/00 , G06F5/00 , G06F13/00
CPC分类号： G06F12/1475 , G06F12/1081
摘要： There is provided a technique of accessing a memory of a processor from a peripheral device, thereby the security is ensured while efficiency is being pursued. An address converter 14 includes an address conversion table for converting an effective address into a physical address. The address conversion table stores the effective address to which an area in a memory of a processor unit 10 is allocated to each peripheral device 30 and identification information of an access source to which access permission is given, in association with each other. When the peripheral device 30 accesses, the address converter 14 determines to permit access to the effective address under the condition that the device identification information, included in an access request packet, by which the peripheral device 30 can be uniquely identified, matches the identification information of the access source corresponding to the effective address, in the address conversion table, designated by the access request packet.
摘要翻译：提供了从外围设备访问处理器的存储器的技术，从而在保持效率的同时确保安全性。地址转换器14包括用于将有效地址转换为物理地址的地址转换表。地址转换表将处理器单元10的存储器中的区域被分配给每个外围设备30的有效地址和彼此相关联地给予访问许可的访问源的标识信息。当外围设备30访问时，地址转换器14在允许外部设备30被唯一标识的访问请求分组中包括的设备识别信息与识别信息匹配的条件下确定允许访问有效地址的访问源对应于有效地址，在地址转换表中，由访问请求分组指定。

63. 发明授权

US07818507B2 Methods and apparatus for facilitating coherency management in distributed multi-processor system 有权
标题翻译：用于促进分布式多处理器系统中的一致性管理的方法和装置
公开(公告)号：US07818507B2
公开(公告)日：2010-10-19
申请号：US11098621
申请日：2005-04-04
申请人： Takeshi Yamazaki , Jeffrey Douglas Brown , Scott Douglas Clark , Charles Ray Johns
发明人： Takeshi Yamazaki , Jeffrey Douglas Brown , Scott Douglas Clark , Charles Ray Johns
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0831 , G06F12/0813 , G06F2212/251 , G06F2212/253
摘要： Methods and apparatus provide for sending a data command from a first of a plurality of devices to a first address concentrator within a first of a plurality of processing systems; selecting one of the other processing systems, the selected processing system having data addressed by the data command stored therein; sending the data command to a first address concentrator of the selected processing system; and broadcasting the data command from the first address concentrator of the selected processing system to a second address concentrator in each of the processing systems.
摘要翻译：方法和装置提供从多个设备中的第一设备向多个处理系统中的第一个内的第一地址集中器发送数据命令; 选择其他处理系统之一，所选择的处理系统具有由其中存储的数据命令寻址的数据; 将所述数据命令发送到所选择的处理系统的第一地址集中器; 以及从所选择的处理系统的第一地址集中器将数据命令广播到每个处理系统中的第二地址集中器。

64. 发明申请

US20100050676A1 COOLING SYSTEM 有权
标题翻译：冷却系统
公开(公告)号：US20100050676A1
公开(公告)日：2010-03-04
申请号：US12515861
申请日：2008-02-06
申请人： Naoyoshi Takamatsu , Takeshi Yamazaki
发明人： Naoyoshi Takamatsu , Takeshi Yamazaki
IPC分类号： F25D31/00
CPC分类号： B60K11/02 , B60K2001/003 , B60K2001/005 , B60L3/0046 , B60L3/0053 , B60L11/123 , B60L11/14 , B60L11/1872 , B60L11/1874 , B60L2200/26 , Y02T10/6217 , Y02T10/7005 , Y02T10/705 , Y02T10/7077 , Y02T90/34
摘要： A cooling system has a configuration in which a cooling system for an inverter device and a motor generator also serves as a cooling system for a battery. In this configuration, a control device performs temperature-raising control of the battery when a battery temperature is below a prescribed temperature lower limit value. The control device controls an operation of a switching valve such that cooling water from a cooling medium path is outputted to a bypass path. Further, if a cooling water temperature is lower than a prescribed temperature, the control device controls the inverter device such that a power loss during a switching operation in a switching element included in the inverter device becomes larger than a power loss during normal control. As a result, the cooling system having a small-sized, low-cost configuration rapidly recovers capacity decline of the battery, which occurs at low temperatures.
摘要翻译：冷却系统具有这样的结构，其中用于逆变器装置的冷却系统和电动发电机也用作电池的冷却系统。在该结构中，当电池温度低于规定的温度下限值时，控制装置进行电池的升温控制。控制装置控制切换阀的操作，使得来自冷却介质路径的冷却水被输出到旁路路径。此外，如果冷却水温度低于规定温度，则控制装置控制逆变器装置，使得包括在逆变器装置中的开关元件的开关操作期间的功率损耗变得大于正常控制期间的功率损耗。结果，具有小型，低成本配置的冷却系统快速恢复在低温下发生的电池的容量下降。

65. 发明申请

US20090222610A1 BRIDGE, INFORMATION PROCESSING DEVICE , AND ACCESS CONTROL METHOD 有权
标题翻译：桥梁，信息处理设备和访问控制方法
公开(公告)号：US20090222610A1
公开(公告)日：2009-09-03
申请号：US12282393
申请日：2006-11-30
申请人： Takeshi Yamazaki , Hideyuki Saito , Yuji Takahashi , Hideki Mitsubayashi
发明人： Takeshi Yamazaki , Hideyuki Saito , Yuji Takahashi , Hideki Mitsubayashi
IPC分类号： G06F13/28
CPC分类号： G06F13/4027 , G06F13/28 , G06F2213/0024
摘要： A downstream port 22 of a bridge 20 connecting a processor unit and a peripheral device acknowledges access from the peripheral device via one of a plurality of downstream channels available for access by the peripheral device to a memory of the processor unit, the downstream channels being virtual channels provided for interfacing with the peripheral device. The router 24 routes the access to upstream channels each assigned a memory bandwidth available for access to the memory, the upstream channels being virtual channels supported by the processor unit. In this process, the router refers to a table storing identifiers of the downstream channels and identifiers of the upstream channels in association with each other so as to allocate to the peripheral device the upstream channel corresponding to the downstream channel used by the peripheral device, in response to the access from the peripheral device.
摘要翻译：连接处理器单元和外围设备的桥接器20的下游端口22通过可用于由外围设备访问的多个下游信道之一确认来自外围设备的访问到处理器单元的存储器，下游信道是虚拟的提供用于与外围设备接口的通道。路由器24将访问路由到每个分配有可用于访问存储器的存储器带宽的上游信道，上行信道是由处理器单元支持的虚拟信道。在这个过程中，路由器是指相互关联地存储下游信道的标识符和上游信道的标识符的表，以便向外围设备分配与外围设备使用的下游信道对应的上行信道，响应来自外围设备的访问。

66. 发明申请

US20090127943A1 Electric Motor, Production Method Of Stator, And Production Method Of Electric Motor 审中-公开
标题翻译：电动机，定子的生产方法和电动机的生产方法
公开(公告)号：US20090127943A1
公开(公告)日：2009-05-21
申请号：US11921210
申请日：2006-05-31
申请人： Eiichi Machida , Takeshi Yamazaki , Hirotatsu Ikeno
发明人： Eiichi Machida , Takeshi Yamazaki , Hirotatsu Ikeno
IPC分类号： H02K15/12
CPC分类号： H02K3/34 , H02K5/08 , H02K15/12 , Y10T29/49009
摘要： Brushless motor (1) which is an electric motor, is provided with a stator unit (3) inserted in and engaged with case (2). A part of the coating material (21) for coating the coil (17) of the stator unit (3) enters the receiving part (13) formed in the bottom part (2B) of the case (2); and the bottom part (2B) of the case (2) and the coil (17) are linked by this coating material (21). While coating, the coating material (21) is dripped from the opening side of the case (2) with the stator unit (3) in the inserted condition in the case (2).
摘要翻译：作为电动机的无刷电动机（1）设置有插入壳体（2）并与其接合的定子单元（3）。用于涂覆定子单元（3）的线圈（17）的涂层材料（21）的一部分进入形成在壳体（2）的底部（2B）中的接收部分（13）中。并且壳体（2）的底部（2B）和线圈（17）由该涂层材料（21）连接。在涂布的同时，将涂料（21）从壳体（2）的开口侧滴下，定子单元（3）处于插入状态（2）中。

67. 发明授权

US07535902B2 Traffic distribution device, traffic distribution method and packet relay method 失效
标题翻译：流量分配装置，流量分配方法和分组中继方法
公开(公告)号：US07535902B2
公开(公告)日：2009-05-19
申请号：US11221189
申请日：2005-09-07
申请人： Takeshi Yamazaki , Naohiko Takamura
发明人： Takeshi Yamazaki , Naohiko Takamura
IPC分类号： H04L12/28
CPC分类号： H04L29/12009 , H04L29/12028 , H04L29/12839 , H04L61/103 , H04L61/6022 , H04L67/1002 , H04L67/1023
摘要： Disclosed is a traffic distribution device, which is used in a way that connects to a 0-th network, a first network including one or more servers and to a second network connected to the first network and including M-pieces of high-order layer processing devices associated with 0 through M-1, capable of improving a throughput of a network without changing a server sided default gateway address. The traffic distribution device has first packet relay unit translating a packet containing a predetermined destination IP address from the 0-th network into a packet in which a destination MAC address is set as a first network sided MAC address of the high-order layer processing device, which MAC address is associated with a remainder value obtained by dividing a source IP address of the packet by M, and transmitting this packet onto the first network; and second packet relay unit translating the packet from the second network into a packet in which a destination MAC address is a second network sided MAC address of the high-order layer processing device, which MAC address is associated with a remainder value obtained by dividing the destination IP address of the packet by M, and transmitting this packet onto the second network.
摘要翻译：公开了一种流量分配装置，其以连接到第0网络，包括一个或多个服务器的第一网络和连接到第一网络的第二网络的方式使用，并且包括M个高阶层处理与0到M-1相关联的设备，能够改善网络的吞吐量而不改变服务器端的默认网关地址。业务分配装置具有第一分组中继单元，将包含预定目的地IP地址的分组从第0网络转换为目的地MAC地址被设置为高阶层处理设备的第一网络侧MAC地址的分组该MAC地址与通过将该分组的源IP地址除以M而获得的余数值相关联，并将该分组发送到第一网络; 以及第二分组中继单元将分组从第二网络转换成其中目的地MAC地址是高阶层处理设备的第二网络侧MAC地址的分组，该MAC地址与通过划分 M的目的地IP地址，并将该数据包发送到第二个网络。

68. 发明授权

US07505457B2 Method and apparatus for providing an interconnection network function 有权
标题翻译：提供互联网络功能的方法和装置
公开(公告)号：US07505457B2
公开(公告)日：2009-03-17
申请号：US11108971
申请日：2005-04-19
申请人： Takeshi Yamazaki
发明人： Takeshi Yamazaki
IPC分类号： H04L12/50
CPC分类号： H04Q3/521 , G06F15/17393 , H04L49/101 , H04L49/25 , H04L49/358 , H04L69/08 , H04L69/18 , H04L69/32 , H04Q2213/1302 , H04Q2213/1304 , H04Q2213/13076 , H04Q2213/13215 , H04Q2213/13292
摘要： Method and apparatus are provided for improved connection of devices and lower latency of communications between devices of a massively parallel network. In particular, method and apparatus are provided for cross-bar switches, a multiple protocol interface device, a low latency upper communication protocol layer, addressing and remote direct memory access over a massively parallel network.
摘要翻译：提供了用于改进设备连接和较大并行网络的设备间通信延迟较低的方法和装置。特别地，提供了用于跨条形交换机，多协议接口设备，低延迟上层通信协议层，通过大规模并行网络的寻址和远程直接存储器访问的方法和装置。

69. 发明授权

US07461240B2 Command execution controlling apparatus, command execution instructing apparatus and command execution controlling method 有权
标题翻译：命令执行控制装置，命令执行指令装置和命令执行控制方法
公开(公告)号：US07461240B2
公开(公告)日：2008-12-02
申请号：US11432107
申请日：2006-05-11
申请人： Katsushi Ohtsuka , Takeshi Yamazaki
发明人： Katsushi Ohtsuka , Takeshi Yamazaki
IPC分类号： G06F13/28
CPC分类号： G06F9/3879 , G06T1/20
摘要： The issuance timing of commands received from and transmitted to among a plurality of processing units is controlled efficiently. An execution command storage unit 222 stores execution commands, received from an external command transmitting entity, where a predetermined upper-limit number of execution commands to be stored is set. An execution command issuing unit 230 retrieves the execution commands stored and issues them to a command execution entity. An adjustment command storage unit 224 stores the adjustment command, transmitted from the command transmitting entity, to adjust the issuance order of the execution commands. A storage area for storing the execution commands to be stored in the execution command storage unit 222 and a storage area for storing the adjustment command to be stored in the adjustment command storage unit 224 are separately provided. When the adjustment command is stored, the execution command issuing unit 230 issues an execution command received after the reception of the adjustment command, on the condition that the issuance of execution commands received prior to the reception of the adjustment command has been completed.
摘要翻译：有效地控制从多个处理单元接收并发送的命令的发布定时。执行命令存储单元222存储从外部命令发送实体接收的执行命令，其中设置要存储的预定的上限执行命令。执行命令发布单元230检索存储的执行命令并将其发布到命令执行实体。调整命令存储单元224存储从命令发送实体发送的调整命令来调整执行命令的发布顺序。分别设置用于存储要存储在执行命令存储单元222中的执行命令的存储区域和用于存储要存储在调整命令存储单元224中的调整命令的存储区域。当存储调整命令时，执行命令发布单元230在接收到调整命令之后接收到的执行命令的发出已经完成的情况下，发出接收到调整命令之后接收到的执行命令。

70. 发明授权

US07383427B2 Multi-scalar extension for SIMD instruction set processors 有权
标题翻译： SIMD指令集处理器的多标量扩展
公开(公告)号：US07383427B2
公开(公告)日：2008-06-03
申请号：US11110307
申请日：2005-04-20
申请人： Takeshi Yamazaki
发明人： Takeshi Yamazaki
IPC分类号： G06F9/00
CPC分类号： G06F9/30101 , G06F9/3851 , G06F9/3867 , G06F9/3885 , G06F9/3887
摘要： A method is provided for executing a plurality of parallel executable sequences of instructions on a processor having a plurality of execution units operated by a single instruction unit. The method includes a) detecting a plurality of sequences of instructions adapted for parallel execution from instructions being provided to the processor, wherein each sequence is adapted for execution by a subset of the plurality of execution units and b) storing information representing a stall status of the execution units. Then, a step c) is performed, wherein, for each unexecuted sequence of the plurality of sequences: i) all of the plurality of execution units other than the subset which corresponds to the unexecuted sequence are stalled, and ii) the sequence of instructions is executed by the corresponding subset. Thereafter, it is determined in a step d) whether a current stall status of the plurality of execution units matches the stall status represented by the stored information. When there is no match, the steps b) through d) are repeated until there is a match in which the current stall status represented by the stored information matches the stored information.
摘要翻译：提供了一种用于在具有由单个指令单元操作的多个执行单元的处理器上执行多个并行可执行指令序列的方法。该方法包括：a）从提供给处理器的指令检测适合于并行执行的多个指令序列，其中每个序列适于由多个执行单元的子集执行，以及b）存储表示第执行单位。然后，执行步骤c），其中对于多个序列中的每个未执行的序列：i）除了对应于未执行的序列的子集之外的所有多个执行单元都被停止，以及ii）指令序列由相应的子集执行。此后，在步骤d）中确定多个执行单元的当前失速状态是否与由所存储的信息表示的停顿状态相匹配。当不匹配时，重复步骤b）至d），直到存在由所存储的信息表示的当前停顿状态与存储的信息匹配的匹配。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式