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1. 发明授权

US08185683B2 Bridge, information processing system, and access control method 失效
标题翻译：桥梁，信息处理系统和访问控制方法
公开(公告)号：US08185683B2
公开(公告)日：2012-05-22
申请号：US12282391
申请日：2007-01-11
申请人： Takeshi Yamazaki , Hideyuki Saito , Yuji Takahashi , Hideki Mitsubayashi
发明人： Takeshi Yamazaki , Hideyuki Saito , Yuji Takahashi , Hideki Mitsubayashi
IPC分类号： G06F13/36 , G06F13/00
CPC分类号： G06F13/4027 , H04L12/4625 , H04L29/12009 , H04L49/25 , H04L61/00 , H04L67/1097
摘要： Transparency of resources is provided and ordering in an access is guaranteed between nodes on a computer network. In an information processing system in which a plurality of processor units are connected to each other by a switch, a global address space is introduced into which effective addresses of the processor units are mapped and which is shared by the plurality of processor units. In response to an access request packet issued by a processor unit and designating an effective address of a target node, a bridge for routing an input and output bus of a processor unit to an input and output bus of the switch converts the effective address of the target node into a global address by appending to the packet a node identification number identifying the target node, and outputs the access request packet designating the global address to the switch. After an access request packet for a write operation is output, the bridge confirms whether the write operation is completed in a target node.
摘要翻译：提供资源的透明度，并在计算机网络上的节点之间保证访问中的顺序。在通过交换机将多个处理器单元彼此连接的信息处理系统中，引入了全局地址空间，其中映射了处理器单元的有效地址，并且由多个处理器单元共享该地址空间。响应于由处理器单元发出的访问请求分组并指定目标节点的有效地址，用于将处理器单元的输入和输出总线路由到交换机的输入和输出总线的桥接器转换有效地址通过向分组附加识别目标节点的节点标识号，将目标节点分配成全局地址，并将指定全局地址的接入请求分组输出到交换机。在输出用于写入操作的访问请求分组之后，桥接器确认目标节点中的写入操作是否完成。

2. 发明授权

US08006000B2 Bridge, processor unit, information processing apparatus, and access control method 有权
标题翻译：桥梁，处理器单元，信息处理设备和访问控制方法
公开(公告)号：US08006000B2
公开(公告)日：2011-08-23
申请号：US11914170
申请日：2007-01-11
申请人： Hideyuki Saito , Takeshi Yamazaki , Yuji Takahashi , Hideki Mitsubayashi
发明人： Hideyuki Saito , Takeshi Yamazaki , Yuji Takahashi , Hideki Mitsubayashi
IPC分类号： G06F13/28 , G06F3/00 , G06F5/00 , G06F13/00
CPC分类号： G06F12/1475 , G06F12/1081
摘要： There is provided a technique of accessing a memory of a processor from a peripheral device, thereby the security is ensured while efficiency is being pursued. An address converter 14 includes an address conversion table for converting an effective address into a physical address. The address conversion table stores the effective address to which an area in a memory of a processor unit 10 is allocated to each peripheral device 30 and identification information of an access source to which access permission is given, in association with each other. When the peripheral device 30 accesses, the address converter 14 determines to permit access to the effective address under the condition that the device identification information, included in an access request packet, by which the peripheral device 30 can be uniquely identified, matches the identification information of the access source corresponding to the effective address, in the address conversion table, designated by the access request packet.
摘要翻译：提供了从外围设备访问处理器的存储器的技术，从而在保持效率的同时确保安全性。地址转换器14包括用于将有效地址转换为物理地址的地址转换表。地址转换表将处理器单元10的存储器中的区域被分配给每个外围设备30的有效地址和彼此相关联地给予访问许可的访问源的标识信息。当外围设备30访问时，地址转换器14在允许外部设备30被唯一标识的访问请求分组中包括的设备识别信息与识别信息匹配的条件下确定允许访问有效地址的访问源对应于有效地址，在地址转换表中，由访问请求分组指定。

3. 发明申请

US20090222610A1 BRIDGE, INFORMATION PROCESSING DEVICE , AND ACCESS CONTROL METHOD 有权
标题翻译：桥梁，信息处理设备和访问控制方法
公开(公告)号：US20090222610A1
公开(公告)日：2009-09-03
申请号：US12282393
申请日：2006-11-30
申请人： Takeshi Yamazaki , Hideyuki Saito , Yuji Takahashi , Hideki Mitsubayashi
发明人： Takeshi Yamazaki , Hideyuki Saito , Yuji Takahashi , Hideki Mitsubayashi
IPC分类号： G06F13/28
CPC分类号： G06F13/4027 , G06F13/28 , G06F2213/0024
摘要： A downstream port 22 of a bridge 20 connecting a processor unit and a peripheral device acknowledges access from the peripheral device via one of a plurality of downstream channels available for access by the peripheral device to a memory of the processor unit, the downstream channels being virtual channels provided for interfacing with the peripheral device. The router 24 routes the access to upstream channels each assigned a memory bandwidth available for access to the memory, the upstream channels being virtual channels supported by the processor unit. In this process, the router refers to a table storing identifiers of the downstream channels and identifiers of the upstream channels in association with each other so as to allocate to the peripheral device the upstream channel corresponding to the downstream channel used by the peripheral device, in response to the access from the peripheral device.
摘要翻译：连接处理器单元和外围设备的桥接器20的下游端口22通过可用于由外围设备访问的多个下游信道之一确认来自外围设备的访问到处理器单元的存储器，下游信道是虚拟的提供用于与外围设备接口的通道。路由器24将访问路由到每个分配有可用于访问存储器的存储器带宽的上游信道，上行信道是由处理器单元支持的虚拟信道。在这个过程中，路由器是指相互关联地存储下游信道的标识符和上游信道的标识符的表，以便向外围设备分配与外围设备使用的下游信道对应的上行信道，响应来自外围设备的访问。

4. 发明授权

US08095718B2 Bridge, information processor, and access control method 有权
标题翻译：桥梁，信息处理器和访问控制方法
公开(公告)号：US08095718B2
公开(公告)日：2012-01-10
申请号：US12282393
申请日：2006-11-30
申请人： Takeshi Yamazaki , Hideyuki Saito , Yuji Takahashi , Hideki Mitsubayashi
发明人： Takeshi Yamazaki , Hideyuki Saito , Yuji Takahashi , Hideki Mitsubayashi
IPC分类号： G06F13/00
CPC分类号： G06F13/4027 , G06F13/28 , G06F2213/0024
摘要： A downstream port 22 of a bridge 20 connecting a processor unit and a peripheral device acknowledges access from the peripheral device via one of a plurality of downstream channels available for access by the peripheral device to a memory of the processor unit, the downstream channels being virtual channels provided for interfacing with the peripheral device. The router 24 routes the access to upstream channels each assigned a memory bandwidth available for access to the memory, the upstream channels being virtual channels supported by the processor unit. In this process, the router refers to a table storing identifiers of the downstream channels and identifiers of the upstream channels in association with each other so as to allocate to the peripheral device the upstream channel corresponding to the downstream channel used by the peripheral device, in response to the access from the peripheral device.
摘要翻译：连接处理器单元和外围设备的桥接器20的下游端口22通过可用于由外围设备访问的多个下游信道之一来确认来自外围设备的访问到处理器单元的存储器，下游信道是虚拟的提供用于与外围设备接口的通道。路由器24将访问路由到每个分配有可用于访问存储器的存储器带宽的上游信道，上行信道是由处理器单元支持的虚拟信道。在这个过程中，路由器是指相互关联地存储下游信道的标识符和上游信道的标识符的表，以便向外围设备分配与外围设备使用的下游信道对应的上行信道，响应来自外围设备的访问。

5. 发明授权

US07552270B2 Signal transmission method, bridge unit, and information processing apparatus 有权
标题翻译：信号传输方法，桥接单元和信息处理装置
公开(公告)号：US07552270B2
公开(公告)日：2009-06-23
申请号：US11651417
申请日：2007-01-09
申请人： Hideki Mitsubayashi , Takeshi Yamazaki , Hideyuki Saito , Yuji Takahashi
发明人： Hideki Mitsubayashi , Takeshi Yamazaki , Hideyuki Saito , Yuji Takahashi
IPC分类号： G06F13/00
CPC分类号： G06F13/4027
摘要： An information processing apparatus having a fat tree structure, in which signal transmission across node columns managed by respective processor units is performed through end point bridges included in bridge chips. In this transmission method, the bridge chips perform routing by using node IDs that are given to the respective node columns and levels that indicate the hierarchical depths of the bridge chips, thereby selecting the shortest routes of signals.
摘要翻译：具有胖树结构的信息处理装置，其中通过包括在桥芯片中的端点桥执行由各个处理器单元管理的节点列之间的信号传输。在这种传输方法中，桥芯片通过使用给予各个节点列的节点ID和指示桥接芯片的分层深度的电平来执行路由，从而选择最短的信号路由。

6. 发明申请

US20070168594A1 Signal transmission method, bridge unit, and information processing apparatus 有权
标题翻译：信号传输方法，桥接单元和信息处理装置
公开(公告)号：US20070168594A1
公开(公告)日：2007-07-19
申请号：US11651417
申请日：2007-01-09
申请人： Hideki Mitsubayashi , Takeshi Yamazaki , Hideyuki Saito , Yuji Takahashi
发明人： Hideki Mitsubayashi , Takeshi Yamazaki , Hideyuki Saito , Yuji Takahashi
IPC分类号： G06F13/36
CPC分类号： G06F13/4027
摘要： An information processing apparatus having a fat tree structure, in which signal transmission across node columns managed by respective processor units is performed through end point bridges included in bridge chips. In this transmission method, the bridge chips perform routing by using node IDs that are given to the respective node columns and levels that indicate the hierarchical depths of the bridge chips, thereby selecting the shortest routes of signals.
摘要翻译：具有胖树结构的信息处理装置，其中通过包括在桥芯片中的端点桥执行由各个处理器单元管理的节点列之间的信号传输。在这种传输方法中，桥芯片通过使用给予各个节点列的节点ID和指示桥接芯片的分层深度的电平来执行路由，从而选择最短的信号路由。

7. 发明申请

US20090235048A1 INFORMATION PROCESSING APPARATUS, SIGNAL TRANSMISSION METHOD, AND BRIDGE 审中-公开
标题翻译：信息处理设备，信号传输方法和桥梁
公开(公告)号：US20090235048A1
公开(公告)日：2009-09-17
申请号：US12159040
申请日：2006-11-08
申请人： Hideki Mitsubayashi , Takeshi Yamazaki , Hideyuki Saito , Yuji Takahashi
发明人： Hideki Mitsubayashi , Takeshi Yamazaki , Hideyuki Saito , Yuji Takahashi
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F13/404
摘要： Introduced is an end-point bridge that relays an end point—formed by an external bus in a device tree managed by a first processor unit and an end point formed by an external bus in a device tree managed by a second processor unit. A conversion unit in the end-point bridge replaces a requestor ID contained in an access request packet, for example, which has reached the end point, to the ID of the end point from the ID of a host bridge. The ID of the host bridge is stored in a memory in a manner that the ID of the host bridge is associated with a tag of the packet, and is used to return the requestor ID when a response packet to the request reaches the end point.
摘要翻译：引入了一种端点桥接器，其将由第一处理器单元管理的设备树中的由外部总线形成的端点和由第二处理器单元管理的设备树中的外部总线形成的端点中继。端点桥接器中的转换单元从主桥ID的ID替换已经到达端点的接入请求分组中的请求者ID到终点的ID。主桥的ID以存储在主机桥的ID与分组的标签相关联的方式存储在存储器中，并且当请求的响应分组到达终点时用于返回请求者ID。

8. 发明申请

US20090216921A1 BRIDGE, PROCESSOR UNIT, INFORMATION PROCESSING APPARATUS, AND ACCESS CONTROL METHOD 有权
标题翻译：桥梁，处理器单元，信息处理装置和访问控制方法
公开(公告)号：US20090216921A1
公开(公告)日：2009-08-27
申请号：US11914170
申请日：2007-01-11
申请人： Hideyuki Saito , Takeshi Yamazaki , Yuji Takahashi , Hideki Mitsubayashi
发明人： Hideyuki Saito , Takeshi Yamazaki , Yuji Takahashi , Hideki Mitsubayashi
IPC分类号： G06F3/00 , G06F12/02
CPC分类号： G06F12/1475 , G06F12/1081
摘要： There is provided a technique of accessing a memory of a processor from a peripheral device, thereby the security is ensured while efficiency is being pursued. An address converter 14 includes an address conversion table for converting an effective address into a physical address. The address conversion table stores the effective address to which an area in a memory of a processor unit 10 is allocated to each peripheral device 30 and identification information of an access source to which access permission is given, in association with each other. When the peripheral device 30 accesses, the address converter 14 determines to permit access to the effective address under the condition that the device identification information, included in an access request packet, by which the peripheral device 30 can be uniquely identified, matches the identification information of the access source corresponding to the effective address, in the address conversion table, designated by the access request packet.
摘要翻译：提供了从外围设备访问处理器的存储器的技术，从而在保持效率的同时确保安全性。地址转换器14包括用于将有效地址转换为物理地址的地址转换表。地址转换表将处理器单元10的存储器中的区域被分配给每个外围设备30的有效地址和彼此相关联地给予访问许可的访问源的标识信息。当外围设备30访问时，地址转换器14在允许外部设备30被唯一标识的访问请求分组中包括的设备识别信息与识别信息匹配的条件下确定允许访问有效地址的访问源对应于有效地址，在地址转换表中，由访问请求分组指定。

9. 发明授权

US08996440B2 Information processing apparatus, information processing method, and program 有权
标题翻译：信息处理装置，信息处理方法和程序
公开(公告)号：US08996440B2
公开(公告)日：2015-03-31
申请号：US13474159
申请日：2012-05-17
申请人： Takeshi Yamazaki , Seiji Wada , Yoshihiro Wakita , Koji Kashima , Natsuki Kimura
发明人： Takeshi Yamazaki , Seiji Wada , Yoshihiro Wakita , Koji Kashima , Natsuki Kimura
IPC分类号： G06N5/02 , G06Q10/10
CPC分类号： G06Q10/109
摘要： An information processing apparatus configured to create a schedule to be presented to a user includes an estimation unit and a creation unit. The estimation unit is configured to estimate whether or not the user acts in accordance with a first schedule including a task to do for accomplishing a preset aim. The creation unit is configured to create, when estimated that the user does not act in accordance with the first schedule, a new second schedule for accomplishing the aim from a state of the user who acts without following the first schedule.
摘要翻译：被配置为创建要呈现给用户的日程表的信息处理设备包括估计单元和创建单元。估计单元被配置为估计用户是否根据包括要完成预设目标的任务的第一调度进行动作。创建单元被配置为当估计用户不按照第一时间表行动时创建新的第二计划，用于从不遵循第一进度的行为的用户的状态完成目标。

10. 发明授权

US08774895B2 Electroencephalographic headset 有权
标题翻译：脑电耳机
公开(公告)号：US08774895B2
公开(公告)日：2014-07-08
申请号：US13616185
申请日：2012-09-14
申请人： Seiji Wada , Takeshi Yamazaki , Natsuki Kimura , Yoshihiro Wakita , Koji Kashima , Tomiji Tanaka , Mitsuhiro Nakamura , Tatsumi Sakaguchi , Haruhiko Soma , Takuro Yamamoto
发明人： Seiji Wada , Takeshi Yamazaki , Natsuki Kimura , Yoshihiro Wakita , Koji Kashima , Tomiji Tanaka , Mitsuhiro Nakamura , Tatsumi Sakaguchi , Haruhiko Soma , Takuro Yamamoto
IPC分类号： A61B5/0478 , A61B5/00
CPC分类号： A61B5/0478 , A61B5/6803 , A61B5/6814 , A61B5/6843
摘要： An electroencephalographic headset includes: a supporter that includes expanding and contracting wires each having expansion and contraction properties and is to be attached to a head of a user by expansion and contraction of each of the expanding and contracting wires; and a plurality of electrodes that are provided to the supporter in defined placement.
摘要翻译：脑电耳机包括：支撑件，其包括每个具有伸缩性能的伸缩线，并且通过每个伸缩线的伸缩来附接到使用者的头部; 以及以规定的位置设置在支撑体上的多个电极。

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