专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明申请

US20090244866A1 Circuit Device 有权
标题翻译：电路设备
公开(公告)号：US20090244866A1
公开(公告)日：2009-10-01
申请号：US12457295
申请日：2009-06-05
申请人： Masaya Kawano , Yasutaka Nakashia
发明人： Masaya Kawano , Yasutaka Nakashia
IPC分类号： H05K1/16 , H01F5/00
CPC分类号： H01F38/14 , H01F17/0013 , H01F27/2804 , H01F27/40 , H01F2017/0086 , H01F2027/2809 , H01F2038/143 , H01L23/535 , H01L27/1203 , H01L28/10 , H01L29/0649 , H01L2224/4813 , H01L2224/48137 , H01L2924/00014 , H01L2924/30107 , H01L2924/00 , H01L2224/45099
摘要： The circuit device includes a first transmitting inductor, a first insulating layer, a first receiving inductor, and a second receiving inductor. The first transmitting inductor is constituted of a helical conductive pattern and receives a transmitted signal. The first receiving inductor is located in a region overlapping the first transmitting inductor through the first insulating layer. The first receiving inductor is constituted of a helical conductive pattern, and generates a received signal corresponding to the transmitted signal input to the first transmitting inductor. The second receiving inductor is connected in series to the first receiving inductor, and constituted of a helical conductive pattern. The second receiving inductor generates a voltage in an opposite direction to that generated by the first receiving inductor, in response to a magnetic field of the same direction.
摘要翻译：电路装置包括第一发射电感器，第一绝缘层，第一接收电感器和第二接收电感器。第一发射电感器由螺旋导电图案构成，并接收发射信号。第一接收电感器位于通过第一绝缘层与第一发射电感器重叠的区域中。第一接收电感器由螺旋导电图案构成，并且产生对应于输入到第一发射电感器的发射信号的接收信号。第二接收电感器与第一接收电感器串联连接，并由螺旋导电图案构成。响应于相同方向的磁场，第二接收电感器产生与由第一接收电感器产生的电压相反的电压。

62. 发明申请

US20060006501A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060006501A1
公开(公告)日：2006-01-12
申请号：US11167121
申请日：2005-06-28
申请人： Masaya Kawano
发明人： Masaya Kawano
IPC分类号： H01L29/06
CPC分类号： H01L25/0657 , H01L23/481 , H01L2224/0554 , H01L2224/05573 , H01L2224/13025 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor device 1 has a semiconductor chip 10. The semiconductor chip 10 is constituted as having a semiconductor substrate 12 and an interlayer insulating film 14 on the semiconductor substrate 12. The semiconductor substrate 12 has a plurality of through electrodes 22 (first through electrodes) and a plurality of through electrodes 24 (second through electrodes) formed therein. On the top surface S1 (first surface) of the semiconductor chip 10, there are provided connection terminals 32 (first connection terminals) and connection terminals 34 (second connection terminals). The connection terminals 32, 34 are connected to the through electrodes 22, 24, respectively. The connection terminals 32 herein are disposed at positions overlapping the through electrodes 22 in a plan view. On the other hand, the connection terminals 34 are disposed at positions not overlapping the through electrodes 24 in a plan view.
摘要翻译：半导体器件1具有半导体芯片10。半导体芯片10构成为在半导体基板12上具有半导体基板12和层间绝缘膜14.半导体基板12具有多个贯通电极22（第一贯通电极）和多个贯通电极24（第二贯通电极电极）。在半导体芯片10的上表面S1（第一表面）上设置有连接端子32（第一连接端子）和连接端子34（第二连接端子）。连接端子32,34分别与贯通电极22,24连接。这里的连接端子32设置在俯视图中与贯通电极22重叠的位置。另一方面，连接端子34在平面图中设置在不与贯通电极24重叠的位置。

63. 发明授权

US08310039B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08310039B2
公开(公告)日：2012-11-13
申请号：US13227065
申请日：2011-09-07
申请人： Masaya Kawano
发明人： Masaya Kawano
IPC分类号： H01L23/48
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/11 , H01L2224/05001 , H01L2224/05009 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/13099 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01072 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/10329 , H01L2924/13091 , H01L2924/19043 , H01L2924/30105 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor device having a through electrode excellent in performance as for an electrode and manufacturing stability is provided. There is provided a through electrode composed of a conductive small diameter plug and a conductive large diameter plug on a semiconductor device. A cross sectional area of the small diameter plug is made larger than a cross sectional area and a diameter of a connection plug, and is made smaller than a cross sectional area and a diameter of the large diameter plug. In addition, a protruding portion formed in such a way that the small diameter plug is projected from the silicon substrate is put into an upper face of the large diameter plug. Further, an upper face of the small diameter plug is connected to a first interconnect.
摘要翻译：提供一种具有电极性能优良的通电极和制造稳定性的半导体装置。在半导体器件上设置有由导电性小直径插头和导电性大直径插头构成的贯通电极。小直径插头的横截面面积大于连接插头的横截面积和直径，并且被制成小于大直径插头的横截面面积和直径。此外，将形成为使得小直径插头从硅衬底突出的方式形成的突出部分放入大直径插头的上表面。此外，小直径插头的上表面连接到第一互连。

64. 发明授权

US07898073B2 Semiconductor device and semiconductor module employing thereof 有权
标题翻译：半导体装置及其半导体模块
公开(公告)号：US07898073B2
公开(公告)日：2011-03-01
申请号：US12820478
申请日：2010-06-22
申请人： Satoshi Matsui , Masaya Kawano
发明人： Satoshi Matsui , Masaya Kawano
IPC分类号： H01L23/04
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/585 , H01L24/05 , H01L2224/0401 , H01L2224/05009 , H01L2224/05551 , H01L2224/05552 , H01L2224/05553 , H01L2224/05555 , H01L2224/13025 , H01L2224/14181 , H01L2224/16 , H01L2224/16146 , H01L2224/16225 , H01L2225/06513
摘要： A semiconductor device is provided with a silicon substrate and a structure filled in a through hole that has a rectangular cross section and extends through the silicon substrate. The structure comprises a pipe-shaped through electrode, stripe-shaped through electrodes, silicons, a first insulating film, a second insulating film and a third insulating film. The pipe-shaped through electrode is utilized as a pipe-shaped electric conductor that extends through the silicon substrate. In addition, the stripe-shaped through electrodes are provided in the interior of the pipe-shaped through electrode so that the stripe-shaped through electrodes extend through the silicon substrate and is spaced away from the pipe-shaped through electrode. A plurality of through electrodes are provided in substantially parallel within the inner region of the pipe-shaped through electrode.
摘要翻译：半导体器件设置有硅衬底和填充有通孔的结构，其具有矩形横截面并延伸穿过硅衬底。该结构包括管状贯通电极，条形穿通电极，硅，第一绝缘膜，第二绝缘膜和第三绝缘膜。管状贯通电极用作延伸穿过硅衬底的管状电导体。此外，条状贯通电极设置在管状贯通电极的内部，使得条状贯通电极延伸穿过硅衬底并与管状通电极间隔开。多个贯通电极大致平行地设置在管状贯通电极的内部区域内。

65. 发明申请

US20100258918A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE EMPLOYING THEREOF 有权
标题翻译：半导体器件和半导体器件
公开(公告)号：US20100258918A1
公开(公告)日：2010-10-14
申请号：US12820478
申请日：2010-06-22
申请人： Satoshi Matsui , Masaya Kawano
发明人： Satoshi Matsui , Masaya Kawano
IPC分类号： H01L23/538 , H01L23/48
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/585 , H01L24/05 , H01L2224/0401 , H01L2224/05009 , H01L2224/05551 , H01L2224/05552 , H01L2224/05553 , H01L2224/05555 , H01L2224/13025 , H01L2224/14181 , H01L2224/16 , H01L2224/16146 , H01L2224/16225 , H01L2225/06513
摘要： A semiconductor device is provided with a silicon substrate and a structure filled in a through hole that has a rectangular cross section and extends through the silicon substrate. The structure comprises a pipe-shaped through electrode, stripe-shaped through electrodes, silicons, a first insulating film, a second insulating film and a third insulating film. The pipe-shaped through electrode is utilized as a pipe-shaped electric conductor that extends through the silicon substrate. In addition, the stripe-shaped through electrodes are provided in the interior of the pipe-shaped through electrode so that the stripe-shaped through electrodes extend through the silicon substrate and is spaced away from the pipe-shaped through electrode. A plurality of through electrodes are provided in substantially parallel within the inner region of the pipe-shaped through electrode.
摘要翻译：半导体器件设置有硅衬底和填充有通孔的结构，其具有矩形横截面并延伸穿过硅衬底。该结构包括管状贯通电极，条形穿通电极，硅，第一绝缘膜，第二绝缘膜和第三绝缘膜。管状贯通电极用作延伸穿过硅衬底的管状电导体。此外，条状贯通电极设置在管状贯通电极的内部，使得条状贯通电极延伸穿过硅衬底并与管状通电极间隔开。多个贯通电极大致平行地设置在管状贯通电极的内部区域内。

66. 发明申请

US20090215261A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090215261A1
公开(公告)日：2009-08-27
申请号：US12427366
申请日：2009-04-21
申请人： Masaya Kawano
发明人： Masaya Kawano
IPC分类号： H01L21/768
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/11 , H01L2224/05001 , H01L2224/05009 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/13099 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01072 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/10329 , H01L2924/13091 , H01L2924/19043 , H01L2924/30105 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor device having a through electrode excellent in performance as for an electrode and manufacturing stability is provided. There is provided a through electrode composed of a conductive small diameter plug and a conductive large diameter plug on a semiconductor device. A cross sectional area of the small diameter plug is made larger than a cross sectional area and a diameter of a connection plug, and is made smaller than a cross sectional area and a diameter of the large diameter plug. In addition, a protruding portion formed in such a way that the small diameter plug is projected from the silicon substrate is put into an upper face of the large diameter plug. Further, an upper face of the small diameter plug is connected to a first interconnect.
摘要翻译：提供一种具有电极性能优良的通电极和制造稳定性的半导体装置。在半导体器件上设置有由导电性小直径插头和导电性大直径插头构成的贯通电极。小直径插头的横截面面积大于连接插头的横截面积和直径，并且被制成小于大直径插头的横截面面积和直径。此外，将形成为使得小直径插头从硅衬底突出的方式形成的突出部分放入大直径插头的上表面。此外，小直径插头的上表面连接到第一互连。

67. 发明申请

US20080303136A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080303136A1
公开(公告)日：2008-12-11
申请号：US12135355
申请日：2008-06-09
申请人： Kentaro Mori , Shintaro Yamamichi , Hideya Murai , Takuo Funaya , Masaya Kawano , Takehiko Maeda , Kouji Soejima
发明人： Kentaro Mori , Shintaro Yamamichi , Hideya Murai , Takuo Funaya , Masaya Kawano , Takehiko Maeda , Kouji Soejima
IPC分类号： H01L23/15 , H01L21/58
CPC分类号： H01L21/6835 , H01L23/5389 , H01L23/544 , H01L24/19 , H01L24/24 , H01L2221/68345 , H01L2223/5442 , H01L2223/54426 , H01L2223/54473 , H01L2223/54486 , H01L2224/04105 , H01L2224/24226 , H01L2224/32225 , H01L2224/73267 , H01L2224/82039 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01041 , H01L2924/01046 , H01L2924/01047 , H01L2924/01056 , H01L2924/01057 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/12044 , H01L2924/15174 , H01L2924/15788 , H01L2924/181 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3011 , Y10S438/977 , H01L2924/00
摘要： A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material so as to cover the semiconductor element; and a via, a wiring layer, an insulation layer, an external terminal, and a solder resist are then formed. The transparent board is then peeled from the semiconductor device through the use of the release material. A chip can thereby be mounted with high precision, there is no need to provide a positioning mark during mounting of the chip on the substrate in the manufacturing process, and the substrate can easily be removed. As a result, a semiconductor device having high density and a thin profile can be manufactured at low cost.
摘要翻译：透明板位于设置有定位标记的支撑板上，并且设置有释放材料。然后将半导体元件定位成使得电极元件面向上，然后移除支撑板。然后在剥离材料上形成绝缘树脂以覆盖半导体元件; 然后形成通孔，布线层，绝缘层，外部端子和阻焊剂。然后透明板通过使用释放材料从半导体器件剥离。因此，可以高精度地安装芯片，在制造过程中不需要在将芯片安装在基板上时提供定位标记，并且可以容易地去除基板。结果，可以以低成本制造具有高密度和薄型的半导体器件。

68. 发明授权

US07405472B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07405472B2
公开(公告)日：2008-07-29
申请号：US11762793
申请日：2007-06-14
申请人： Masaya Kawano
发明人： Masaya Kawano
IPC分类号： H01L23/02
CPC分类号： H01L23/3128 , H01L23/481 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L2224/05001 , H01L2224/05026 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/13025 , H01L2224/16145 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2225/06555 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/19041 , H01L2224/05099
摘要： A semiconductor device, which is constituted in such a way that a pad portion of a logic chip is connected to an element region of a semiconductor chip with a bump bonding, is capable of achieving high speed operability of the elements, because delay of transmission of an electrical signal is suppressed. a logic chip is directly connected to a DRAM, therefore, it is possible to suppress an increase of load capacitance caused by interconnects, and securing a wide bus width by a multiple pin connection. As a result, it becomes possible to enhance performance of the semiconductor device upon suppressing delay of information transmission from the logic chip to the DRAM.
摘要翻译：一种半导体器件，其以逻辑芯片的焊盘部分连接到具有凸块焊接的半导体芯片的元件区域的方式构成，因此能够实现元件的高速可操作性，因为延迟传输电信号被抑制。逻辑芯片直接连接到DRAM，因此，可以抑制由互连引起的负载电容的增加，并且通过多引脚连接来确保宽的总线宽度。结果，在抑制从逻辑芯片到DRAM的信息传输的延迟的情况下，可以提高半导体器件的性能。

69. 发明申请

US20070275554A1 Semiconductor device with interconnection structure for reducing stress migration 有权
标题翻译：具有用于减少应力迁移的互连结构的半导体器件
公开(公告)号：US20070275554A1
公开(公告)日：2007-11-29
申请号：US11703701
申请日：2007-02-08
申请人： Masaya Kawano , Yoshiaki Yamamoto , Takamasa Ito
发明人： Masaya Kawano , Yoshiaki Yamamoto , Takamasa Ito
IPC分类号： H01L21/4763
CPC分类号： H01L23/5226 , H01L21/76804 , H01L21/76808 , H01L21/76877 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device of the present invention includes a first interconnection, a via-plug that is connected to the first interconnection, and a second interconnection that is formed as a single unit with the via-plug. The cross-sectional shape of the via-plug is such that the plug sidewall angle, which indicates the angle of the via-plug sidewall with respect to the surface of the first interconnection, is a positive angle; and moreover, at least two points exist between the base and the top of the via-plug on at least one sidewall of the two sidewalls of the cross-sectional shape of the via-plug at which the plug sidewall angle attains a maximum value. Since shapes that would give rise to the occurrence of concentrations of stress are not formed in the via-plug sidewalls, metal is more effectively embedded in the via-hole, and the incidence of voids is prevented.
摘要翻译：本发明的半导体器件包括第一互连，连接到第一互连的通孔，以及与通孔连接形成为单个单元的第二互连。通孔塞的横截面形状使得指示通孔塞侧壁相对于第一互连件的表面的角度的插塞侧壁角度为正角度; 此外，在插塞侧壁角达到最大值的过孔塞的横截面形状的两个侧壁的至少一个侧壁上，在通孔塞的基部和顶部之间至少存在两个点。由于在通孔塞侧壁中不会形成会产生应力集中的形状，所以金属更有效地嵌入到通路孔中，能够防止空隙的发生。

70. 发明申请

US20060006493A1 Semiconductor chip and method for manufacturing the same and semiconductor device 有权
标题翻译：半导体芯片及其制造方法及半导体器件
公开(公告)号：US20060006493A1
公开(公告)日：2006-01-12
申请号：US11143672
申请日：2005-06-03
申请人： Masaya Kawano , Tsutomu Tashiro , Yoichiro Kurita
发明人： Masaya Kawano , Tsutomu Tashiro , Yoichiro Kurita
IPC分类号： H01L29/00
CPC分类号： H01L23/585 , H01L21/76264 , H01L23/562 , H01L23/564 , H01L2224/32145
摘要： The semiconductor chip 1 has a semiconductor substrate 10. In the present embodiment, the semiconductor substrate 10, which is an SOI substrate, is constituted by comprising a support substrate 12, an insulating layer 14 formed on the support substrate 12 with a layered structure, and a silicon layer 16 formed on the insulating layer 14 with the layered structure. The semiconductor substrate 10 has a circuit forming region A1 provided in the silicon layer 16. An insulating region 18 is provided on the semiconductor substrate 10. The insulating region 18 is provided so as to surround the entire side face of the circuit forming region A1.
摘要翻译：半导体芯片1具有半导体基板10。在本实施例中，作为SOI衬底的半导体衬底10由包括支撑衬底12，形成在具有层状结构的支撑衬底12上的绝缘层14和形成在绝缘层上的硅层16构成 14具有分层结构。半导体衬底10具有设置在硅层16中的电路形成区域A 1。绝缘区域18设置在半导体衬底10上。绝缘区域18设置成包围电路形成区域A 1的整个侧面。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式