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61. 发明申请

US20110309425A1 Air Gap Isolation In Non-Volatile Memory 有权
标题翻译：非易失性存储器中的空气间隙隔离
公开(公告)号：US20110309425A1
公开(公告)日：2011-12-22
申请号：US13162475
申请日：2011-06-16
申请人： Vinod Robert Purayath , George Matamis , Eli Harari , Hiroyuki Kinoshita , Tuan Pham
发明人： Vinod Robert Purayath , George Matamis , Eli Harari , Hiroyuki Kinoshita , Tuan Pham
IPC分类号： H01L29/788 , H01L21/764
CPC分类号： H01L21/764 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation between adjacent active areas of a substrate can be provided, at least in part, by bit line air gaps that are elongated in a column direction between the active areas. At least one cap is formed over each isolation region, at least partially overlying air to provide an upper endpoint for the corresponding air gap. The caps may be formed at least partially along the sidewalls of adjacent charge storage regions. In various embodiments, selective growth processes are used to form capping strips over the isolation regions to define the air gaps. Word line air gaps that are elongated in a row direction between adjacent rows of storage elements are also provided.
摘要翻译：提供了非易失性存储器阵列中的气隙隔离和相关制造工艺。至少部分地可以通过在活动区域之间沿列方向延伸的位线空气间隙来提供衬底的相邻有源区域之间的电隔离。在每个隔离区域上形成至少一个盖，至少部分地覆盖空气以提供相应气隙的上端点。帽可以至少部分地沿着相邻的电荷存储区域的侧壁形成。在各种实施方案中，选择性生长过程用于在隔离区域上形成封盖条以限定气隙。还提供了在相邻行存储元件之间沿行方向延伸的字线气隙。

62. 发明授权

US08013343B2 Silicon carbide single crystal, silicon carbide substrate and manufacturing method for silicon carbide single crystal 有权
标题翻译：碳化硅单晶，碳化硅基板和碳化硅单晶的制造方法
公开(公告)号：US08013343B2
公开(公告)日：2011-09-06
申请号：US11258998
申请日：2005-10-27
申请人： Hiromu Shiomi , Hiroyuki Kinoshita
发明人： Hiromu Shiomi , Hiroyuki Kinoshita
IPC分类号： H01L29/36 , C30B23/02 , C01B31/36
CPC分类号： C30B29/36 , C30B23/00 , Y10S438/931
摘要： SiC single crystal that includes a first dopant functioning as an acceptor, and a second dopant functioning as a donor is provided, where the content of the first dopant is no less than 5×1015 atoms/cm3, the content of the second dopant is no less than 5×1015 atoms/cm3, and the content of the first dopant is greater than the content of the second dopant. A manufacturing method for silicon carbide single crystal is provided with the steps of: fabricating a raw material by mixing a metal boride with a material that includes carbon and silicon; vaporizing the raw material; generating a mixed gas that includes carbon, silicon, boron and nitride; and growing silicon carbide single crystal that includes boron and nitrogen on a surface of a seed crystal substrate by re-crystallizing the mixed gas on the surface of the seed crystal substrate.
摘要翻译：提供了包含作为受体发挥作用的第一掺杂剂的SiC单晶和作为供体的第二掺杂剂，其中第一掺杂剂的含量不小于5×1015原子/ cm3，第二掺杂剂的含量不为小于5×1015原子/ cm3，第一掺杂剂的含量大于第二掺杂剂的含量。提供了一种碳化硅单晶的制造方法，其特征在于：通过将金属硼化物与包含碳和硅的材料混合来制造原料; 蒸发原料; 产生包括碳，硅，硼和氮化物的混合气体; 以及通过使晶种基板的表面上的混合气体再结晶，在晶种基板的表面上生长包含硼和氮的碳化硅单晶。

63. 发明授权

US07842618B2 System and method for improving mesa width in a semiconductor device 有权
标题翻译：用于改善半导体器件中的台面宽度的系统和方法
公开(公告)号：US07842618B2
公开(公告)日：2010-11-30
申请号：US11193409
申请日：2005-08-01
申请人： Unsoon Kim , Angela T. Hui , Yider Wu , Kuo-Tung Chang , Hiroyuki Kinoshita
发明人： Unsoon Kim , Angela T. Hui , Yider Wu , Kuo-Tung Chang , Hiroyuki Kinoshita
IPC分类号： H01L21/302 , B44C1/22
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11521 , H01L27/11531
摘要： A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench.
摘要翻译：提供了一种用于形成存储器件的方法。在衬底上形成氮化物层。蚀刻氮化物层和衬底以形成沟槽。在沟槽的相对侧上修整氮化物层，以加宽氮化物层内的沟槽。沟槽填充有氧化物材料。从存储器件剥离氮化物层，在沟槽上方形成台面。

64. 发明授权

US07834917B2 Imaging apparatus, noise reduction apparatus, noise reduction method, and noise reduction program 失效
标题翻译：成像装置，降噪装置，降噪方法和降噪程序
公开(公告)号：US07834917B2
公开(公告)日：2010-11-16
申请号：US11665037
申请日：2006-08-09
申请人： Hiroyuki Kinoshita , Jing Zhang , Masahiro Ito , Akira Matsui
发明人： Hiroyuki Kinoshita , Jing Zhang , Masahiro Ito , Akira Matsui
IPC分类号： H04N5/217
CPC分类号： H04N5/21 , G06T3/4023 , G06T5/002 , G06T5/005 , G06T5/20 , G06T7/13 , G06T2207/10024 , G06T2207/20012 , G06T2207/20032 , G06T2207/20192 , H04N5/213
摘要： Noise reduction is performed on the basis of characteristics of an image in a detection range. A noise reduction block 4′ performs a second-order differentiation process and a symmetry process to decide adjacent pixels with which noise reduction is preformed for an attention pixel. With the pixel level of the attention pixel in the detection range and the pixel levels of adjacent pixels used for noise reduction, an arithmetic mean processing section 16 calculates a mean value. A median filter 17 selects a median value. With the number of pixels used for noise reduction, it is determined whether the image in the detection range contains a flat portion, a ramp portion, or an edge. The mean value and the median value are weight-added with a weighted coefficient that are changed on the basis of characteristics of the image. The result is substituted for the level of the attention pixel. When the attention pixel is an isolated point, an all-pixel median filter section 31 selects a medium value of the levels of all the pixels in the detection range including the attention pixel and substitutes the median value for the level of the attention pixel.
摘要翻译：基于检测范围内的图像的特性进行降噪。降噪块4'执行二阶微分处理和对称处理，以确定针对注意像素执行降噪的相邻像素。利用检测范围内的关注像素的像素级和用于降噪的相邻像素的像素级，算术平均处理部16计算平均值。中值滤波器17选择中值。利用用于降噪的像素数量，确定检测范围内的图像是否包含平坦部分，斜坡部分或边缘。平均值和中值是加权系数，加权系数根据图像的特性而改变。结果代替注意像素的级别。当注意像素是孤立点时，全像素中值滤波器部分31选择包括关注像素在内的检测范围内的所有像素的电平的中值，并代入关注像素的电平的中值。

65. 发明授权

US07679129B1 System and method for improving oxide-nitride-oxide (ONO) coupling in a semiconductor device 有权
标题翻译：用于改善半导体器件中的氧化物 - 氧化物 - 氧化物（ONO）耦合的系统和方法
公开(公告)号：US07679129B1
公开(公告)日：2010-03-16
申请号：US11128389
申请日：2005-05-13
申请人： Angela T. Hui , Unsoon Kim , Hiroyuki Kinoshita , Kuo-Tung Chang
发明人： Angela T. Hui , Unsoon Kim , Hiroyuki Kinoshita , Kuo-Tung Chang
IPC分类号： H01L29/94
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/66825
摘要： A memory device includes a substrate and a first dielectric layer formed over the substrate. At least two charge storage elements are formed over the first dielectric layer. The substrate and the first dielectric layer include a shallow trench filled with an oxide material. The oxide material formed in a center portion of the shallow trench is removed to provide a region with a substantially rectangular cross-section.
摘要翻译：存储器件包括衬底和形成在衬底上的第一电介质层。在第一电介质层上形成至少两个电荷存储元件。衬底和第一介电层包括填充有氧化物材料的浅沟槽。形成在浅沟槽的中心部分的氧化物材料被去除以提供具有基本上矩形横截面的区域。

66. 发明授权

US07666739B2 Methods for fabricating a split charge storage node semiconductor memory 有权
标题翻译：分离电荷存储节点半导体存储器的制造方法
公开(公告)号：US07666739B2
公开(公告)日：2010-02-23
申请号：US11614048
申请日：2006-12-20
申请人： Chungho Lee , Ashot Melik-Martirosian , Hiroyuki Kinoshita , Kuo-Tung Chang , Sugimo Rinji , Wei Zheng
发明人： Chungho Lee , Ashot Melik-Martirosian , Hiroyuki Kinoshita , Kuo-Tung Chang , Sugimo Rinji , Wei Zheng
IPC分类号： H01L21/336
CPC分类号： H01L21/28282 , H01L29/792
摘要： Methods are provided for fabricating a split charge storage node semiconductor memory device. In accordance with one embodiment the method comprises the steps of forming a gate insulator layer having a first physical thickness and a first effective oxide thickness on a semiconductor substrate and forming a control gate electrode having a first edge and a second edge overlying the gate insulator layer. The gate insulator layer is etched to form first and second undercut regions at the edges of the control gate electrode, the first and second undercut region each exposing a portion of the semiconductor substrate and an underside portion of the control gate electrode. First and second charge storage nodes are formed in the undercut regions, each of the charge storage nodes comprising an oxide-storage material-oxide structure having a physical thickness substantially equal to the first physical thickness and an effective oxide thickness less than the first effective oxide thickness.
摘要翻译：提供了用于制造分离电荷存储节点半导体存储器件的方法。根据一个实施例，该方法包括以下步骤：在半导体衬底上形成具有第一物理厚度和第一有效氧化物厚度的栅极绝缘体层，并形成具有覆盖栅极绝缘体层的第一边缘和第二边缘的控制栅极电极。栅极绝缘体层被蚀刻以在控制栅电极的边缘处形成第一和第二底切区域，第一和第二底切区域各自暴露半导体衬底的一部分和控制栅电极的下侧部分。第一和第二电荷存储节点形成在底切区域中，每个电荷存储节点包括具有基本上等于第一物理厚度的物理厚度和小于第一有效氧化物的有效氧化物厚度的氧化物存储材料 - 氧化物结构厚度。

67. 发明申请

US20090108330A1 SPLIT CHARGE STORAGE NODE OUTER SPACER PROCESS 有权
标题翻译：分离式充电储存节点外部间隔过程
公开(公告)号：US20090108330A1
公开(公告)日：2009-04-30
申请号：US11924169
申请日：2007-10-25
申请人： Minghao Shen , Chungho Lee , Hiroyuki Kinoshita , Huaqiang Wu
发明人： Minghao Shen , Chungho Lee , Hiroyuki Kinoshita , Huaqiang Wu
IPC分类号： H01L29/792 , H01L21/3205
CPC分类号： H01L29/7923 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L27/115 , H01L27/11568
摘要： Memory cells containing two split sub-lithographic charge storage nodes on a semiconductor substrate and methods for making the memory cells are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing an exposed portion of a fist poly layer between sloping side surfaces or outer surfaces of spacers while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing an exposed portion of a charge storage layer between sloping side surfaces or outer surfaces of spacers, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.
摘要翻译：提供了包含半导体衬底上的两个分裂子光刻电荷存储节点的存储单元以及用于制造存储单元的方法。这些方法可以包括通过使用间隔物形成技术形成两个分裂的亚光刻电荷存储节点。通过在间隔物的倾斜侧表面或外表面之间除去第一多晶硅层的暴露部分，同时留下被间隔物保护的第一多晶硅层的部分，该方法可以提供两个分裂的次光刻的第一多晶硅栅极。此外，通过去除间隔物的倾斜侧表面或外表面之间的电荷存储层的暴露部分，该方法可以提供电荷存储层的两个分开的窄部分，其随后形成两个分裂的亚光刻电荷存储节点。

68. 发明申请

US20090061631A1 GATE REPLACEMENT WITH TOP OXIDE REGROWTH FOR THE TOP OXIDE IMPROVEMENT 有权
标题翻译：顶部氧化物改进的顶部氧化物替换
公开(公告)号：US20090061631A1
公开(公告)日：2009-03-05
申请号：US11848515
申请日：2007-08-31
申请人： Chungho Lee , Hiroyuki Kinoshita , Kuo-Tung Chang , Rinji Sugino , Chi Chang , Huaqiang Wu
发明人： Chungho Lee , Hiroyuki Kinoshita , Kuo-Tung Chang , Rinji Sugino , Chi Chang , Huaqiang Wu
IPC分类号： H01L21/311
CPC分类号： H01L29/7923 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42348 , H01L29/7887
摘要： Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are provided. The method can involve removing a first poly over a first top oxide from the memory cell; removing the first top oxide from the memory cell; and forming a second top oxide around the charge storage element. The second top oxide can be formed by oxidizing a portion of the charge storage element or by forming a sacrificial layer over the charge storage element and oxidizing the sacrificial layer to a second top oxide.
摘要翻译：提供了替换/重整存储单元的电荷存储元件周围的顶部氧化物的方法和提高存储单元的电荷存储元件周围的顶部氧化物的质量的方法。该方法可以包括从存储器单元去除第一顶部氧化物上的第一多晶硅; 从存储器单元中去除第一顶部氧化物; 以及在所述电荷存储元件周围形成第二顶部氧化物。可以通过氧化电荷存储元件的一部分或通过在电荷存储元件上形成牺牲层并将牺牲层氧化成第二顶部氧化物来形成第二顶部氧化物。

69. 发明授权

US07432156B1 Memory device and methods for its fabrication 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US07432156B1
公开(公告)日：2008-10-07
申请号：US11409361
申请日：2006-04-20
申请人： Chungho Lee , Ashot Melik-Martirosian , Hiroyuki Kinoshita , Kuo-Tung Chang , Amol Joshi , Meng Ding
发明人： Chungho Lee , Ashot Melik-Martirosian , Hiroyuki Kinoshita , Kuo-Tung Chang , Amol Joshi , Meng Ding
IPC分类号： H01L21/8247
CPC分类号： H01L21/28282 , H01L29/42332 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an edge of the gate electrode and the undercut opening is filled with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride. A region of the semiconductor substrate is impurity doped to form a bit line aligned with the gate electrode, and a conductive layer is deposited and patterned to form a word line coupled to the gate electrode.
摘要翻译：提供半导体存储器件及其制造方法。根据本发明的一个实施例，该方法包括以下步骤：形成栅极绝缘体和覆盖半导体衬底的栅电极。蚀刻栅极绝缘体以在栅电极的边缘下方形成底切开口，并且底切开口填充有包括夹在氧化物层和氮化物层之间的电荷捕获层的分层结构。掺杂半导体衬底的区域以形成与栅电极对准的位线，并且沉积并图案化导电层以形成耦合到栅电极的字线。

70. 发明申请

US20080153236A1 FLASH MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME 审中-公开
标题翻译：闪存存储器件及其制造方法
公开(公告)号：US20080153236A1
公开(公告)日：2008-06-26
申请号：US11615425
申请日：2006-12-22
申请人： Ning Cheng , Kuo-Tung Chang , Hiroyuki Kinoshita , Minh-Van Ngo , Fred Cheung , Alexander Nickel
发明人： Ning Cheng , Kuo-Tung Chang , Hiroyuki Kinoshita , Minh-Van Ngo , Fred Cheung , Alexander Nickel
IPC分类号： H01L21/336
CPC分类号： H01L29/66833 , H01L27/115 , H01L27/11568
摘要： Flash memory devices and methods for fabricating the same are provided. A method for fabricating a memory device comprises the steps of fabricating a first gate stack and a second gate stack overlying a P-type silicon substrate and implanting an impurity dopant into the substrate substantially between the first gate stack and the second gate stack to form an impurity-doped region of the substrate. A channel region underlies the first gate stack adjacent to the impurity-doped region. An intrinsically tensile-stressed insulating member is formed between the first and the second gate stacks and overlying the impurity-doped region. The tensile-stressed insulating member causes a uniaxial lateral tensile stress to be transmitted to the first channel region. A word line is formed overlying the intrinsically tensile-stressed insulating member and in electrical contact with the first gate stack and the second gate stack.
摘要翻译：提供闪存器件及其制造方法。一种用于制造存储器件的方法包括以下步骤：制造覆盖P型硅衬底的第一栅极堆叠和第二栅极堆叠，并且基本上在第一栅极堆叠和第二栅极堆叠之间将杂质掺杂剂注入到衬底中，以形成衬底的杂质掺杂区域。位于与杂质掺杂区相邻的第一栅叠层下方的沟道区。在第一和第二栅极堆叠之间并且覆盖杂质掺杂区域上形成本征拉伸应力的绝缘构件。拉伸应力绝缘构件使单向横向拉伸应力传递到第一沟道区域。在本征拉伸应力绝缘构件上形成字线并且与第一栅极堆叠和第二栅极堆叠电接触。

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