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61. 发明授权

US5994193A Method of making high performance MOSFET with integrated poly/metal gate electrode 失效
标题翻译：制造具有集成多晶/金属栅电极的高性能MOSFET的方法
公开(公告)号：US5994193A
公开(公告)日：1999-11-30
申请号：US95088
申请日：1998-06-10
申请人： Mark I. Gardner , Derick J. Wristers , Jon D. Cheek
发明人： Mark I. Gardner , Derick J. Wristers , Jon D. Cheek
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L29/66575 , H01L21/28061 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： An integrated circuit transistor and method of making the same are provided. The transistor includes a substrate, first and second source/drain regions, and a gate electrode stack coupled to the substrate. The gate electrode stack is fabricated by forming a first insulating layer on the substrate, forming a first conductor layer on the first insulating layer, and forming a metal layer on the first conductor layer. A second insulating layer, such as an interlevel dielectric layer, is coupled to the substrate adjacent to the gate electrode stack. Sidewall spacers and LDD processing may be incorporated. The transistor and method integrate metal and polysilicon into a self-aligned gate electrode stack.
摘要翻译：提供集成电路晶体管及其制造方法。晶体管包括衬底，第一和第二源极/漏极区域以及耦合到衬底的栅电极堆叠。通过在基板上形成第一绝缘层，在第一绝缘层上形成第一导体层，在第一导体层上形成金属层，制作栅电极堆叠。诸如层间电介质层的第二绝缘层耦合到与栅电极堆叠相邻的衬底。可以并入侧壁间隔物和LDD处理。晶体管和方法将金属和多晶硅集成到自对准栅极电极堆叠中。

62. 发明授权

US5962894A Trench transistor with metal spacers 失效
标题翻译：沟槽晶体管与金属间隔
公开(公告)号：US5962894A
公开(公告)日：1999-10-05
申请号：US30052
申请日：1998-02-24
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/336 , H01L29/417 , H01L29/423 , H01L29/76 , H01L31/062
CPC分类号： H01L29/41775 , H01L29/66621 , H01L29/78
摘要： An IGFET with a gate electrode and metal spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, metal spacers adjacent to the sidewalls and the bottom surface, a gate insulator on the bottom surface between the metal spacers, protective insulators on the metal spacers, a gate electrode on the gate insulator and protective insulators, and a source and drain adjacent to the bottom surface. A method of forming the IGFET includes implanting a doped layer into the substrate, etching completely through the doped layer and partially through the substrate to form the trench and split the doped layer into source and drain regions, applying a high-temperature anneal to diffuse the source and drain regions beneath the bottom surface, depositing a blanket layer of conductive metal over the substrate and applying an anisotropic etch to form the metal spacers, depositing a continuous insulative layer over the substrate to provide the gate insulator and the protective insulators, depositing a blanket layer of gate electrode material over the substrate, and polishing the gate electrode material so that the gate electrode is substantially aligned with a top surface of the substrate. Advantageously, the channel length is significantly smaller than the trench length, and the metal spacers reduce the parasitic resistance of lightly doped source and drain regions.
摘要翻译：公开了具有沟槽中的栅电极和金属间隔物的IGFET。 IGFET包括具有相对的侧壁和半导体衬底中的底表面的沟槽，与侧壁和底表面相邻的金属间隔物，位于金属间隔物之间的底表面上的栅极绝缘体，金属间隔物上的保护绝缘体，栅电极在栅极绝缘体和保护绝缘体上，以及与底表面相邻的源极和漏极。形成IGFET的方法包括将掺杂层注入到衬底中，完全通过掺杂层蚀刻并部分地穿过衬底以形成沟槽并将掺杂层分裂成源极和漏极区域，施加高温退火以扩散在底表面下方的源极和漏极区域，在衬底上沉积导电金属的覆盖层，并施加各向异性蚀刻以形成金属间隔物，在衬底上沉积连续的绝缘层以提供栅极绝缘体和保护绝缘体，覆盖衬底上的栅电极材料层，并且对栅电极材料进行抛光，使得栅电极基本上与衬底的顶表面对准。有利地，沟道长度显着小于沟槽长度，并且金属间隔物减少了轻掺杂源极和漏极区域的寄生电阻。

63. 发明授权

US5930634A Method of making an IGFET with a multilevel gate 失效
标题翻译：制造具有多级门的IGFET的方法
公开(公告)号：US5930634A
公开(公告)日：1999-07-27
申请号：US844927
申请日：1997-04-21
申请人： Frederick N. Hause , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Frederick N. Hause , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66575 , H01L21/28035 , H01L21/28052 , H01L29/42376 , H01L29/4925 , H01L29/6659 , H01L29/7833
摘要： A method of making an IGFET with a multilevel gate that includes upper and lower gate levels is disclosed. The method includes providing a semiconductor substrate with an active region, forming a gate insulator on the active region, forming a first gate material with a thickness of at most 1000 angstroms on the gate inslator and over the active region, forming a first photoresist layer over the first gate material, irradiating the first photoresist layer with a first image pattern and removing irradiated portions of the first photoresist layer to provide openings above the active region, etching the first gate material through the openings in the first photoresist layer using the first photoresist layer as an etch mask for a portion of the first gate material that forms a lower gate level, removing the first photoresist layer, forming an upper gate level on the lower gate level after removing the first photoresist layer, and forming a source and drain in the active region. Advantageously, the first photoresist layer can be ultra-thin to enhance the accuracy in which the image pattern is replicated, thereby reducing variations in channel length and device performance.
摘要翻译：公开了一种制造具有包括上下栅极电平的多电平栅极的IGFET的方法。该方法包括提供具有有源区的半导体衬底，在有源区上形成栅极绝缘体，在栅极绝缘体上并在有源区上形成厚度至多为1000埃的第一栅极材料，形成第一光致抗蚀剂层第一栅极材料，用第一图案图案照射第一光致抗蚀剂层，并去除第一光致抗蚀剂层的照射部分以在有源区上方提供开口，使用第一光致抗蚀剂层蚀刻通过第一光致抗蚀剂层中的开口的第一栅极材料作为用于形成下栅极电平的第一栅极材料的一部分的蚀刻掩模，去除第一光致抗蚀剂层，在去除第一光致抗蚀剂层之后在下栅极电平上形成上栅极电平，并在其中形成源极和漏极活跃区域。有利地，第一光致抗蚀剂层可以是超薄的，以提高复制图像图案的精度，从而减少通道长度和器件性能的变化。

64. 发明授权

US5891787A Semiconductor fabrication employing implantation of excess atoms at the edges of a trench isolation structure 失效
标题翻译：半导体制造采用在沟槽隔离结构的边缘处植入多余的原子
公开(公告)号：US5891787A
公开(公告)日：1999-04-06
申请号：US923181
申请日：1997-09-04
申请人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76237
摘要： A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the masking layer. A pair of dielectric spacers are formed upon the sidewalls of the masking layer within the opening. A trench is then etched in the semiconductor substrate between the dielectric spacers. A first dielectric layer is then thermally grown on the walls and base of the trench. A CVD oxide is deposited into the trench and processed such that the upper surface of the CVD oxide is commensurate with the substrate surface. Portions of the spacers are also removed such that the thickness of the spacers is between about 0 to 200 .ANG.. Silicon atoms and/or barrier atoms, such as nitrogen atoms, are then implanted into regions of the active areas in close proximity to the trench isolation structure.
摘要翻译：一种用于将第一有源区与第二有源区隔离的方法，二者均配置在半导体衬底内。该方法包括在半导体衬底上形成电介质掩模层。然后通过掩模层形成开口。在开口内的掩模层的侧壁上形成一对电介质隔离物。然后在电介质间隔物之间的半导体衬底中蚀刻沟槽。然后在沟槽的壁和基底上热生长第一介电层。将CVD氧化物沉积到沟槽中并进行处理，使得CVD氧化物的上表面与衬底表面相当。间隔物的部分也被去除，使得间隔物的厚度在约0至200安培之间。然后将硅原子和/或势垒原子（例如氮原子）注入紧邻沟槽隔离结构的有源区的区域中。

65. 发明授权

US5877058A Method of forming an insulated-gate field-effect transistor with metal spacers 失效
标题翻译：用金属间隔物形成绝缘栅场效应晶体管的方法
公开(公告)号：US5877058A
公开(公告)日：1999-03-02
申请号：US703272
申请日：1996-08-26
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L29/6659 , H01L29/6656
摘要： An IGFET with metal spacers is disclosed. The IGFET includes a gate electrode on a gate insulator on a semiconductor substrate. Sidewall insulators are adjacent to opposing vertical edges of the gate electrode, and metal spacers are formed on the substrate and adjacent to the sidewall insulators. The metal spacers are electrically isolated from the gate electrode but contact portions of the drain and the source. Preferably, the metal spacers are adjacent to edges of the gate insulator beneath the sidewall insulators. The metal spacers are formed by depositing a metal layer over the substrate then applying an anisotropic etch. In one embodiment, the metal spacers contact lightly and heavily doped drain and source regions, thereby increasing the conductivity between the heavily doped drain and source regions and the channel underlying the gate electrode. The metal spacers can also provide low resistance drain and source contacts.
摘要翻译：公开了具有金属间隔物的IGFET。 IGFET在半导体衬底上的栅极绝缘体上包括栅电极。侧壁绝缘体与栅电极的相对的垂直边缘相邻，并且金属间隔件形成在衬底上并且与侧壁绝缘体相邻。金属间隔物与栅电极电绝缘，但是漏极和源极的接触部分。优选地，金属间隔件邻近侧壁绝缘体之下的栅极绝缘体的边缘。通过在衬底上沉积金属层然后施加各向异性蚀刻来形成金属间隔物。在一个实施例中，金属间隔物接触轻掺杂和重掺杂的漏极和源极区域，从而增加重掺杂漏极和源极区域之间的导电性以及栅电极下面的沟道。金属间隔物还可以提供低电阻漏极和源极触点。

66. 发明授权

US5847428A Integrated circuit gate conductor which uses layered spacers to produce a graded junction 失效
标题翻译：集成电路栅极导体，其使用分层间隔物来产生分级结
公开(公告)号：US5847428A
公开(公告)日：1998-12-08
申请号：US761132
申请日：1996-12-06
申请人： H. Jim Fulford, Jr. , Mark I. Gardner , Derick J. Wristers
发明人： H. Jim Fulford, Jr. , Mark I. Gardner , Derick J. Wristers
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/6659 , H01L29/665 , H01L29/6656 , H01L29/7833 , Y10S257/90
摘要： A transistor is provided with a graded source/drain junction. At least two dielectric spacers are formed in sequence upon the gate conductor. Adjacent dielectric spacers have dissimilar etch characteristics. An ion implant follows the formation of at least two of the dielectric spacers to introduce dopants into the source/drain region of the transistor. The ion implants are placed in different positions a spaced distance from the gate conductor according to a thickness of the dielectric spacers. As the implants are introduced further from the channel, the implant dosage and energy is increased. In a second embodiment, the ion implants are performed in reverse order. The dielectric spacers pre-exist on the sidewall surfaces of the gate conductor. The spacers are sequentially removed followed by an ion implant. An etchant is used which attacks the spacer to be removed but not the spacer beneath to the one being removed. Each time, the implants are performed with a lower energy and with a lower dosage so as to grade the junction with lighter concentrations and energies as the implant areas approach the channel. Reversing the implantation process enables high-temperature thermal anneals required for high-concentration low-diffusivity dopants to be performed first. The LDD implant comprises dopants of lower concentration and higher diffusivity requiring lower temperature anneals. Performing lower temperature anneals later in the sequence affords a lessened opportunity for undesirable short-channel effects.
摘要翻译：晶体管具有渐变源极/漏极结。在栅极导体上依次形成至少两个电介质间隔物。相邻的电介质间隔物具有不同的蚀刻特性。离子注入沿着至少两个电介质间隔物的形成，以将掺杂剂引入到晶体管的源极/漏极区域中。离子植入物根据电介质间隔物的厚度被放置在与栅极导体间隔距离的不同位置。随着植入物从通道进一步引入，植入物剂量和能量增加。在第二实施例中，以相反的顺序执行离子注入。电介质垫片预先存在于栅极导体的侧壁表面上。依次移除间隔物，然后离子注入。使用蚀刻剂来攻击待移除的间隔物，而不是将垫片下移到被去除的间隔物。每次，植入物以较低的能量和较低的剂量进行，以便随着植入区域接近通道而将结点分级为较轻的浓度和能量。倒置注入工艺可以实现高浓度低扩散性掺杂剂首先要求的高温热退火。 LDD植入物包含较低浓度和较高扩散系数的掺杂剂，需要较低的温度退火。在该顺序的稍后进行较低的温度退火可以减少不期望的短通道效应的机会。

67. 发明授权

US5844276A CMOS integrated circuit and method for implanting NMOS transistor areas prior to implanting PMOS transistor areas to optimize the thermal diffusivity thereof 失效
标题翻译： CMOS集成电路和用于在注入PMOS晶体管区域之前注入NMOS晶体管区域以优化其热扩散率的方法
公开(公告)号：US5844276A
公开(公告)日：1998-12-01
申请号：US760462
申请日：1996-12-06
申请人： H. Jim Fulford, Jr. , Mark I. Gardner , Derick J. Wristers
发明人： H. Jim Fulford, Jr. , Mark I. Gardner , Derick J. Wristers
IPC分类号： H01L21/8238 , H01L27/092 , H01L27/088
CPC分类号： H01L27/092 , H01L21/823814 , Y10S257/90
摘要： A transistor and a transistor fabrication method for forming an LDD structure in which the n-type dopants associated with an n-channel transistor are formed prior to the formation of the p-type dopants is presented. The n-type source/drain and LDD implants generally require higher activation energy (thermal anneal) than the p-type source/drain and LDD implants. The n-type arsenic source/drain implant, which has the lowest diffusivity and requires the highest temperature anneal, is performed first in the LDD process formation. Performing such a high temperature anneal first ensures minimum additional migration of subsequent, more mobile implants. Mobile implants associated with lighter and less dense implant species are prevalent in LDD areas near the channel perimeter. The likelihood of those implants moving into the channel is lessened by tailoring subsequent anneal steps to temperatures less than the source/drain anneal step.
摘要翻译：提出一种用于形成LDD结构的晶体管和晶体管制造方法，其中在形成p型掺杂剂之前形成与n沟道晶体管相关联的n型掺杂剂。 n型源极/漏极和LDD植入物通常需要比p型源极/漏极和LDD植入物更高的活化能（热退火）。首先在LDD工艺形成中执行具有最低扩散率并且需要最高温度退火的n型砷源/漏极注入。首先进行这样的高温退火可确保随后的更多移动式植入物的最小额外迁移。与更轻和较不密集的种植体物种相关的移植植入物在通道周边附近的LDD区域是普遍的。通过将后续退火步骤调整到低于源极/漏极退火步骤的温度，使得这些植入物进入通道的可能性降低。

68. 发明授权

US5770485A MOSFET device with an amorphized source and fabrication method thereof 失效
标题翻译：制造具有非晶化源的mosfet器件的方法
公开(公告)号：US5770485A
公开(公告)日：1998-06-23
申请号：US811417
申请日：1997-03-04
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Derick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Derick J. Wristers
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L21/8234 , H01L29/08 , H01L29/78 , H01L21/00 , H01L21/425
CPC分类号： H01L29/66659 , H01L21/26506 , H01L21/28123 , H01L21/823418 , H01L29/0847 , H01L29/7835
摘要： An amorphized implant is performed to retard diffusion of ions in the source and drain regions. By retarding the diffusion of ions in these regions, a shallower junction is advantageously created in the silicon regions of the wafer. A slight degradation in leakage current is obtained if the amorphized implant is performed on both the source and the drain sides of a transistor. However, since the source region is a low voltage region with a very shallow junction, MOSFETs in both n-channel and p-channel regions are formed with improved performance and reliability. A method of fabricating an integrated circuit includes forming a gate electrode over a semiconductor substrate, forming a source mask extending over the drain region of the semiconductor substrate, and implanting an implant species into the source region of the semiconductor substrate to form an amorphous implant layer of the semiconductor substrate. The semiconductor substrate has a source region adjacent to a first side of the gate electrode and has a drain region adjacent to a second side of the gate electrode. The amorphous implant layer is self-aligned with the source mask and extends through the exposed region of the semiconductor substrate and the source region of the semiconductor substrate. The method further includes the step of implanting a source implant into the exposed region of the semiconductor substrate and the source region of the semiconductor substrate to form a source implant layer of the semiconductor substrate. The source implant layer extends a shallower depth into the semiconductor substrate than the amorphous implant layer.
摘要翻译：执行非晶化的植入物以阻止源极和漏极区域中的离子的扩散。通过延迟这些区域中的离子的扩散，有利地在晶片的硅区域中产生较浅的结。如果在晶体管的源极和漏极两侧进行非晶化注入，则可以获得漏电流的轻微降低。然而，由于源极区域是具有非常浅的结的低电压区域，所以在n沟道区域和p沟道区域中形成具有改进的性能和可靠性的MOSFET。一种制造集成电路的方法包括在半导体衬底上形成栅电极，形成在半导体衬底的漏极区域上延伸的源极掩模，以及将注入物质注入到半导体衬底的源极区域中以形成无定形注入层的半导体衬底。半导体衬底具有与栅电极的第一侧相邻的源极区，并且具有与栅电极的第二侧相邻的漏极区。非晶注入层与源极掩模自对准并延伸穿过半导体衬底的暴露区域和半导体衬底的源极区域。该方法还包括将源植入物植入半导体衬底的暴露区域和半导体衬底的源极区域以形成半导体衬底的源极注入层的步骤。源极注入层比无定形植入层将比较深的深度延伸到半导体衬底中。

69. 发明授权

US5710054A Method of forming a shallow junction by diffusion from a silicon-based spacer 失效
标题翻译：通过从硅基间隔物扩散形成浅结的方法
公开(公告)号：US5710054A
公开(公告)日：1998-01-20
申请号：US703273
申请日：1996-08-26
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/225 , H01L21/28 , H01L21/336 , H01L29/08 , H01L29/78 , H01L21/265 , H01L21/385
CPC分类号： H01L29/66575 , H01L21/2256 , H01L21/2257 , H01L21/28105 , H01L21/28114 , H01L29/0847 , H01L29/41783 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7834
摘要： A method of forming a shallow junction in an IGFET is disclosed. The method includes forming a gate insulator on a semiconductor substrate of first conductivity type, forming a gate electrode on the gate insulator, forming a sidewall insulator on an edge of the gate electrode, forming a silicon-based spacer over the substrate such that the sidewall insulator separates and electrically isolates the spacer and the gate electrode, and diffusing a dopant of second conductivity type from the spacer into the substrate. The diffused dopant forms a shallow region of second conductivity type in the substrate, and a shallow junction is substantially laterally aligned with the edge of the gate electrode.
摘要翻译：公开了一种在IGFET中形成浅结的方法。该方法包括在第一导电类型的半导体衬底上形成栅极绝缘体，在栅极绝缘体上形成栅电极，在栅电极的边缘上形成侧壁绝缘体，在衬底上形成硅基间隔物，使得侧壁绝缘体分离并电隔离间隔物和栅电极，并将第二导电类型的掺杂剂从间隔物扩散到衬底中。扩散掺杂剂在衬底中形成第二导电类型的浅区域，并且浅结与栅电极的边缘基本上横向对齐。

70. 发明授权

US06661057B1 Tri-level segmented control transistor and fabrication method 失效
标题翻译：三电平分段控制晶体管及其制造方法
公开(公告)号：US06661057B1
公开(公告)日：2003-12-09
申请号：US09056836
申请日：1998-04-07
申请人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L27088
CPC分类号： H01L21/76843 , H01L21/28518 , H01L21/32053 , H01L21/76802 , H01L21/76855 , H01L29/66484 , H01L29/6656 , H01L29/6659 , H01L29/7831 , H01L29/7833 , Y10S257/90
摘要： A transistor is formed in an active area having a segmented gate structure. The segmented gate structure advantageously provides for dynamic control of a channel region formed within the transistor. Lightly doped source and drain (LDD) regions are formed aligned to a gate electrode. After forming an insulating layer adjacent the exposed surfaces of the gate electrode, conductive spacers are formed disposed overlying the LDD regions. These spacers are electrically isolated from the gate electrode by the insulating layer. Heavily doped source and drain (S/D) regions are formed which are aligned to the spacers and make electrical contact, for example through a salicide process, supplied to the conductive spacer, the gate electrode, and the S/D regions. The described structure advantageously supplies dynamic control of the channel region through dynamic, independent control of the LDD portions of the S/D regions.
摘要翻译：晶体管形成在具有分段栅极结构的有源区中。分段栅结构有利地提供了在晶体管内形成的沟道区的动态控制。轻掺杂的源极和漏极（LDD）区域形成为与栅电极对准。在与栅电极的暴露表面相邻形成绝缘层之后，形成布置在LDD区域上方的导电间隔物。这些间隔物通过绝缘层与栅电极电隔离。形成重掺杂的源极和漏极（S / D）区域，其与间隔物对准，并且例如通过提供给导电间隔物，栅电极和S / D区域的自对准硅化物工艺进行电接触。所描述的结构有利地通过对S / D区域的LDD部分的动态独立控制来提供通道区域的动态控制。

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