专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明申请

US20080169513A1 Emitter Ballasting by Contact Area Segmentation in ESD Bipolar Based Semiconductor Component 有权
标题翻译：通过ESD双极性半导体元件中的接触区域分割发射器镇流器
公开(公告)号：US20080169513A1
公开(公告)日：2008-07-17
申请号：US11863971
申请日：2007-09-28
申请人： Marie Denison
发明人： Marie Denison
IPC分类号： H01L27/102 , H01L21/8249
CPC分类号： H01L27/0259 , H01L24/05 , H01L27/0641 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/00
摘要： Integrated circuits (ICs) utilize bipolar transistors in electro-static discharge (ESD) protection circuits to shunt discharge currents during ESD events to protect the components in the ICs. Bipolar transistors are subject to non-uniform current crowding across the emitter-base junction during ESD events, which results in less protection for the IC components and degradation of the bipolar transistor. This invention comprises multiple contact islands (126) on the emitter (116) of a bipolar transistor, which act to spread current uniformly across the emitter-base junction. Also included in this invention is segmentation of the emitter diffused region to further improve current uniformity and biasing of the transistor. This invention can be combined with drift region ballasting or back-end ballasting to optimize an ESD protection circuit.
摘要翻译：集成电路（IC）利用静电放电（ESD）保护电路中的双极晶体管在ESD事件期间分流放电电流，以保护IC中的组件。在ESD事件期间，双极晶体管在发射极 - 基极结上受到不均匀的电流拥挤，这导致对IC器件的更少的保护和双极晶体管的劣化。本发明包括在双极晶体管的发射极（116）上的多个接触岛（126），其用于均匀地扩散电流穿过发射极 - 基极结。本发明还包括发射极扩散区域的分割，以进一步提高晶体管的电流均匀性和偏置。本发明可以与漂移区镇流或后端镇流相组合，以优化ESD保护电路。

62. 发明授权

US08890579B2 Circuit for current sensing in high-voltage transistor 有权
标题翻译：高压晶体管电流检测电路
公开(公告)号：US08890579B2
公开(公告)日：2014-11-18
申请号：US13554846
申请日：2012-07-20
申请人： Joseph M. Khayat , Marie Denison
发明人： Joseph M. Khayat , Marie Denison
IPC分类号： H03K3/00
CPC分类号： H03K17/08 , H03K2217/0027
摘要： An integrated circuit including a high-voltage n-channel MOS power transistor, a high-voltage n-channel MOS blocking transistor, a high-voltage n-channel MOS reference transistor, and a voltage comparator, configured to provide an overcurrent signal if drain current through the power transistor in the on state exceeds a predetermined value. The power transistor source node is grounded. The blocking transistor drain node is connected to the power transistor drain node. The blocking transistor source node is coupled to the comparator non-inverting input. The reference transistor drain node is fed by a current source and is connected to the comparator inverting input. The reference transistor gate node is coupled to a gate node of the power transistor. The comparator output provides the overcurrent signal. A process of operating the integrated circuit is disclosed.
摘要翻译：包括高电压n沟道MOS功率晶体管，高压n沟道MOS截止晶体管，高压n沟道MOS参考晶体管和电压比较器的集成电路，被配置为在漏极通过处于导通状态的功率晶体管的电流超过预定值。功率晶体管源节点接地。阻塞晶体管漏极节点连接到功率晶体管漏极节点。阻塞晶体管源节点耦合到比较器同相输入。参考晶体管漏极节点由电流源馈送并连接到比较器反相输入。参考晶体管栅极节点耦合到功率晶体管的栅极节点。比较器输出提供过电流信号。公开了一种操作该集成电路的过程。

63. 发明申请

US20140197486A1 POWER INTEGRATED CIRCUIT INCLUDING SERIES-CONNECTED SOURCE SUBSTRATE AND DRAIN SUBSTRATE POWER MOSFETS 有权
标题翻译：功率集成电路，包括串联源极基极和漏极基极功率MOSFET
公开(公告)号：US20140197486A1
公开(公告)日：2014-07-17
申请号：US13563923
申请日：2012-08-01
申请人： Christopher Boguslaw Kocon , Marie Denison , Taylor Efland
发明人： Christopher Boguslaw Kocon , Marie Denison , Taylor Efland
IPC分类号： H01L27/088 , H01L29/78
CPC分类号： H01L27/088 , H01L27/0922 , H01L29/0634 , H01L29/0649 , H01L29/0696 , H01L29/404 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/4933 , H01L29/7802 , H01L29/7803 , H01L29/7809 , H01L29/7816 , H01L29/7835
摘要： A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region parallel to channel current flow. The RESURF trenches have dielectric liners and electrically conductive RESURF elements on the liners. Source contact metal is disposed over the body region and source regions. A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer, and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region perpendicular to channel current flow. Source contact metal is disposed in a source contact trench and extended over the drain drift region to provide a field plate.
摘要翻译：一种半导体器件，其包含在下漏极层上方具有漏极漂移区域的高电压MOS晶体管和横向设置在衬底顶表面处的沟道区域。 RESURF沟槽穿过漏极漂移区域和与通道电流流动平行的体区域。 RESURF沟槽在衬垫上具有电介质衬垫和导电RESURF元件。源接触金属设置在身体区域和源区域上。一种半导体器件，其包含在下漏极层上具有漏极漂移区域的高电压MOS晶体管，以及横向设置在衬底顶表面处的沟道区域。 RESURF沟槽穿过垂直于沟道电流的漏极漂移区域和体区。源极接触金属设置在源极接触沟槽中并在漏极漂移区域上延伸以提供场板。

64. 发明授权

US08617960B2 Silicon microphone transducer 有权
标题翻译：硅麦克风换能器
公开(公告)号：US08617960B2
公开(公告)日：2013-12-31
申请号：US12969784
申请日：2010-12-16
申请人： Marie Denison , Brian E. Goodlin , Wei-Yan Shih , Lance W. Barron
发明人： Marie Denison , Brian E. Goodlin , Wei-Yan Shih , Lance W. Barron
IPC分类号： H04R11/04 , H01L29/84 , H01L21/04
CPC分类号： H04R19/04 , H01L28/60
摘要： A capacitive microphone transducer integrated into an integrated circuit includes a fixed plate and a membrane formed in or above an interconnect region of the integrated circuit. A process of forming an integrated circuit containing a capacitive microphone transducer includes etching access trenches through the fixed plate to a region defined for the back cavity, filling the access trenches with a sacrificial material, and removing a portion of the sacrificial material from a back side of the integrated circuit.
摘要翻译：集成到集成电路中的电容麦克风换能器包括固定板和形成在集成电路的互连区域中或上方的膜。形成包含电容式麦克风换能器的集成电路的过程包括将通过固定板的访问沟槽蚀刻到为后腔定义的区域，用牺牲材料填充进入沟槽，以及从背面去除牺牲材料的一部分的集成电路。

65. 发明授权

US08598008B2 Stacked ESD clamp with reduced variation in clamp voltage 有权
标题翻译：堆叠的ESD钳位钳位电压变化较小
公开(公告)号：US08598008B2
公开(公告)日：2013-12-03
申请号：US13277939
申请日：2011-10-20
申请人： Sameer P. Pendharkar , Marie Denison , Yongxi Zhang
发明人： Sameer P. Pendharkar , Marie Denison , Yongxi Zhang
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L27/082 , H01L21/8222 , H01L27/0259 , H01L27/0823 , H01L29/735
摘要： An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed.
摘要翻译：公开了一种包含串联连接的两个双极晶体管的叠层双极晶体管的集成电路。每个双极晶体管包括击穿诱导特征。击穿诱发特征相对于彼此具有反射对称性。还公开了一种用于形成集成电路的方法，该集成电路包括具有串联连接的两个双极晶体管和具有反射对称性的击穿诱发特征的堆叠双极晶体管。

66. 发明申请

US20120104493A1 LATERAL SUPERJUNCTION EXTENDED DRAIN MOS TRANSISTOR 有权
标题翻译：横向超级扩展漏磁MOS晶体管
公开(公告)号：US20120104493A1
公开(公告)日：2012-05-03
申请号：US13284054
申请日：2011-10-28
申请人： Marie Denison , Sameer Pendhakar
发明人： Marie Denison , Sameer Pendhakar
IPC分类号： H01L29/78 , H01L21/762
CPC分类号： H01L29/7816 , H01L21/76224 , H01L29/0634 , H01L29/0649 , H01L29/0692 , H01L29/0696 , H01L29/0882 , H01L29/4236 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： An integrated circuit containing an extended drain MOS transistor with deep semiconductor (SC) RESURF trenches in the drift region, in which each deep SC RESURF trench has a semiconductor RESURF layer at a sidewall of the trench contacting the drift region. The semiconductor RESURF layer has an opposite conductivity type from the drift region. The deep SC RESURF trenches have depth:width ratios of at least 5:1, and do not extend through a bottom surface of the drift region. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching undersized trenches and counterdoping the sidewall region to form the semiconductor RESURF layer. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching trenches and growing an epitaxial layer on the sidewall region to form the semiconductor RESURF layer.
摘要翻译：一种集成电路，其包含在漂移区域中具有深半导体（SC）RESURF沟槽的扩展漏极MOS晶体管，其中每个深的SC RESURF沟槽在与漂移区接触的沟槽的侧壁处具有半导体RESURF层。半导体RESURF层具有与漂移区相反的导电类型。深的SC RESURF沟槽具有至少5：1的深度：宽度比，并且不延伸穿过漂移区域的底部表面。通过蚀刻尺寸不足的沟槽和反向掺杂侧壁区以形成半导体RESURF层，在漂移区中形成具有深SC RESURF沟槽的集成电路的工艺。通过蚀刻沟槽并在侧壁区域上生长外延层以形成半导体RESURF层，在漂移区中形成具有深SC RESURF沟槽的集成电路的工艺。

67. 发明申请

US20110158439A1 Silicon Microphone Transducer 有权
标题翻译：硅麦克风传感器
公开(公告)号：US20110158439A1
公开(公告)日：2011-06-30
申请号：US12969784
申请日：2010-12-16
申请人： Marie Denison , Brian E. Goodlin , Wei-Yan Shih , Lance W. Barron
发明人： Marie Denison , Brian E. Goodlin , Wei-Yan Shih , Lance W. Barron
IPC分类号： H04R11/04 , H01L29/84 , H01L21/04
CPC分类号： H04R19/04 , H01L28/60
摘要： A capacitive microphone transducer integrated into an integrated circuit includes a fixed plate and a membrane formed in or above an interconnect region of the integrated circuit. A process of forming an integrated circuit containing a capacitive microphone transducer includes etching access trenches through the fixed plate to a region defined for the back cavity, filling the access trenches with a sacrificial material, and removing a portion of the sacrificial material from a back side of the integrated circuit.
摘要翻译：集成到集成电路中的电容麦克风换能器包括固定板和形成在集成电路的互连区域中或上方的膜。形成包含电容式麦克风换能器的集成电路的过程包括将通过固定板的访问沟槽蚀刻到为后腔定义的区域，用牺牲材料填充进入沟槽，以及从背面去除牺牲材料的一部分的集成电路。

68. 发明申请

US20110151634A1 LATERAL DRAIN-EXTENDED MOSFET HAVING CHANNEL ALONG SIDEWALL OF DRAIN EXTENSION DIELECTRIC 有权
标题翻译：排水延伸电磁场的横向排水扩散型MOSFET
公开(公告)号：US20110151634A1
公开(公告)日：2011-06-23
申请号：US13027734
申请日：2011-02-15
申请人： Marie Denison , Taylor Rice Efland
发明人： Marie Denison , Taylor Rice Efland
IPC分类号： H01L21/336
CPC分类号： H01L29/7825 , H01L29/0653 , H01L29/0878 , H01L29/402 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66704
摘要： An integrated circuit (200) includes one of more transistors (210) on or in a substrate (10) having semiconductor surface layer, the surface layer having a top surface. At least one of the transistors are drain extended metal-oxide-semiconductor (DEMOS) transistor (210). The DEMOS transistor includes a drift region (14) in the surface layer having a first dopant type, a field dielectric (23) in or on a portion of the surface layer, and a body region of a second dopant type (16) within the drift region (14). The body region (16) has a body wall extending from the top surface of the surface layer downwards along at least a portion of a dielectric wall of an adjacent field dielectric region. A gate dielectric (21) is on at least a portion of the body wall. An electrically conductive gate electrode (22) is on the gate dielectric (21) on the body wall. A source region (18) of the first doping type is in the body region (16), a drain region (20) of the first doping type is in the drift region (14), and interconnects (521) are operable to electrically connect the one or more transistors to each other on the integrated circuit (200).
摘要翻译：集成电路（200）包括在具有半导体表面层的衬底（10）上或衬底（10）中的多个晶体管（210）中的一个，所述表面层具有顶表面。至少一个晶体管是漏极延伸的金属氧化物半导体（DEMOS）晶体管（210）。 DEMOS晶体管包括在表面层中具有第一掺杂剂类型的漂移区域（14），表面层的一部分中或之上的场电介质（23），以及在该层内的第二掺杂剂类型（16）的体区漂移区（14）。身体区域（16）具有从表面层的顶表面沿相邻场介电区域的电介质壁的至少一部分向下延伸的主体壁。门电介质（21）位于体壁的至少一部分上。导电栅电极（22）位于体壁上的栅电介质（21）上。第一掺杂型的源极区域（18）位于体区（16）中，第一掺杂型漏区（20）位于漂移区（14）中，互连（521）可操作以电连接集成电路（200）上的一个或多个晶体管彼此相连。

69. 发明授权

US07915676B2 Integrated circuit 有权
标题翻译：集成电路
公开(公告)号：US07915676B2
公开(公告)日：2011-03-29
申请号：US11186402
申请日：2005-07-21
申请人： Nils Jensen , Marie Denison
发明人： Nils Jensen , Marie Denison
IPC分类号： H01L29/94
CPC分类号： H01L29/7302 , H01L27/0248 , H01L29/7808 , H01L29/7809 , H01L29/7821 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to an integrated circuit having a semiconductor component (10) comprising a first p-type region (12) and a first n-type region (11) adjoining the first p-type region (12), which together form a first pn junction having a breakdown voltage. According to the invention, a further n-type region adjoining the first p-type region or a further p-type region (13) adjoining the first n-type region (11) is provided, the first p-type or n-type region (11) and the further n-type or p-type region (13) adjoining the latter together forming a further pn junction having a further breakdown voltage, the first pn junction and the further pn junction being connected or connectable to one another in such a way that, in the case of an overloading of the semiconductor component, on account of a current loading of the first pn junction, first of all the further pn junction breaks down.
摘要翻译：本发明涉及一种具有半导体元件（10）的集成电路，该半导体元件（10）包括第一p型区域（12）和毗邻第一p型区域（12）的第一n型区域（11），它们一起形成第一 pn结具有击穿电压。根据本发明，提供了邻接第一p型区域的另一个n型区域或与第一n型区域（11）相邻的另外的p型区域（13），第一p型或n型区域区域（11）和与之相邻的另外的n型或p型区域（13）一起形成具有另外的击穿电压的另外的pn结，所述第一pn结和所述另外的pn结可以彼此连接或连接这样一种方式，在半导体部件的过载的情况下，由于第一pn结的电流负载，首先进一步的pn结破裂。

70. 发明授权

US07253474B2 Quasi-vertical semiconductor component 有权
标题翻译：准垂直半导体元件
公开(公告)号：US07253474B2
公开(公告)日：2007-08-07
申请号：US10667629
申请日：2003-09-22
申请人： Marie Denison , Hannes Estl
发明人： Marie Denison , Hannes Estl
IPC分类号： H01L27/01
CPC分类号： H01L29/7811 , H01L29/0684 , H01L29/0688 , H01L29/0804 , H01L29/1004 , H01L29/1095 , H01L29/7322 , H01L29/7802
摘要： A quasi-vertical semiconductor component in which, by variation of the layout, the process or the wiring of inner cells, a compensation for a voltage drop along a buried layer is provided in order thus to ensure a similar operating point of the individual inner cells in the well. Therefore, the disadvantages brought about by a voltage drop in the buried layer are ultimately overcome.
摘要翻译：准垂直半导体元件，其中通过布局的变化，内部单元的处理或布线，沿着掩埋层提供对电压降的补偿，从而确保各个内部单元的类似工作点在井里。因此，最终克服了埋层中的电压降引起的缺点。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式