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1. 发明授权

US08471337B2 Integrated circuit 有权
标题翻译：集成电路
公开(公告)号：US08471337B2
公开(公告)日：2013-06-25
申请号：US13073755
申请日：2011-03-28
申请人： Nils Jensen , Marie Denison
发明人： Nils Jensen , Marie Denison
IPC分类号： H01L29/94
CPC分类号： H01L29/7302 , H01L27/0248 , H01L29/7808 , H01L29/7809 , H01L29/7821 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is disclosed having a semiconductor component comprising a first p-type region and a first n-type region adjoining the first p-type region, which together form a first pn junction having a breakdown voltage. A further n-type region adjoining the first p-type region or a further p-type region adjoining the first n-type region is provided, the first p-type or n-type region and the further n-type or p-type region adjoining the latter together forming a further pn junction having a further breakdown voltage, the first pn junction and the further pn junction being connected or connectable to one another in such a way that, in the case of an overloading of the semiconductor component, on account of a current loading of the first pn junction, first of all the further pn junction breaks down.
摘要翻译：公开了一种集成电路，其具有包括第一p型区域和与第一p型区域邻接的第一n型区域的半导体部件，其一起形成具有击穿电压的第一pn结。提供了与第一p型区域相邻的另一个n型区域或与第一n型区域相邻的另外的p型区域，第一p型或n型区域和另外的n型或p型区域区域相邻的区域一起形成具有另外的击穿电压的另外的pn结，第一pn结和另外的pn结彼此连接或连接，使得在半导体部件的过载的情况下，考虑到当前负载的第一个pn结，首先进一步的pn结分解。

2. 发明申请

US20110169564A1 Integrated Circuit 有权
标题翻译：集成电路
公开(公告)号：US20110169564A1
公开(公告)日：2011-07-14
申请号：US13073755
申请日：2011-03-28
申请人： Nils Jensen , Marie Denison
发明人： Nils Jensen , Marie Denison
IPC分类号： H01L25/00 , H01L23/58
CPC分类号： H01L29/7302 , H01L27/0248 , H01L29/7808 , H01L29/7809 , H01L29/7821 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is disclosed having a semiconductor component comprising a first p-type region and a first n-type region adjoining the first p-type region, which together form a first pn junction having a breakdown voltage. A further n-type region adjoining the first p-type region or a further p-type region adjoining the first n-type region is provided, the first p-type or n-type region and the further n-type or p-type region adjoining the latter together forming a further pn junction having a further breakdown voltage, the first pn junction and the further pn junction being connected or connectable to one another in such a way that, in the case of an overloading of the semiconductor component, on account of a current loading of the first pn junction, first of all the further pn junction breaks down.
摘要翻译：公开了一种集成电路，其具有包括第一p型区域和与第一p型区域邻接的第一n型区域的半导体部件，其一起形成具有击穿电压的第一pn结。提供了与第一p型区域相邻的另一个n型区域或与第一n型区域相邻的另外的p型区域，第一p型或n型区域和另外的n型或p型区域区域相邻的区域一起形成具有另外的击穿电压的另外的pn结，第一pn结和另外的pn结彼此连接或连接，使得在半导体部件的过载的情况下，考虑到当前负载的第一个pn结，首先进一步的pn结分解。

3. 发明申请

US20060071236A1 Integrated circuit 有权
标题翻译：集成电路
公开(公告)号：US20060071236A1
公开(公告)日：2006-04-06
申请号：US11186402
申请日：2005-07-21
申请人： Nils Jensen , Marie Denison
发明人： Nils Jensen , Marie Denison
IPC分类号： H01L29/74
CPC分类号： H01L29/7302 , H01L27/0248 , H01L29/7808 , H01L29/7809 , H01L29/7821 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to an integrated circuit having a semiconductor component (10) comprising a first p-type region (12) and a first n-type region (11) adjoining the first p-type region (12), which together form a first pn junction having a breakdown voltage. According to the invention, a further n-type region adjoining the first p-type region or a further p-type region (13) adjoining the first n-type region (11) is provided, the first p-type or n-type region (11) and the further n-type or p-type region (13) adjoining the latter together forming a further pn junction having a further breakdown voltage, the first pn junction and the further pn junction being connected or connectable to one another in such a way that, in the case of an overloading of the semiconductor component, on account of a current loading of the first pn junction, first of all the further pn junction breaks down.
摘要翻译：本发明涉及一种具有半导体元件（10）的集成电路，该半导体元件（10）包括第一p型区域（12）和毗邻第一p型区域（12）的第一n型区域（11），它们一起形成第一 pn结具有击穿电压。根据本发明，提供了邻接第一p型区域的另一个n型区域或与第一n型区域（11）相邻的另外的p型区域（13），第一p型或n型区域区域（11）和与之相邻的另外的n型或p型区域（13）一起形成具有另外的击穿电压的另外的pn结，所述第一pn结和所述另外的pn结可以彼此连接或连接这样一种方式，在半导体部件的过载的情况下，由于第一pn结的电流负载，首先进一步的pn结破裂。

4. 发明授权

US07915676B2 Integrated circuit 有权
标题翻译：集成电路
公开(公告)号：US07915676B2
公开(公告)日：2011-03-29
申请号：US11186402
申请日：2005-07-21
申请人： Nils Jensen , Marie Denison
发明人： Nils Jensen , Marie Denison
IPC分类号： H01L29/94
CPC分类号： H01L29/7302 , H01L27/0248 , H01L29/7808 , H01L29/7809 , H01L29/7821 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to an integrated circuit having a semiconductor component (10) comprising a first p-type region (12) and a first n-type region (11) adjoining the first p-type region (12), which together form a first pn junction having a breakdown voltage. According to the invention, a further n-type region adjoining the first p-type region or a further p-type region (13) adjoining the first n-type region (11) is provided, the first p-type or n-type region (11) and the further n-type or p-type region (13) adjoining the latter together forming a further pn junction having a further breakdown voltage, the first pn junction and the further pn junction being connected or connectable to one another in such a way that, in the case of an overloading of the semiconductor component, on account of a current loading of the first pn junction, first of all the further pn junction breaks down.
摘要翻译：本发明涉及一种具有半导体元件（10）的集成电路，该半导体元件（10）包括第一p型区域（12）和毗邻第一p型区域（12）的第一n型区域（11），它们一起形成第一 pn结具有击穿电压。根据本发明，提供了邻接第一p型区域的另一个n型区域或与第一n型区域（11）相邻的另外的p型区域（13），第一p型或n型区域区域（11）和与之相邻的另外的n型或p型区域（13）一起形成具有另外的击穿电压的另外的pn结，所述第一pn结和所述另外的pn结可以彼此连接或连接这样一种方式，在半导体部件的过载的情况下，由于第一pn结的电流负载，首先进一步的pn结破裂。

5. 发明授权

US09806190B2 High voltage drain extension on thin buried oxide SOI 有权
公开(公告)号：US09806190B2
公开(公告)日：2017-10-31
申请号：US13282305
申请日：2011-10-26
申请人： Marie Denison , Philip L. Hower , Sameer Pendharkar
发明人： Marie Denison , Philip L. Hower , Sameer Pendharkar
IPC分类号： H01L29/78 , H01L21/336 , H01L27/12 , H01L29/10 , H01L29/861 , H01L27/06
CPC分类号： H01L29/7824 , H01L27/0629 , H01L27/1203 , H01L29/1087 , H01L29/7818 , H01L29/7835 , H01L29/861
摘要： An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) so that the drain or body region is coupled to the handle wafer through a p-n junction. An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) coupled to the handle wafer through a p-n junction, that is electrically isolated from the drain or body region. A process of forming an integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel).

6. 发明授权

US08866263B2 Emitter ballasting by contact area segmentation in ESD bipolar based semiconductor component 有权
标题翻译：通过ESD双极型半导体元件中的接触区域分割发射器镇流
公开(公告)号：US08866263B2
公开(公告)日：2014-10-21
申请号：US11863971
申请日：2007-09-28
申请人： Marie Denison
发明人： Marie Denison
IPC分类号： H01L23/48 , H01L27/02 , H01L23/00 , H01L27/06
CPC分类号： H01L27/0259 , H01L24/05 , H01L27/0641 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/00
摘要： Integrated circuits (ICs) utilize bipolar transistors in electro-static discharge (ESD) protection circuits to shunt discharge currents during ESD events to protect the components in the ICs. Bipolar transistors are subject to non-uniform current crowding across the emitter-base junction during ESD events, which results in less protection for the IC components and degradation of the bipolar transistor. This invention comprises multiple contact islands (126) on the emitter (116) of a bipolar transistor, which act to spread current uniformly across the emitter-base junction. Also included in this invention is segmentation of the emitter diffused region to further improve current uniformity and biasing of the transistor. This invention can be combined with drift region ballasting or back-end ballasting to optimize an ESD protection circuit.
摘要翻译：集成电路（IC）利用静电放电（ESD）保护电路中的双极晶体管在ESD事件期间分流放电电流，以保护IC中的组件。在ESD事件期间，双极晶体管在发射极 - 基极结上受到不均匀的电流拥挤，这导致对IC器件的更少的保护和双极晶体管的劣化。本发明包括在双极晶体管的发射极（116）上的多个接触岛（126），其用于均匀地扩散电流穿过发射极 - 基极结。本发明还包括发射极扩散区域的分割，以进一步提高晶体管的电流均匀性和偏置。本发明可以与漂移区镇流或后端镇流相组合，以优化ESD保护电路。

7. 发明授权

US08853029B2 Method of making vertical transistor with graded field plate dielectric 有权
标题翻译：制造具有梯度场板电介质的垂直晶体管的方法
公开(公告)号：US08853029B2
公开(公告)日：2014-10-07
申请号：US13188162
申请日：2011-07-21
申请人： Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin
发明人： Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin
IPC分类号： H01L21/336 , H01L29/66 , H01L29/78 , H01L29/423
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/66719 , H01L29/66734
摘要： An electronic device has a plurality of trenches formed in a semiconductor layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric having increased thickness at greater depth is located between the field plate section and the vertical drift region.
摘要翻译：电子器件具有形成在半导体层中的多个沟槽。垂直漂移区域位于沟槽之间和相邻的沟槽之间。电极位于每个沟槽内，电极具有栅电极部分和场板部分。在场板部分和垂直漂移区域之间设置具有较大深度的厚度增加的分级场板电介质。

8. 发明申请

US20130062996A1 MEMS DEVICE FABRICATED WITH INTEGRATED CIRCUIT 有权
标题翻译：具有集成电路的MEMS器件
公开(公告)号：US20130062996A1
公开(公告)日：2013-03-14
申请号：US13230350
申请日：2011-09-12
申请人： Kezhakkedath R. Udayakumar , Marie Denison , Ted S. Moise
发明人： Kezhakkedath R. Udayakumar , Marie Denison , Ted S. Moise
IPC分类号： H01L41/04 , H01L21/02
CPC分类号： H01L41/08 , H01L27/20 , H01L41/0533 , H01L41/1134 , H01L41/1136 , H01L41/1138 , H01L41/22 , H01L41/318 , H01L2224/18
摘要： A planar integrated MEMS device has a piezoelectric element on a dielectric isolation layer over a flexible element attached to a proof mass. The piezoelectric element contains a ferroelectric element with a perovskite structure formed over an isolation dielectric. At least two electrodes are formed on the ferroelectric element. An upper hydrogen barrier is formed over the piezoelectric element. Front side singulation trenches are formed at a periphery of the MEMS device extending into the semiconductor substrate. A DRIE process removes material from the bottom side of the substrate to form the flexible element, removes material from the substrate under the front side singulation trenches, and forms the proof mass from substrate material. The piezoelectric element overlaps the flexible element.
摘要翻译：平面集成MEMS器件在连接到校准块的柔性元件上的介电隔离层上具有压电元件。压电元件包含在隔离电介质上形成的具有钙钛矿结构的铁电元件。在铁电元件上形成至少两个电极。在压电元件上形成上部氢屏障。在延伸到半导体衬底中的MEMS器件的周边形成有正面侧划分沟槽。 DRIE工艺从衬底的底侧去除材料以形成柔性元件，在正面单面沟槽之下从衬底去除材料，并从衬底材料形成校验物质。压电元件与柔性元件重叠。

9. 发明申请

US20120104497A1 HIGH VOLTAGE DRAIN EXTENSION ON THIN BURIED OXIDE SOI 有权
标题翻译：稀土氧化物SOI上的高压漏电延伸
公开(公告)号：US20120104497A1
公开(公告)日：2012-05-03
申请号：US13282305
申请日：2011-10-26
申请人： Marie Denison , Philip L. Hower , Sameer Pendharkar
发明人： Marie Denison , Philip L. Hower , Sameer Pendharkar
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7824 , H01L27/0629 , H01L27/1203 , H01L29/1087 , H01L29/7818 , H01L29/7835 , H01L29/861
摘要： An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) so that the drain or body region is coupled to the handle wafer through a p-n junction. An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) coupled to the handle wafer through a p-n junction, that is electrically isolated from the drain or body region. A process of forming an integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel).
摘要翻译： SOI衬底上的集成电路，其包含在漏极（n沟道）或体区（p沟道）中具有穿通衬底二极管的扩展漏极MOS晶体管，使得漏极或体区域通过pn耦合到处理晶片交界处在SOI衬底上的集成电路，其包含通过pn结耦合到处理晶片的漏极（n沟道）或体区（p沟道）中的贯穿衬底二极管的延伸漏极MOS晶体管，其与排水或身体区域。在包含漏极（n沟道）或体区（p沟道）中的贯通衬底二极管的延伸漏极MOS晶体管的SOI衬底上形成集成电路的工艺。

10. 发明申请

US20110111569A1 MOS TRANSISTOR WITH GATE TRENCH ADJACENT TO DRAIN EXTENSION FIELD INSULATION 有权
标题翻译：具有栅极扩展的MOS晶体管与漏极扩展场绝缘相邻
公开(公告)号：US20110111569A1
公开(公告)日：2011-05-12
申请号：US13006589
申请日：2011-01-14
申请人： Marie Denison , Sameer Pendharkar , Binghua Hu , Taylor Rice Efland , Sridhar Seetharaman
发明人： Marie Denison , Sameer Pendharkar , Binghua Hu , Taylor Rice Efland , Sridhar Seetharaman
IPC分类号： H01L21/336
CPC分类号： H01L29/7825 , H01L29/0653 , H01L29/0696 , H01L29/086 , H01L29/0865 , H01L29/0869 , H01L29/0878 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66689 , H01L29/66704
摘要： An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.
摘要翻译：一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的沟槽栅极。体阱和源极扩散区域与栅极沟槽的底表面重叠。一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的第一沟槽栅极和位于重掺杂掩埋层上方的第二沟槽栅极。埋层是与漂移区相同的导电类型。形成包含MOS晶体管的集成电路的过程，其包括在晶体管的漏极的漂移区上方的隔离电介质层和形成在栅极沟槽中的栅极，该栅极与隔离电介质层相邻。通过去除与隔离电介质层相邻的衬底材料形成栅极沟槽。

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