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61. 发明申请

US20110161588A1 FORMATION OF AN EXCLUSIVE OWNERSHIP COHERENCE STATE IN A LOWER LEVEL CACHE 有权
标题翻译：在较低级别的高速缓存中形成独家所有权的相关状态
公开(公告)号：US20110161588A1
公开(公告)日：2011-06-30
申请号：US12649725
申请日：2009-12-30
申请人： Guy L. Guthrie , William J. Starke , Jeffrey Stuecheli , Derek E. Williams , Phillip G. Williams
发明人： Guy L. Guthrie , William J. Starke , Jeffrey Stuecheli , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0811 , G06F9/3834 , G06F12/0815 , G06F12/0831 , Y02D10/13
摘要： In response to a memory access request of a processor core that targets a target cache line, the lower level cache of a vertical cache hierarchy associated with the processor core supplies a copy of the target cache line to an upper level cache in the vertical cache hierarchy and retains a copy in a shared coherence state. The upper level cache holds the copy of the target cache line in a private shared ownership coherence state indicating that each cached copy of the target memory block is cached within the vertical cache hierarchy associated with the processor core. In response to the upper level cache signaling replacement of the copy of the target cache line in the private shared ownership coherence state, the lower level cache updates its copy of the target cache line to the exclusive ownership coherence state without coherency messaging with other vertical cache hierarchies.
摘要翻译：响应于针对目标高速缓存线的处理器核心的存储器访问请求，与处理器核心相关联的垂直高速缓存层级的较低级缓存将目标高速缓存行的副本提供给垂直高速缓存层级中的高级缓存并保留共享一致状态的副本。高级缓存将目标高速缓存行的副本保存在私有共享所有权一致状态中，指示目标存储器块的每个高速缓存副本被缓存在与处理器核心相关联的垂直高速缓存层级内。响应于在私有共享所有权相干状态下高级缓存信令替换目标高速缓存行的副本，下级缓存将其目标高速缓存行的副本更新为独占所有权相干状态，而不与其他垂直高速缓存的一致性消息传递层次结构。

62. 发明申请

US20110153943A1 Aggregate Data Processing System Having Multiple Overlapping Synthetic Computers 有权
标题翻译：具有多重重合成计算机的综合数据处理系统
公开(公告)号：US20110153943A1
公开(公告)日：2011-06-23
申请号：US12643800
申请日：2009-12-21
申请人： Guy L. Guthrie , Charles F. Marino , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , Charles F. Marino , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00 , G06F12/14 , G06F12/08
CPC分类号： G06F12/0813 , G06F12/0284 , G06F15/167
摘要： A first SMP computer has first and second processing units and a first system memory pool, a second SMP computer has third and fourth processing units and a second system memory pool, and a third SMP computer has at least fifth and sixth processing units and third, fourth and fifth system memory pools. The fourth system memory pool is inaccessible to the third, fourth and sixth processing units and accessible to at least the second and fifth processing units, and the fifth system memory pool is inaccessible to the first, second and sixth processing units and accessible to at least the fourth and fifth processing units. A first interconnect couples the second processing unit for load-store coherent, ordered access to the fourth system memory pool, and a second interconnect couples the fourth processing unit for load-store coherent, ordered access to the fifth system memory pool.
摘要翻译：第一SMP计算机具有第一和第二处理单元和第一系统存储器池，第二SMP计算机具有第三和第四处理单元和第二系统存储器池，并且第三SMP计算机具有至少第五和第六处理单元，第三SMP计算机具有至少第五和第六处理单元，第四和第五系统内存池。第四系统存储器池对于第三，第四和第六处理单元是不可访问的，并且可访问至少第二和第五处理单元，并且第五系统存储器池对于第一，第二和第六处理单元是不可访问的，并且至少可访问第四和第五处理单元。第一互连耦合第二处理单元，用于对第四系统存储池进行加载存储相关的有序访问，并且第二互连耦合第四处理单元，用于加载存储相关的有序访问到第五系统存储池。

63. 发明申请

US20100268884A1 Updating Partial Cache Lines in a Data Processing System 有权
标题翻译：更新数据处理系统中的部分缓存行
公开(公告)号：US20100268884A1
公开(公告)日：2010-10-21
申请号：US12424434
申请日：2009-04-15
申请人： David W. Cummings , Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams , Phillip G. Williams
发明人： David W. Cummings , Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0822 , G06F12/0897 , G06F2212/507
摘要： A processing unit for a data processing system includes a processor core having one or more execution units for processing instructions and a register file for storing data accessed in processing of the instructions. The processing unit also includes a multi-level cache hierarchy coupled to and supporting the processor core. The multi-level cache hierarchy includes at least one upper level of cache memory having a lower access latency and at least one lower level of cache memory having a higher access latency. The lower level of cache memory, responsive to receipt of a memory access request that hits only a partial cache line in the lower level cache memory, sources the partial cache line to the at least one upper level cache memory to service the memory access request. The at least one upper level cache memory services the memory access request without caching the partial cache line.
摘要翻译：用于数据处理系统的处理单元包括具有一个或多个用于处理指令的执行单元的处理器核心和用于存储在指令处理中访问的数据的寄存器文件。处理单元还包括耦合到并支持处理器核的多级高速缓存层级。多级高速缓存层级包括具有较低访问延迟的至少一个高级缓存存储器和具有较高访问延迟的至少一个较低级别的高速缓存存储器。响应于仅接收低级高速缓冲存储器中的部分高速缓存行的存储器访问请求的响应，较低级别的高速缓存存储器将部分高速缓存行源送到至少一个上级高速缓冲存储器以服务存储器访问请求。至少一个上级缓存存储器服务于存储器访问请求，而不缓存部分高速缓存行。

64. 发明申请

US20100257316A1 Virtual Barrier Synchronization Cache Castout Election 失效
标题翻译：虚拟障碍同步缓存铸造选举
公开(公告)号：US20100257316A1
公开(公告)日：2010-10-07
申请号：US12419343
申请日：2009-04-07
申请人： Ravi K. Arimilli , Guy L. Guthrie , Michael Siegel , William J. Starke , Derek E. Williams
发明人： Ravi K. Arimilli , Guy L. Guthrie , Michael Siegel , William J. Starke , Derek E. Williams
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0811 , G06F9/30101 , G06F9/3851 , G06F9/522
摘要： A data processing system includes an interconnect fabric, a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs), and a plurality of processing units coupled to the interconnect fabric and operable to access the virtual barrier synchronization region. Each of the plurality of processing units includes a processor core and a cache memory including a cache controller and a cache array that caches VBSR lines from the virtual barrier synchronization region of the system memory. The cache controller of a first processing unit, responsive to a memory access request from its processor core that targets a first VBSR line, transfers responsibility for writing back to the virtual barrier synchronization region a second VBSR line contemporaneously held in the cache arrays of first, second and third processing units. The responsibility is transferred via an election held over the interconnect fabric.
摘要翻译：数据处理系统包括互连结构，耦合到互连结构并包括分配给虚拟屏障同步寄存器（VBSR）的存储的虚拟屏障同步区域的系统存储器，以及耦合到互连结构的多个处理单元，访问虚拟屏障同步区域。多个处理单元中的每一个包括处理器核心和高速缓存存储器，其包括高速缓存控制器和从系统存储器的虚拟屏障同步区域缓存VBSR行的高速缓存阵列。响应于来自其处理器核心的第一VBSR线路的存储器访问请求的第一处理单元的高速缓存控制器将负责向第一虚拟屏障同步区域写回同时保存在第一VBSR线路的高速缓存阵列中的第二VBSR线路，第二和第三处理单元。通过互连结构上的选举来转移责任。

65. 发明授权

US09110808B2 Formation of an exclusive ownership coherence state in a lower level cache upon replacement from an upper level cache of a cache line in a private shared owner state 有权
标题翻译：在私有共享所有者状态下从高速缓存行的高级缓存替换时，在下级缓存中形成独占所有权一致性状态
公开(公告)号：US09110808B2
公开(公告)日：2015-08-18
申请号：US12649725
申请日：2009-12-30
申请人： Guy L. Guthrie , William J. Starke , Jeffrey Stuecheli , Derek E. Williams , Phillip G. Williams
发明人： Guy L. Guthrie , William J. Starke , Jeffrey Stuecheli , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/00 , G06F12/08 , G06F9/38
CPC分类号： G06F12/0811 , G06F9/3834 , G06F12/0815 , G06F12/0831 , Y02D10/13
摘要： In response to a memory access request of a processor core that targets a target cache line, the lower level cache of a vertical cache hierarchy associated with the processor core supplies a copy of the target cache line to an upper level cache in the vertical cache hierarchy and retains a copy in a shared coherence state. The upper level cache holds the copy of the target cache line in a private shared ownership coherence state indicating that each cached copy of the target memory block is cached within the vertical cache hierarchy associated with the processor core. In response to the upper level cache signaling replacement of the copy of the target cache line in the private shared ownership coherence state, the lower level cache updates its copy of the target cache line to the exclusive ownership coherence state without coherency messaging with other vertical cache hierarchies.
摘要翻译：响应于针对目标高速缓存线的处理器核心的存储器访问请求，与处理器核心相关联的垂直高速缓存层级的较低级缓存将目标高速缓存行的副本提供给垂直高速缓存层级中的高级缓存并保留共享一致状态的副本。高级缓存将目标高速缓存行的副本保存在私有共享所有权一致状态中，指示目标存储器块的每个高速缓存副本被缓存在与处理器核心相关联的垂直高速缓存层级内。响应于在私有共享所有权相干状态下高级缓存信令替换目标高速缓存行的副本，下级缓存将其目标高速缓存行的副本更新为独占所有权相干状态，而不与其他垂直高速缓存的一致性消息传递层次结构。

66. 发明授权

US08683140B2 Cache-based speculation of stores following synchronizing operations 失效
标题翻译：同步操作后，存储器中基于缓存的推测
公开(公告)号：US08683140B2
公开(公告)日：2014-03-25
申请号：US13456420
申请日：2012-04-26
申请人： Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0837 , G06F12/0895
摘要： A method of processing store requests in a data processing system includes enqueuing a store request in a store queue of a cache memory of the data processing system. The store request identifies a target memory block by a target address and specifies store data. While the store request and a barrier request older than the store request are enqueued in the store queue, a read-claim machine of the cache memory is dispatched to acquire coherence ownership of target memory block of the store request. After coherence ownership of the target memory block is acquired and the barrier request has been retired from the store queue, a cache array of the cache memory is updated with the store data.
摘要翻译：在数据处理系统中处理存储请求的方法包括在数据处理系统的高速缓存存储器的存储队列中引入存储请求。存储请求通过目标地址识别目标存储器块并指定存储数据。当存储请求和存储请求之前的屏障请求在存储队列中排队时，调度高速缓冲存储器的读取机器以获取存储请求的目标存储器块的一致性所有权。在获取目标存储器块的一致性所有权并且屏障请求已经从存储队列中退出之后，用存储数据更新高速缓冲存储器的高速缓存阵列。

67. 发明申请

US20130262778A1 DATA CACHE BLOCK DEALLOCATE REQUESTS IN A MULTI-LEVEL CACHE HIERARCHY 有权
标题翻译：数据缓存区块在多级高速缓存中调用请求
公开(公告)号：US20130262778A1
公开(公告)日：2013-10-03
申请号：US13433048
申请日：2012-03-28
申请人： Sanjeev Ghai , Guy L. Guthrie , William J. Starke , Jeff A. Stuecheli , Derek E. Williams , Phillip G. Williams
发明人： Sanjeev Ghai , Guy L. Guthrie , William J. Starke , Jeff A. Stuecheli , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/12
CPC分类号： G06F12/0817 , G06F12/0804 , G06F12/121 , G06F12/122 , G06F12/126
摘要： In response to executing a deallocate instruction, a deallocation request specifying a target address of a target cache line is sent from a processor core to a lower level cache. In response, a determination is made if the target address hits in the lower level cache. If so, the target cache line is retained in a data array of the lower level cache, and a replacement order field of the lower level cache is updated such that the target cache line is more likely to be evicted in response to a subsequent cache miss in a congruence class including the target cache line. In response to the subsequent cache miss, the target cache line is cast out to the lower level cache with an indication that the target cache line was a target of a previous deallocation request of the processor core.
摘要翻译：响应于执行取消分配指令，将指定目标高速缓存行的目标地址的解除分配请求从处理器核发送到较低级高速缓存。作为响应，确定目标地址是否在较低级别高速缓存中。如果是这样，则目标高速缓存行被保留在较低级高速缓存的数据阵列中，并且更新较低级高速缓存的替换顺序字段，使得目标高速缓存行更可能响应于后续高速缓存未命中而被驱逐在包含目标缓存行的同余类中。响应于随后的高速缓存未命中，目标高速缓存行被推出到较低级缓存，指示目标高速缓存行是处理器核心的先前释放请求的目标。

68. 发明授权

US08332588B2 Performing a partial cache line storage-modifying operation based upon a hint 失效
标题翻译：基于提示执行部分缓存行存储修改操作
公开(公告)号：US08332588B2
公开(公告)日：2012-12-11
申请号：US13349315
申请日：2012-01-12
申请人： Ravi K. Arimilli , Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Ravi K. Arimilli , Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/04
CPC分类号： G06F12/0822
摘要： Analyzing pre-processed code includes identifying at least one storage-modifying construct specifying a storage-modifying memory access to a memory hierarchy of a data processing system and determining if more than one granule of a cache line of data containing multiple granules that is targeted by the storage-modifying construct is subsequently referenced by said pre-processed code. Post-processed code including a storage-modifying instruction corresponding to the at least one storage-modifying construct in the pre-processed code is generated and stored. Generating the post-processed code includes marking the storage-modifying instruction with a partial cache line hint indicating that said storage-modifying instruction targets less than a full cache line of data within a memory hierarchy if the analyzing indicates only one granule of the target cache line will be accessed while the cache line is held in the cache memory and otherwise refraining from marking the storage-modifying instruction with the partial cache line hint.
摘要翻译：分析预处理的代码包括识别指定对数据处理系统的存储器层次结构的存储修改存储器访问的至少一个存储修改结构，并且确定是否存在多个颗粒的高速缓存行数据，所述数据包含多个颗粒的高速缓存行是由存储修改结构随后由所述预处理代码引用。生成并存储包括与预处理代码中的至少一个存储修改结构对应的存储修改指令的后处理代码。生成后处理代码包括用部分高速缓存线提示标记存储修改指令，指示所述存储修改指令的目标小于存储器层次结构内的完整高速缓存数据行，如果分析仅指示目标高速缓存的一个颗粒将高速缓存线保持在高速缓存存储器中，并以其它方式避免使用部分高速缓存线提示来标记存储修改指令。

69. 发明申请

US20120265938A1 PERFORMING A PARTIAL CACHE LINE STORAGE-MODIFYING OPERATION BASED UPON A HINT 失效
标题翻译：根据提示执行部分缓存线存储 - 修改操作
公开(公告)号：US20120265938A1
公开(公告)日：2012-10-18
申请号：US13349315
申请日：2012-01-12
申请人： Ravi K. Arimilli , Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Ravi K. Arimilli , Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0822
摘要： Analyzing pre-processed code includes identifying at least one storage-modifying construct specifying a storage-modifying memory access to a memory hierarchy of a data processing system and determining if more than one granule of a cache line of data containing multiple granules that is targeted by the storage-modifying construct is subsequently referenced by said pre-processed code. Post-processed code including a storage-modifying instruction corresponding to the at least one storage-modifying construct in the pre-processed code is generated and stored. Generating the post-processed code includes marking the storage-modifying instruction with a partial cache line hint indicating that said storage-modifying instruction targets less than a full cache line of data within a memory hierarchy if the analyzing indicates only one granule of the target cache line will be accessed while the cache line is held in the cache memory and otherwise refraining from marking the storage-modifying instruction with the partial cache line hint.
摘要翻译：分析预处理的代码包括识别指定对数据处理系统的存储器层次结构的存储修改存储器访问的至少一个存储修改结构，并且确定是否存在多个颗粒的高速缓存行数据，所述数据包含多个颗粒的高速缓存行是由存储修改结构随后由所述预处理代码引用。生成并存储包括与预处理代码中的至少一个存储修改结构对应的存储修改指令的后处理代码。生成后处理代码包括用部分高速缓存线提示标记存储修改指令，指示所述存储修改指令的目标小于存储器层次结构内的完整高速缓存数据行，如果分析仅指示目标高速缓存的一个颗粒将高速缓存线保持在高速缓存存储器中，并以其它方式避免使用部分高速缓存线提示来标记存储修改指令。

70. 发明申请

US20120210072A1 CACHE-BASED SPECULATION OF STORES FOLLOWING SYNCHRONIZING OPERATIONS 失效
标题翻译：随着同步操作的基于缓存的库存分析
公开(公告)号：US20120210072A1
公开(公告)日：2012-08-16
申请号：US13456420
申请日：2012-04-26
申请人： Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0837 , G06F12/0895
摘要： A method of processing store requests in a data processing system includes enqueuing a store request in a store queue of a cache memory of the data processing system. The store request identifies a target memory block by a target address and specifies store data. While the store request and a barrier request older than the store request are enqueued in the store queue, a read-claim machine of the cache memory is dispatched to acquire coherence ownership of target memory block of the store request. After coherence ownership of the target memory block is acquired and the barrier request has been retired from the store queue, a cache array of the cache memory is updated with the store data.
摘要翻译：在数据处理系统中处理存储请求的方法包括在数据处理系统的高速缓存存储器的存储队列中引入存储请求。存储请求通过目标地址识别目标存储器块并指定存储数据。当存储请求和存储请求之前的屏障请求在存储队列中排队时，调度高速缓冲存储器的读取机器以获取存储请求的目标存储器块的一致性所有权。在获取目标存储器块的一致性所有权并且屏障请求已经从存储队列中退出之后，用存储数据更新高速缓冲存储器的高速缓存阵列。

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