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    • 66. 发明申请
    • Electronic Circuit
    • 电子电路
    • US20090210599A1
    • 2009-08-20
    • US11794668
    • 2006-01-11
    • Tsuyoshi Nakamura
    • Tsuyoshi Nakamura
    • G06F13/24
    • G06F11/2038G06F11/2028G06F11/2035
    • An electronic circuit comprises a bus (300), a processor unit (100), and an operating sector (400). The operating sector (400) includes a first operating unit (421), a second operating unit (422), a third operating unit (423), registers (431) to (434), a first selector (441), a second selector (442), a switching unit (450), and a controller (410). For example, when the processor unit (100) substitutes processing of the second operating unit (422), the switching unit (450) selects output data (D12) of the first operating unit (421), and the second selector (442) selects processing result (D10) that is performed by the processor unit (100). Then, the switching unit (450) inputs the result into the third operating unit (423).
    • 电子电路包括总线(300),处理器单元(100)和操作扇区(400)。 操作扇区(400)包括第一操作单元(421),第二操作单元(422),第三操作单元(423),寄存器(431)至(434),第一选择器(441),第二选择器 (442),切换单元(450)和控制器(410)。 例如,当处理器单元(100)代替第二操作单元(422)的处理时,切换单元(450)选择第一操作单元(421)的输出数据(D12),第二选择器(442)选择 由处理器单元(100)执行的处理结果(D10)。 然后,切换单元(450)将结果输入到第三操作单元(423)。
    • 67. 发明申请
    • VARIABLE LENGTH DECODING METHOD AND DEVICE
    • 可变长度解码方法和设备
    • US20090085781A1
    • 2009-04-02
    • US12243231
    • 2008-10-01
    • Masahiro OHASHITsuyoshi Nakamura
    • Masahiro OHASHITsuyoshi Nakamura
    • H03M7/40
    • H03M7/425H03M7/40
    • A variable length decoding device comprises a CPU, a variable length decoding unit, an encoded data memory, a decoded data memory, and a mass memory. The variable length decoding unit comprises a decoding table memory operable to store decoding table, a standard information storage unit operable to store standard information of encoded data, and a frequency information storage unit operable to store information on frequency of usage of each table element of the decoding table. According to the structure, the decoding table is not necessary to transfer when decoding the encoded data based on the same standard of the previously-decoded encoded data. The decoding table to be stored in the decoding table memory can be composed by table elements of higher frequency of usage, thereby decreasing occurrence of cache error.
    • 可变长度解码装置包括CPU,可变长度解码单元,编码数据存储器,解码数据存储器和大容量存储器。 可变长度解码单元包括可操作以存储解码表的解码表存储器,用于存储编码数据的标准信息的标准信息存储单元,以及频率信息存储单元,用于存储关于编码数据的每个表格元素的使用频率的信息 解码表。 根据该结构,基于相同的先前解码的编码数据的标准,解码表不需要在对编码数据进行解码时进行传送。 要存储在解码表存储器中的解码表可以由较高使用频率的表格元素组成,从而减少高速缓存错误的发生。
    • 70. 发明申请
    • Simulator and simulation method
    • 模拟器和仿真方法
    • US20050091028A1
    • 2005-04-28
    • US10969027
    • 2004-10-21
    • Takahiro KondoTsuyoshi NakamuraMaiko TarukiTomonori Yonezawa
    • Takahiro KondoTsuyoshi NakamuraMaiko TarukiTomonori Yonezawa
    • G06F11/28G06F9/455G06F11/30G06F17/50G06F9/45
    • G06F17/5022
    • A simulator operable to simulate behaviors of a processor using software is provided. The simulator includes a command input unit, a memory element, a register element, a control element, a resource information storage unit, and a resource access-analyzing unit. The command input unit is operable to analyze/process entered commands. The memory element is operable to store executive instructions issued by the processor and data treated by the processor. The register element is operable to contain data for use in calculation. The control element is operable to access the memory element and register element in accordance with the executive instructions. The resource information storage unit is operable to contain specified resource information and a piece of read/write information for each piece of the resource information. The resource access-analyzing unit is operable to compare access destinations (the memory element and register element to be accessed by the control element) and a read/write classification with the resource information and read/write information contained in the resource information storage unit, thereby practicing a resource access analysis as to whether or not the access destinations are allowed by the resource information and read/write information.
    • 提供了一种可以使用软件模拟处理器行为的模拟器。 模拟器包括命令输入单元,存储元件,寄存器元件,控制元件,资源信息存储单元和资源访问分析单元。 命令输入单元用于分析/处理输入的命令。 存储元件可操作以存储处理器发出的执行指令和由处理器处理的数据。 寄存器元件可操作地包含用于计算的数据。 控制元件可操作以根据执行指令访问存储器元件和寄存器元件。 资源信息存储单元可操作以对于每个资源信息包含指定的资源信息和一条读/写信息。 资源访问分析单元可操作以将资源信息存储单元中包含的资源信息和读取/写入信息的访问目的地(由控制元素访问的存储元件和注册元素)与读/写分类进行比较, 从而对资源信息和读/写信息是否允许访问目的地进行资源访问分析。