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61. 发明授权

US06548861B2 Memory cell, memory cell arrangement and fabrication method 有权
标题翻译：存储单元，存储单元布置和制造方法
公开(公告)号：US06548861B2
公开(公告)日：2003-04-15
申请号：US09900649
申请日：2001-07-06
申请人： Herbert Palm , Josef Willer
发明人： Herbert Palm , Josef Willer
IPC分类号： H09L2996
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L29/66833
摘要： An electrically conductive layer or layer sequence preferably includes a metal-containing layer applied to a metal silicide or a polysilicon layer to reduce the resistance of buried bit lines. The layer or layer sequence has been patterned in strip form so as to correspond to the bit lines and is arranged on the source/drain regions of memory transistors having an ONO memory layer sequence and gate electrodes that are arranged in trenches. The metal silicide is preferably cobalt silicide, and the metal-containing layer is preferably tungsten silicide or WN/W.
摘要翻译：导电层或层序列优选地包括施加到金属硅化物或多晶硅层的含金属层以降低掩埋位线的电阻。层或层序列已经以带状形式图案化，以对应于位线，并且布置在具有ONO存储层序列的存储晶体管的源极/漏极区域和布置在沟槽中的栅极电极。金属硅化物优选为硅化钴，并且含金属层优选为硅化钨或WN / W。

62. 发明授权

US06525363B1 Integrated circuit configuration with at least one capacitor and method for producing the same 有权
标题翻译：具有至少一个电容器的集成电路配置及其制造方法
公开(公告)号：US06525363B1
公开(公告)日：2003-02-25
申请号：US09677433
申请日：2000-10-02
申请人： Josef Willer , Bernhard Sell , Dirk Schumann
发明人： Josef Willer , Bernhard Sell , Dirk Schumann
IPC分类号： H01L27108
CPC分类号： H01L28/84 , H01L27/10852 , H01L27/10876 , H01L27/10885 , H01L28/86 , H01L28/90
摘要： A first capacitor electrode of the capacitor, which is arranged on a surface of a substrate (1), has a lower part (T) and a lateral part (S) arranged thereon. At least a first lateral area of the lateral part (S) is undulatory in such a way that it has bulges and indentations alternately which are formed along lines each running in a plane parallel to the surface of the substrate (1). The lateral part (T) can be produced by depositing conductive material in a depression (V) which is produced in a layer sequence whose layers are composed alternately of a first material and a second material and in which the first material is subjected to wet etching selectively with respect to the second material down to a first depth. The first capacitor electrode is provided with a capacitor dielectric (KD). A second capacitor electrode (P) adjoins the capacitor dielectric (KD).
摘要翻译：设置在基板（1）的表面上的电容器的第一电容电极具有布置在其上的下部（T）和侧部（S）。横向部分（S）的至少第一横向区域以这样的方式波动，使得其具有沿着平行于基底（1）的表面的平面中的每条线条沿着线形成的凸起和凹陷。横向部分（T）可以通过将导电材料沉积在层中产生的凹陷（V）中来制造，层的顺序是层，其层由第一材料和第二材料交替组成，并且其中第一材料经受湿蚀刻相对于第二材料选择性地到达第一深度。第一电容器电极设置有电容器电介质（KD）。第二电容器电极（P）与电容器电介质（KD）相邻。

63. 发明授权

US06222753B1 SRAM cell arrangement and method for manufacturing same 有权
标题翻译： SRAM单元布置及其制造方法
公开(公告)号：US06222753B1
公开(公告)日：2001-04-24
申请号：US09446419
申请日：1999-12-20
申请人： Bernd Goebel , Emmerich Bertagnolli , Josef Willer , Barbara Hasler , Paul-Werner von Basse
发明人： Bernd Goebel , Emmerich Bertagnolli , Josef Willer , Barbara Hasler , Paul-Werner von Basse
IPC分类号： G11C700
CPC分类号： H01L27/11 , H01L27/1104
摘要： An SRAM cell arrangement which includes six MOS transistors per memory cell wherein each transistor is formed as a vertical transistors. The MOS transistors are arranged at sidewalls of trenches. Parts of the memory cell such as, for example, gate electrodes or conductive structures fashioned as spacers are contacted via adjacent, horizontal, conductive structures arranged above a surface of a substrate. Connections between parts of memory cells occur via third conductive structures arranged at the sidewalls of the depressions and word lines via diffusion regions that are adjacent to the sidewalls of the depressions within the substrate, via first bit lines, via second bit lines and/or via conductive structures that are partially arranged at different heights with respect to an axis perpendicular to the surface. Contacts contact a plurality of parts of the MOS transistors simultaneously.
摘要翻译：每个存储单元包括六个MOS晶体管的SRAM单元布置，其中每个晶体管形成为垂直晶体管。 MOS晶体管布置在沟槽的侧壁。存储单元的部分，例如栅极电极或形成为间隔物的导电结构，经由布置在衬底表面上方的相邻的水平导电结构接触。存储器单元的部分之间的连接通过布置在凹陷和字线的侧壁处的第三导电结构经由第一位线经由第二位线和/或通孔的扩散区域经由衬底内的凹陷的侧壁相邻布置相对于垂直于表面的轴部分地布置在不同高度的导电结构。触头同时接触MOS晶体管的多个部分。

64. 发明授权

US6040995A Method of operating a storage cell arrangement 失效
标题翻译：操作存储单元布置的方法
公开(公告)号：US6040995A
公开(公告)日：2000-03-21
申请号：US230614
申请日：1999-01-28
申请人： Hans Reisinger , Ulrike Gruning , Hermann Wendt , Reinhard Stengl , Volker Lehmann , Josef Willer , Martin Franosch , Herbert Schafer , Wolfgang Krautschneider , Franz Hofmann , Thomas Bohm
发明人： Hans Reisinger , Ulrike Gruning , Hermann Wendt , Reinhard Stengl , Volker Lehmann , Josef Willer , Martin Franosch , Herbert Schafer , Wolfgang Krautschneider , Franz Hofmann , Thomas Bohm
IPC分类号： H01L21/8247 , H01L29/51 , H01L29/788 , H01L29/792 , H01L27/02
CPC分类号： H01L29/513 , H01L29/518 , H01L29/792
摘要： For the operation of a memory cell arrangement with MOS transistors as memory cells that comprise a dielectric triple layer (5) with a first silicon oxide layer (51), a silicon nitride layer (52) and a second silicon oxide layer (53) as gate dielectric, whereby the silicon oxide layers are respectively at least 3 nm thick, a first cutoff voltage value is allocated to a first logical value and a second cutoff voltage value of the MOS transistor is allocated to a second logical value for storing digital data. The information stored in the memory cell can be modified by applying corresponding voltage levels, although a complete removal of charge stored in the silicon nitride layer is not possible because of the thickness of the silicon oxide layers. What is exploited when modifying the cutoff voltage is that the electrical field in the dielectric triple layer is distorted by charge stored in the silicon nitride layer.
摘要翻译： PCT No.PCT / DE97 / 01601 Sec。 371日期1999年1月28日 102（e）1999年1月28日PCT PCT 1997年7月29日PCT公布。出版物WO98 / 06140 日期1998年2月12日对于具有MOS晶体管的存储单元布置的操作，作为包含具有第一氧化硅层（51）的介电三层（5）的存储单元，具有氮化硅层（52）和第二氧化硅层（53）作为栅极电介质，由此氧化硅层分别为至少3nm厚，将第一截止电压值分配给第一逻辑值，并将MOS晶体管的第二截止电压值分配给第二逻辑值用于存储数字数据。存储在存储单元中的信息可以通过施加相应的电压电平来修改，尽管由于氧化硅层的厚度，不可能完全去除存储在氮化硅层中的电荷。当修改截止电压时，利用的是电介质三层中的电场由存储在氮化硅层中的电荷而失真。

65. 发明授权

US6033534A Method for producing an Al-containing layer with a planar surface on a substrate having hole structures with a high aspect ratio in the surface 失效
标题翻译：在具有在表面上具有高纵横比的孔结构的基板上制造具有平坦表面的含Al层的方法
公开(公告)号：US6033534A
公开(公告)日：2000-03-07
申请号：US54200
申请日：1993-04-30
申请人： Josef Willer , Hermann Wendt , Volker Lehmann
发明人： Josef Willer , Hermann Wendt , Volker Lehmann
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/334 , C23C14/34
CPC分类号： H01L29/66181 , H01L21/28512
摘要： A method for producing an Al-containing layer having a planar surface onto a substrate having hole structures with high aspect ratios formed in the surface of the substrate, wherein the Al-containing layer is applied in a sputtering process during which the substrate is held at an elevated temperature and the sputtering process is implemented at a pressure between 1.3.times.10.sup.-2 Pa and 13 Pa and at a low partial gas pressure. The substrate can be held at a temperature between approximately 400.degree. C. and 500.degree. C. during the sputtering process. A partial residual gas pressure of less than 1.3.times.10.sup.-5 PA can prevail in the vacuum. An intermediate layer of pure titanium and a barrier layer of TiN can be directly deposited onto the substrate and the Al-containing layer can then be applied onto this intermediate end barrier layer.
摘要翻译：一种在基板的表面形成具有高纵横比的孔结构的基板上的具有平坦表面的含Al层的方法，其中所述含Al层以基板保持在其中的溅射工艺升高的温度和溅射过程在1.3×10 -2 Pa至13 Pa之间的压力下和在低的部分气体压力下实施。在溅射过程中，衬底可保持在约400℃至500℃的温度。小于1.3×10-5PA的部分残余气体压力可以在真空中占优势。可以将纯钛的中间层和TiN的阻挡层直接沉积到衬底上，然后将含Al层施加到该中间阻挡层上。

66. 发明授权

US5882969A Method for manufacturing an electrically writeable and erasable read-only memory cell arrangement 失效
标题翻译：用于制造电可写和可擦除的只读存储单元布置的方法
公开(公告)号：US5882969A
公开(公告)日：1999-03-16
申请号：US967419
申请日：1997-11-11
申请人： Wolfgang Krautschneider , Franz Hofmann , Hans Reisinger , Josef Willer
发明人： Wolfgang Krautschneider , Franz Hofmann , Hans Reisinger , Josef Willer
IPC分类号： H01L21/822 , H01L21/8247 , H01L29/788 , H01L29/792 , H01L21/336 , H01L29/78
CPC分类号： H01L27/11521 , H01L21/8221 , H01L27/11551
摘要： In a method for manufacturing an electrically writeable and erasable ad-only memory cell arrangement, by self-adjusting process steps, a read-only memory cell arrangement having memory cells that respectively comprise an MOS transistor with a floating gate is manufactured. The MOS transistors are arranged in rows that run parallel. Adjacent rows thus respectively run alternately on the bottom of longitudinal trenches and between adjacent longitudinal trenches. The control gates laterally surround the floating gates so that the memory cells on the bottom of the longitudinal trenches also comprise a coupling ratio>1. A surface requirement per memory cell of 2F.sup.2 (F minimum structural size) is achieved.
摘要翻译：在通过自调整处理步骤制造电可写和可擦除的仅ad的存储单元布置的方法中，制造了具有分别包括具有浮置栅极的MOS晶体管的存储单元的只读存储单元布置。 MOS晶体管排列成并行的行。因此，相邻的行分别在纵向沟槽的底部和相邻的纵向沟槽之间交替地行进。控制门横向围绕浮动栅极，使得纵向沟槽底部的存储单元也包括耦合比> 1。实现2F2（F最小结构尺寸）每个存储单元的表面要求。

67. 发明授权

US5306647A Method for manufacturing a solar cell from a substrate wafer 失效
标题翻译：从基板晶片制造太阳能电池的方法
公开(公告)号：US5306647A
公开(公告)日：1994-04-26
申请号：US998611
申请日：1992-12-30
申请人： Volker Lehmann , Reinhard Stengl , Hermann Wendt , Wolfgang Hoenlein , Josef Willer
发明人： Volker Lehmann , Reinhard Stengl , Hermann Wendt , Wolfgang Hoenlein , Josef Willer
IPC分类号： C25F3/12 , H01L21/3063 , H01L31/0352 , H01L31/047 , H01L31/18
CPC分类号： H01L31/1804 , H01L21/3063 , H01L31/03529 , H01L31/047 , Y02E10/547 , Y02P70/521
摘要： A self-supporting layer of n-doped monocrystalline silicon is stripped from a substrate wafer of n-doped, monocrystalline silicon by electrochemical etching for manufacturing a solar cell. Holes are formed in the substrate wafer by electrochemical etching, particularly in a fluoride-containing, acidic electrolyte wherein the substrate wafer is connected as an anode. When a depth of the holes that essentially corresponds to the thickness of the self-supporting layer is reached, the process parameters of the etching are modified such that the self-supporting layer is stripped as a consequence of the holes growing together. The solar cell is manufactured from the self-supporting layer, and the method can be applied repeatedly on the same substrate wafer for stripping a plurality of self-supporting layers.
摘要翻译：通过用于制造太阳能电池的电化学蚀刻，从n掺杂的单晶硅的衬底晶片剥离n掺杂单晶硅的自支撑层。通过电化学蚀刻，特别是在其中衬底晶片作为阳极连接的含氟化物的酸性电解质中，在衬底晶片中形成孔。当达到基本上对应于自支撑层的厚度的孔的深度时，蚀刻的工艺参数被修改，使得自支撑层由于孔一起生长而被剥离。该太阳能电池由自支撑层制造，并且可以在相同的基板晶片上重复地施加该方法以剥离多个自支撑层。

68. 发明授权

US07940575B2 Memory device and method providing logic connections for data transfer 有权
标题翻译：提供用于数据传输的逻辑连接的存储器件和方法
公开(公告)号：US07940575B2
公开(公告)日：2011-05-10
申请号：US12058191
申请日：2008-03-28
申请人： Roberto Ravasio , Andreas Kux , Detlev Richter , Girolamo Gallo , Josef Willer , Ramirez Xavier Veredas
发明人： Roberto Ravasio , Andreas Kux , Detlev Richter , Girolamo Gallo , Josef Willer , Ramirez Xavier Veredas
IPC分类号： G11C7/10 , G11C8/12 , G11C16/06
CPC分类号： G06F13/385 , Y02D10/14 , Y02D10/151
摘要： In an embodiment, a method for transferring data in a memory device is provided. The method may include transferring data from a first memory cell arrangement including a plurality of memory cells to a second memory cell arrangement including a plurality of memory cells via a connecting circuit arrangement coupled to the plurality of memory cell arrangements and providing a plurality of controllable connections via a plurality of connecting circuit terminals, the memory cell arrangements being connected with at least one connecting circuit terminal of the plurality of connecting circuit terminals, wherein the connecting circuit is configured to provide arbitrarily controllable signal flow connections between the plurality of connecting circuit terminals. The data are transferred via a logic connection using the controllable connections. Simultaneously, a further logic connection may be provided to a memory cell arrangement of the memory cell arrangements using the controllable connections.
摘要翻译：在一个实施例中，提供了一种用于在存储器件中传送数据的方法。该方法可以包括经由耦合到多个存储器单元布置的连接电路装置将数据从包括多个存储单元的第一存储单元布置传送到包括多个存储单元的第二存储单元布置，并提供多个可控制的连接通过多个连接电路端子，所述存储单元布置与所述多个连接电路端子中的至少一个连接电路端子连接，其中所述连接电路被配置为在所述多个连接电路端子之间提供任意可控的信号流连接。数据通过使用可控连接的逻辑连接进行传输。同时，可以使用可控制连接将另外的逻辑连接提供给存储器单元布置。

69. 发明授权

US07767567B2 Method of forming a semiconductor memory device and semiconductor memory device 有权
标题翻译：形成半导体存储器件和半导体存储器件的方法
公开(公告)号：US07767567B2
公开(公告)日：2010-08-03
申请号：US11541404
申请日：2006-09-29
申请人： Josef Willer , Franz Hofmann
发明人： Josef Willer , Franz Hofmann
IPC分类号： H01L21/3205
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： Gate stacks of an array of memory cells and a plurality of select transistors are formed above a carrier, the gate stacks being separated by spacers. An opening is formed between the spacers in an area that is provided for a source line. A sacrificial layer is applied to fill the opening and is subsequently patterned. Interspaces are filled with a planarizing layer of dielectric material. The residues of the sacrificial layer are removed and an electrically conductive material is applied to form a source line.
摘要翻译：存储器单元阵列和多个选择晶体管的栅极堆叠形成在载体上方，栅极堆叠被间隔物隔开。在为源极线提供的区域中的间隔件之间形成开口。施加牺牲层以填充开口并且随后被图案化。间隙填充有介电材料的平坦化层。去除牺牲层的残余物并施加导电材料以形成源极线。

70. 发明申请

US20090244949A1 Memory Device and Method Providing Logic Connections for Data Transfer 有权
标题翻译：为数据传输提供逻辑连接的存储器件和方法
公开(公告)号：US20090244949A1
公开(公告)日：2009-10-01
申请号：US12058191
申请日：2008-03-28
申请人： Roberto Ravasio , Andreas Kux , Detlev Richter , Girolamo Gallo , Josef Willer , Ramirez Xavier Veredas
发明人： Roberto Ravasio , Andreas Kux , Detlev Richter , Girolamo Gallo , Josef Willer , Ramirez Xavier Veredas
IPC分类号： G11C5/06
CPC分类号： G06F13/385 , Y02D10/14 , Y02D10/151
摘要： In an embodiment, a method for transferring data in a memory device is provided. The method may include transferring data from a first memory cell arrangement including a plurality of memory cells to a second memory cell arrangement including a plurality of memory cells via a connecting circuit arrangement coupled to the plurality of memory cell arrangements and providing a plurality of controllable connections via a plurality of connecting circuit terminals, the memory cell arrangements being connected with at least one connecting circuit terminal of the plurality of connecting circuit terminals, wherein the connecting circuit is configured to provide arbitrarily controllable signal flow connections between the plurality of connecting circuit terminals. The data are transferred via a logic connection using the controllable connections. Simultaneously, a further logic connection may be provided to a memory cell arrangement of the memory cell arrangements using the controllable connections.
摘要翻译：在一个实施例中，提供了一种用于在存储器件中传送数据的方法。该方法可以包括经由耦合到多个存储器单元布置的连接电路装置将数据从包括多个存储单元的第一存储单元布置传送到包括多个存储单元的第二存储单元布置，并提供多个可控制的连接通过多个连接电路端子，所述存储单元布置与所述多个连接电路端子中的至少一个连接电路端子连接，其中所述连接电路被配置为在所述多个连接电路端子之间提供任意可控的信号流连接。数据通过使用可控连接的逻辑连接进行传输。同时，可以使用可控制连接将另外的逻辑连接提供给存储器单元布置。

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