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61. 发明授权

US07855670B2 A-to-D converter 有权
公开(公告)号：US07855670B2
公开(公告)日：2010-12-21
申请号：US12749277
申请日：2010-03-29
申请人： Shiro Dosho , Takashi Morie , Kazuo Matsukawa
发明人： Shiro Dosho , Takashi Morie , Kazuo Matsukawa
IPC分类号： H03M1/66
CPC分类号： H03M1/46 , H03M1/1215 , H03M1/14 , H03M1/667 , H03M1/682
摘要： A successive approximation type A-to-D converter includes a cyclic D-to-A converter (11), a comparator (12) for comparing an analog value with an output value of the D-to-A converter (11), and memory means (13) for sequentially storing an output value of the comparator (12) and supplying the stored value to the D-to-A converter (11) in a reverse order.

62. 发明授权

US07808307B2 Reference current circuit, reference voltage circuit, and startup circuit 有权
标题翻译：参考电流电路，参考电压电路和启动电路
公开(公告)号：US07808307B2
公开(公告)日：2010-10-05
申请号：US12093393
申请日：2007-09-04
申请人： Shiro Sakiyama , Akinori Matsumoto , Takashi Morie , Masayoshi Kinoshita
发明人： Shiro Sakiyama , Akinori Matsumoto , Takashi Morie , Masayoshi Kinoshita
IPC分类号： G05F1/10
CPC分类号： G05F3/262
摘要： A current mirror circuit 10 is formed to have a current ratio (a transistor size ratio) of 1:m. As well, respective pairs of nMOS transistors MN1, MN3 and nMOS transistors MN2, MN4 are formed to have a current ratio of 1:m. Two currents output from the current mirror circuit 10 are each distributed to two. The distributed currents flowing in the nMOS transistors MN2, MN4 are added and are then allowed to flow into one resistor R2. Hence, for the resistor R2, only one resistor in which current of double flows suffices when m=1, for example. This effortlessly reduces the necessary resistance to one fourth.
摘要翻译：电流镜电路10形成为具有1：m的电流比（晶体管尺寸比）。同样，各对nMOS晶体管MN1，MN3和nMOS晶体管MN2，MN4形成为具有1：m的电流比。从电流镜电路10输出的两个电流分别分配给两个。在nMOS晶体管MN2，MN4中流动的分布电流相加，然后被允许流入一个电阻器R2。因此，对于电阻器R2，例如当m = 1时，只有一个双电流的电流就足够了。这轻而易举地减少了四分之一的必要阻力。

63. 发明授权

US07808295B2 Multiphase level shift system 有权
标题翻译：多相电平转换系统
公开(公告)号：US07808295B2
公开(公告)日：2010-10-05
申请号：US12296021
申请日：2007-06-15
申请人： Shiro Sakiyama , Akinori Matsumoto , Takashi Morie , Shiro Dosho , Yusuke Tokunaga
发明人： Shiro Sakiyama , Akinori Matsumoto , Takashi Morie , Shiro Dosho , Yusuke Tokunaga
IPC分类号： H03L5/00 , H03F3/66
CPC分类号： H03K19/01855 , H03K3/0315 , H03K3/354
摘要： Each of n level shifters (LS0 to LS7) includes an NMOS transistor (Mn1) for receiving any one of n clock signals (P0 to P7) and a PMOS transistor (Mp1) for receiving an output signal from another level shifter. An output signal given to the PMOS transistor (Mp1) included in each of the level shifters (LS0 to LS7) is an output signal of the level shifter which receives the clock signal whose phase delay amount with respect to the clock signal given to the NMOS transistor (Mn1) included in that level shifter is a phase amount X (0°
摘要翻译： n个电平移位器（LS0〜LS7）中的每一个包括用于接收n个时钟信号（P0〜P7）中的任何一个的NMOS晶体管（Mn1）和用于接收来自另一个电平移位器的输出信号的PMOS晶体管（Mp1）。给予每个电平移位器（LS0至LS7）中的PMOS晶体管（Mp1）的输出信号是电平移位器的输出信号，其接收相对于给予NMOS的时钟信号的相位延迟量的时钟信号包括在该电平移位器中的晶体管（Mn1）是相位量X（0°

64. 发明授权

US07667448B2 Reference voltage generation circuit 有权
标题翻译：参考电压发生电路
公开(公告)号：US07667448B2
公开(公告)日：2010-02-23
申请号：US11783800
申请日：2007-04-12
申请人： Akinori Matsumoto , Shiro Sakiyama , Takashi Morie
发明人： Akinori Matsumoto , Shiro Sakiyama , Takashi Morie
IPC分类号： G05F3/04
CPC分类号： G05F3/30
摘要： A reference voltage generation circuit of the present invention includes: a band gap reference-type current generation circuit for controlling each of currents flowing through a first current path and a second current path, which are extending from a first node to a second node, to be a predetermined reference current, by utilizing a voltage difference occurring between a pair of transistors or diodes; and a resistive load circuit provided between the second node and a third node.
摘要翻译：本发明的参考电压产生电路包括：带隙基准电流产生电路，用于控制从第一节点延伸到第二节点的流过第一电流路径和第二电流路径的每个电流到通过利用在一对晶体管或二极管之间出现的电压差来作为预定的参考电流; 以及设置在第二节点和第三节点之间的电阻性负载电路。

65. 发明申请

US20090134931A1 MULTIPHASE LEVEL SHIFT SYSTEM 有权
标题翻译：多级水平移位系统
公开(公告)号：US20090134931A1
公开(公告)日：2009-05-28
申请号：US12296021
申请日：2007-06-15
申请人： Shiro Sakiyama , Akinori Matsumoto , Takashi Morie , Shiro Dosho , Yusuke Tokunaga
发明人： Shiro Sakiyama , Akinori Matsumoto , Takashi Morie , Shiro Dosho , Yusuke Tokunaga
IPC分类号： H03L5/00
CPC分类号： H03K19/01855 , H03K3/0315 , H03K3/354
摘要： Each of n level shifters (LS0 to LS7) includes an NMOS transistor (Mn1) for receiving any one of n clock signals (P0 to P7) and a PMOS transistor (Mp1) for receiving an output signal from another level shifter. An output signal given to the PMOS transistor (Mp1) included in each of the level shifters (LS0 to LS7) is an output signal of the level shifter which receives the clock signal whose phase delay amount with respect to the clock signal given to the NMOS transistor (Mn1) included in that level shifter is a phase amount X (0°
摘要翻译： n个电平移位器（LS0〜LS7）中的每一个包括用于接收n个时钟信号（P0〜P7）中的任何一个的NMOS晶体管（Mn1）和用于接收来自另一个电平移位器的输出信号的PMOS晶体管（Mp1）。给予每个电平移位器（LS0至LS7）中的PMOS晶体管（Mp1）的输出信号是电平移位器的输出信号，其接收相对于给予NMOS的时钟信号的相位延迟量的时钟信号包括在该电平移位器中的晶体管（Mn1）是相位量X（0°

66. 发明申请

US20090040089A1 A-TO-D CONVERTER 有权
标题翻译： A转To转换器
公开(公告)号：US20090040089A1
公开(公告)日：2009-02-12
申请号：US12162930
申请日：2007-11-30
申请人： Shiro Dosho , Takashi Morie , Kazuo Matsukawa
发明人： Shiro Dosho , Takashi Morie , Kazuo Matsukawa
IPC分类号： H03M1/38
CPC分类号： H03M1/46 , H03M1/1215 , H03M1/14 , H03M1/667 , H03M1/682
摘要： A successive approximation type A-to-D converter includes a cyclic D-to-A converter (11), a comparator (12) for comparing an analog value with an output value of the D-to-A converter (11), and memory means (13) for sequentially storing an output value of the comparator (12) and supplying the stored value to the D-to-A converter (11) in a reverse order.
摘要翻译：逐次逼近型A到D转换器包括循环D转换器（A），用于将模拟值与D转换器（11）的输出值进行比较的比较器（12），以及存储装置（13），用于顺序地存储比较器（12）的输出值，并以相反的顺序将存储的值提供给D-A转换器（11）。

67. 发明授权

US07477099B2 Filter adjustment circuit 有权
标题翻译：滤波器调节电路
公开(公告)号：US07477099B2
公开(公告)日：2009-01-13
申请号：US11792081
申请日：2005-09-02
申请人： Kouji Okamoto , Takashi Morie , Shiro Dosho , Hirokuni Fujiyama
发明人： Kouji Okamoto , Takashi Morie , Shiro Dosho , Hirokuni Fujiyama
IPC分类号： H03B1/00
CPC分类号： H03G5/16 , H03H11/1291 , H03H11/20
摘要： In a filter adjustment circuit for an analog filter circuit such as a Gm-C filter, an input signal IS from a reference signal generation circuit 1 is inputted to a Gm-C filter 2 to be filtered and then converted by a conversion circuit 3 to a digital signal. A reference signal RS from the reference signal generation circuit 1 is converted by a conversion circuit 4 to a digital signal. The two converted signals are held in time series in a holding circuit 5. A timing generation circuit 6 generates an update timing signal en based on a reference time-series signal ref from the holding circuit 5. A control signal generation circuit 7 generates a control signal CS based on the reference time-series signal ref and a filter output time-series signal tgt, each from the holding circuit 5. The control signal CS is inputted to the Gm-C filter 2 in response to the update timing signal en to adjust the gain of the Gm-C filter 2. As a result, variations in the response characteristics of the Gm-C filter 2 are adjusted with high accuracy with a simple circuit structure.
摘要翻译：在用于诸如Gm-C滤波器的模拟滤波器电路的滤波器调节电路中，来自参考信号产生电路1的输入信号IS被输入到要过滤的Gm-C滤波器2，然后由转换电路3转换成数字信号。来自参考信号发生电路1的参考信号RS由转换电路4转换成数字信号。两个转换信号在保持电路5中保持时间序列。定时产生电路6基于来自保持电路5的基准时间序列信号ref产生更新定时信号en。控制信号产生电路7产生控制基于参考时间序列信号ref的信号CS和来自保持电路5的滤波器输出时间序列信号tgt。控制信号CS响应于更新定时信号en至...而被输入到Gm-C滤波器2 调整Gm-C滤波器2的增益。结果，以简单的电路结构，高精度地调整Gm-C滤波器2的响应特性的变化。

68. 发明申请

US20080218255A1 Filter Characteristic Adjusting Apparatus and Filter Characteristic Adjusting Method 有权
标题翻译：过滤特性调节装置和过滤器特性调整方法
公开(公告)号：US20080218255A1
公开(公告)日：2008-09-11
申请号：US11792946
申请日：2005-11-29
申请人： Hirokuni Fujiyama , Takashi Morie , Hiroya Ueno
发明人： Hirokuni Fujiyama , Takashi Morie , Hiroya Ueno
IPC分类号： H03K5/00
CPC分类号： H03H11/08 , H03H11/1291
摘要： There is provided a filter characteristic adjusting apparatus and a filter characteristic adjusting method which can avoid an increase in circuit scale of the filter characteristic adjusting apparatus, and can speedily adjust a characteristic frequency of the filter to a desired frequency. When performing characteristic adjustment for the filter, the test signal generation unit (31) generates a test signal (s14) which is a pulse signal having the same frequency as the characteristic frequency of the filter (10) on the basis of a reference signal (s17), and a phase-shifted test signal (s14′) that is obtained by shifting the phase of the test signal (s14) by a predetermined amount with a phase shift unit (32) in a control signal generation unit (33) is compared with a filter output signal (s16) that is obtained by inputting the test signal (s14) into the filter (10) to obtain a phase difference between the signals, and then the phase difference is subjected to a binary search to generate a control signal (s11).
摘要翻译：提供一种滤波特性调节装置和滤波器特性调整方法，其可以避免滤波器特性调节装置的电路规模的增加，并且可以将滤波器的特征频率快速调整到期望的频率。当对滤波器进行特性调整时，测试信号生成单元（31）基于参考信号产生作为与滤波器（10）的特征频率相同频率的脉冲信号的测试信号（s 14）（s 17）和通过在控制信号生成单元（32）中用相移单元（32）将测试信号（s 14）的相位移位预定量而获得的相移测试信号（s 14'）（33）与通过将测试信号（s 14）输入到滤波器（10）中以获得信号之间的相位差而获得的滤波器输出信号（s 16）进行比较，然后将相位差进行二进制搜索以产生控制信号（s 11）。

69. 发明授权

US07215623B2 Reproduction signal processing apparatus 有权
标题翻译：再生信号处理装置
公开(公告)号：US07215623B2
公开(公告)日：2007-05-08
申请号：US10704691
申请日：2003-11-12
申请人： Hiroyuki Nakahira , Takashi Morie
发明人： Hiroyuki Nakahira , Takashi Morie
IPC分类号： G11B7/05
CPC分类号： G11B20/10009 , G11B20/10046 , G11B2020/10981
摘要： An analog filter is placed at a stage previous to an analog-digital converter (ADC), and a waveform equalizer is placed at a stage subsequent to the ADC. The sampling frequency of the ADC is determined by a clock generation section according to the relationship between the bit rate of an input reproduction signal and the characteristic of the analog filter. The number of taps is changed according to the relationship between the bit rate of the input reproduction signal and the characteristic of the analog filter. Further, the tap coefficients of a waveform equalizer are changed according to the height of the frequency band of the input reproduction signal. A waveform evaluation section generates a signal that evaluates a waveform equalization signal transmitted from the waveform equalizer to a Viterbi decoder, whereby adaptive waveform equalization is realized.
摘要翻译：模拟滤波器放置在模拟数字转换器（ADC）之前的阶段，波形均衡器放置在ADC后的阶段。根据输入再现信号的比特率与模拟滤波器的特性之间的关系，由时钟产生部分确定ADC的采样频率。抽头数根据输入再现信号的比特率与模拟滤波器的特性之间的关系而改变。此外，波形均衡器的抽头系数根据输入再现信号的频带的高度而改变。波形评估部分生成评估从波形均衡器发送到维特比解码器的波形均衡信号的信号，从而实现自适应波形均衡。

70. 发明申请

US20060088136A1 Complex filter circuit and receiver circuit 失效
公开(公告)号：US20060088136A1
公开(公告)日：2006-04-27
申请号：US11247136
申请日：2005-10-12
申请人： Takashi Morie , Hiroya Ueno , Hirokuni Fujiyama , Joji Hayashi , Akinori Matsumoto , Katsumasa Hijikata
发明人： Takashi Morie , Hiroya Ueno , Hirokuni Fujiyama , Joji Hayashi , Akinori Matsumoto , Katsumasa Hijikata
IPC分类号： H04B1/10
CPC分类号： H04B1/123 , H04B1/30
摘要： A pseudo-image signal producing section produces a pseudo-image signal imitating an actual image signal. An amplitude detection section detects the amplitude of the pseudo-image signal having passed through a complex filter circuit. A filter control section controls an element value control section in the complex filter circuit so as to decrease the detected amplitude. The element value control section performs an element value adjustment so that absolute element values of a pair of elements corresponding to each other in two filter circuits in the complex filter circuit increase/decrease in opposite directions.

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