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61. 发明授权

US07492644B2 Semiconductor integrated circuit device 有权
公开(公告)号：US07492644B2
公开(公告)日：2009-02-17
申请号：US11832727
申请日：2007-08-02
申请人： Riichiro Takemura , Takeshi Sakata , Norikatsu Takaura , Kazuhiko Kajigaya
发明人： Riichiro Takemura , Takeshi Sakata , Norikatsu Takaura , Kazuhiko Kajigaya
IPC分类号： G11C7/00
CPC分类号： G11C13/0069 , G11C7/1078 , G11C7/1087 , G11C7/1096 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/004 , G11C2213/79
摘要： There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.

62. 发明授权

US07388768B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07388768B2
公开(公告)日：2008-06-17
申请号：US11354131
申请日：2006-02-15
申请人： Satoru Hanzawa , Riichiro Takemura , Kazuhiko Kajigaya
发明人： Satoru Hanzawa , Riichiro Takemura , Kazuhiko Kajigaya
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C15/043
摘要： Control clocks of different phases are distributed to a memory array divided into multiple banks, and processing of entries and search keys (read and write operations and search operation) is performed at different phases. The memory array divided into banks is further divided into smaller arrays, that is, sub-arrays, and a sense amplifier in a read-write-search circuit block is shared by the two sub-arrays. In this case, a so-called open bit line structure in which each one bit line is connected from both sub-arrays to a sense amplifier is adopted. The same look-up table is registered to multiple banks, successively inputted search keys are sequentially inputted to the multiple banks, and the search operation is carried out in synchronization with the control clocks of different phases.
摘要翻译：将不同相位的控制时钟分配到划分为多个存储体的存储器阵列，并且在不同阶段执行条目和搜索关键字的处理（读取和写入操作和搜索操作）。划分为存储体的存储器阵列进一步分成较小的阵列，即子阵列，并且读写搜索电路块中的读出放大器由两个子阵列共享。在这种情况下，采用所谓的开放位线结构，其中每个位线都从两个子阵列连接到读出放大器。相同的查找表被注册到多个存储体，连续输入的搜索键被顺序地输入到多个存储体，并且与不同相位的控制时钟同步地执行搜索操作。

63. 发明申请

US20070274144A1 Semiconductor Integrated Circuit Device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US20070274144A1
公开(公告)日：2007-11-29
申请号：US10579911
申请日：2003-11-21
申请人： Satoru Hanzawa , Junji Shigeta , Shinichiro Kimura , Takeshi Sakata , Riichiro Takemura , Kazuhiko Kajigaya
发明人： Satoru Hanzawa , Junji Shigeta , Shinichiro Kimura , Takeshi Sakata , Riichiro Takemura , Kazuhiko Kajigaya
IPC分类号： G11C7/00
CPC分类号： G11C15/04 , G11C15/043
摘要： In a memory array structured of memory cells using a storage circuit STC and a comparator CP, either one electrode of a source electrode or a drain electrode of a transistor, whose gate electrode is connected to a search line, of a plurality of transistors structuring the comparator CP is connected to a match line HMLr precharged to a high voltage. Further, a match detector MDr is arranged on a match line LMLr precharged to a low voltage to discriminate a comparison signal voltage generated at the match line according to the comparison result of data. According to such memory array structure and operation, comparison operation can be performed at low power and at high speed while influence of search-line noise is avoided in a match line pair. Therefore, a low power content addressable memory which allows search operation at high speed can be realized.
摘要翻译：在使用存储电路STC和比较器CP的存储器单元构成的存储器阵列中，将栅电极连接到搜索线的晶体管的源电极或漏电极的一个电极，构成比较器CP连接到预充电到高电压的匹配线HMLr。此外，匹配检测器MDr布置在预充电到低电压的匹配线LMLr上，以根据数据的比较结果来识别在匹配线处产生的比较信号电压。根据这种存储器阵列结构和操作，可以在低功率和高速度下执行比较操作，同时在匹配线对中避免搜索线噪声的影响。因此，可以实现允许高速搜索操作的低功率内容可寻址存储器。

64. 发明授权

US07257034B2 Semiconductor integrated circuit device 有权
公开(公告)号：US07257034B2
公开(公告)日：2007-08-14
申请号：US11598702
申请日：2006-11-14
申请人： Riichiro Takemura , Takeshi Sakata , Norikatsu Takaura , Kazuhiko Kajigaya
发明人： Riichiro Takemura , Takeshi Sakata , Norikatsu Takaura , Kazuhiko Kajigaya
IPC分类号： G11C11/34
CPC分类号： G11C13/0069 , G11C7/1078 , G11C7/1087 , G11C7/1096 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/004 , G11C2213/79
摘要： There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.

65. 发明申请

US20110134678A1 Semiconductor device having hierarchical structured bit line 失效
标题翻译：具有分层结构位线的半导体器件
公开(公告)号：US20110134678A1
公开(公告)日：2011-06-09
申请号：US12926693
申请日：2010-12-03
申请人： Takenori Sato , Kazuhiko Kajigaya , Yoshimitsu Yanagawa , Tomonori Sekiguchi , Akira Kotabe , Satoru Akiyama
发明人： Takenori Sato , Kazuhiko Kajigaya , Yoshimitsu Yanagawa , Tomonori Sekiguchi , Akira Kotabe , Satoru Akiyama
IPC分类号： G11C5/06
CPC分类号： G11C5/06 , G11C7/08 , G11C11/4091 , G11C11/4097 , H01L27/10876 , H01L27/10885
摘要： A sense operation with respect to simultaneously-accessed two memory cells is performed by time division by using two sense amplifiers, and thereafter restore operations are performed simultaneously. With this arrangement, it is not necessary to provide switches in the middle of global bit lines, and no problem occurs when performing the restore operation by time division. Further, because a parasitic CR model of a first sense amplifier and that of a second sense amplifier become mutually the same, high sensitivity can be maintained.
摘要翻译：通过使用两个读出放大器进行时分执行相对于同时访问的两个存储单元的检测操作，然后同时执行恢复操作。通过这种布置，不需要在全局位线的中间设置开关，并且在通过时分执行恢复操作时不会发生问题。此外，由于第一读出放大器和第二读出放大器的寄生CR模型相互相同，因此可以保持高灵敏度。

66. 发明申请

US20060142988A1 Design methodology and manufacturing method for semiconductor memory 审中-公开
标题翻译：半导体存储器的设计方法和制造方法
公开(公告)号：US20060142988A1
公开(公告)日：2006-06-29
申请号：US11318431
申请日：2005-12-28
申请人： Satoru Akiyama , Tomonori Sekiguchi , Takayuki Kawahara , Kazuhiko Kajigaya
发明人： Satoru Akiyama , Tomonori Sekiguchi , Takayuki Kawahara , Kazuhiko Kajigaya
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F2217/10 , G06F2217/78
摘要： A manufacturing method for semiconductor memory and a semiconductor design device, which can facilitate design and reduce a period of time required for the design, are provided. For example, when a designed memory array is verified, a read-out signal of a memory cell formulated by functions of respective parameters having various distributions is used. A value of the read-out signal is calculated by using a value extracted randomly from the distribution for each kind of parameter. Quality of the memory cell is determined from a calculated result. Calculation of the value of the read-out signal and determination of the quality of the memory cell are carried out to a great number of memory cells the memory array has. The total number of failed bits and the like obtained from these is used as an evaluation criterion.
摘要翻译：提供一种半导体存储器和半导体设计装置的制造方法，其可以促进设计并减少设计所需的时间。例如，当设计的存储器阵列被验证时，使用由具有各种分布的各个参数的功能所制定的存储器单元的读出信号。通过使用从各种参数的分布中随机提取的值来计算读出信号的值。从计算结果确定存储单元的质量。对存储器阵列具有的大量存储单元执行读出信号的值的计算和存储单元的质量的确定。将从这些获得的故障比特等的总数用作评估标准。

67. 发明授权

US06545902B2 Ferroelectric memory device 有权
公开(公告)号：US06545902B2
公开(公告)日：2003-04-08
申请号：US09987590
申请日：2001-11-15
申请人： Takeshi Sakata , Tomonori Sekiguchi , Hiroki Fujisawa , Katsutaka Kimura , Masanori Isoda , Kazuhiko Kajigaya
发明人： Takeshi Sakata , Tomonori Sekiguchi , Hiroki Fujisawa , Katsutaka Kimura , Masanori Isoda , Kazuhiko Kajigaya
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： Since a ferroelectric memory device cannot employ a VCC/2 precharge scheme widely used in DRAM, its array noise and power consumption are large. Further, a ferroelectric capacitor is deteriorated in its characteristics due to its fatigue and imprint. To avoid this, data line pairs are precharged to two voltages VCC and VSS. As a result, a voltage on a data line in a memory cell array MCA varies symmetrically with respect to VCC/2 as its center to thereby reduce the array noise. Further, when early sense and early precharge operations are carried out based on charge sharing between data lines of different precharge voltages, the power consumption can be reduced. Furthermore, when the precharge voltages are switched for respective data lines, reverse and non-reverse polarization are alternately carried out in the ferroelectric capacitor in the memory cell to suppress its fatigue and imprint.

68. 发明授权

US06535451B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US06535451B2
公开(公告)日：2003-03-18
申请号：US09810574
申请日：2001-03-19
申请人： Tomonori Sekiguchi , Kazuhiko Kajigaya
发明人： Tomonori Sekiguchi , Kazuhiko Kajigaya
IPC分类号： G11C700
CPC分类号： G11C11/4091 , G11C7/18 , G11C11/4085 , G11C11/4097
摘要： A plurality of sense amplifier areas are placed alternately with respect to a plurality of memory array areas arranged along a first direction. The plurality of memory array areas are respectively provided with a plurality of bit lines provided along the first direction, a plurality of word lines provided along a second direction intersecting the first direction, and a plurality of memory cells provided in association with portions where the plurality of bit lines and the plurality of word lines intersect. Sense amplifiers are provided, each of which receives therein a pair of signals from each of the bit lines extending to one of the memory array areas on both sides adjacent to the respective sense amplifier areas and each of the bit lines extending to the other thereof. Respective word-line selecting timings or addresses with respect to the two memory array areas spaced away from each other with the two or more memory array areas interposed therebetween are independently set.
摘要翻译：多个读出放大器区域相对于沿着第一方向布置的多个存储器阵列区交替放置。多个存储器阵列区域分别设置有沿着第一方向设置的多个位线，沿着与第一方向相交的第二方向设置的多个字线，以及多个存储单元，其与多个存储单元的位线和多条字线相交。提供了检测放大器，每个放大器在其中接收来自每个位线的一对信号，所述位线延伸到与相应的感测放大器区域相邻的两侧的存储器阵列区域之一，并且每个位线延伸到另一个。独立地设置相对于彼此间隔开的两个或更多个存储器阵列区域彼此间隔的两个存储器阵列区域的相应字线选择定时或地址。

69. 发明授权

US08675419B2 Device including a plurality of memory banks and a pipeline control circuit configured to execute a command on the plurality of memory banks 有权
标题翻译：包括多个存储体的装置和配置成在多个存储体上执行命令的流水线控制电路
公开(公告)号：US08675419B2
公开(公告)日：2014-03-18
申请号：US12929126
申请日：2011-01-03
申请人： Kazuhiko Kajigaya , Tomonori Sekiguchi , Kazuo Ono
发明人： Kazuhiko Kajigaya , Tomonori Sekiguchi , Kazuo Ono
IPC分类号： G11C7/10
CPC分类号： G11C11/409 , G11C5/02 , G11C5/06 , G11C7/1039 , G11C7/18 , G11C11/4076
摘要： A semiconductor device includes a delay buffer, and a pipeline control circuit. The pipeline control circuit controls the delay buffer to hold read data from outputting to a read/write bus for each of banks based on a read command to the each bank while the pipeline control circuit controlling the delay buffer to output write data to the read/write bus, when a next command to the each bank is a write command for the write data. The read/write bus is common to the banks.
摘要翻译：半导体器件包括延迟缓冲器和流水线控制电路。流水线控制电路控制延迟缓冲器，以便基于对每个存储体的读取命令将读出数据保存到每个存储体的读/写总线，同时控制延迟缓冲器的流水线控制电路将写入数据输出到读/ 写入总线时，下一个命令到每个存储区都是写入数据的写入命令。读/写总线是银行常见的。

70. 发明授权

US08605476B2 Semiconductor device having hierarchical structured bit line 失效
标题翻译：具有分层结构位线的半导体器件
公开(公告)号：US08605476B2
公开(公告)日：2013-12-10
申请号：US12926693
申请日：2010-12-03
申请人： Takenori Sato , Kazuhiko Kajigaya , Yoshimitsu Yanagawa , Tomonori Sekiguchi , Akira Kotabe , Satoru Akiyama
发明人： Takenori Sato , Kazuhiko Kajigaya , Yoshimitsu Yanagawa , Tomonori Sekiguchi , Akira Kotabe , Satoru Akiyama
IPC分类号： G11C5/06
CPC分类号： G11C5/06 , G11C7/08 , G11C11/4091 , G11C11/4097 , H01L27/10876 , H01L27/10885
摘要： A sense operation with respect to simultaneously-accessed two memory cells is performed by time division by using two sense amplifiers, and thereafter restore operations are performed simultaneously. With this arrangement, it is not necessary to provide switches in the middle of global bit lines, and no problem occurs when performing the restore operation by time division. Further, because a parasitic CR model of a first sense amplifier and that of a second sense amplifier become mutually the same, high sensitivity can be maintained.
摘要翻译：通过使用两个读出放大器进行时分执行相对于同时访问的两个存储单元的检测操作，然后同时执行恢复操作。通过这种布置，不需要在全局位线的中间设置开关，并且在通过时分执行恢复操作时不会发生问题。此外，由于第一读出放大器和第二读出放大器的寄生CR模型相互相同，因此可以保持高灵敏度。

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