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61. 发明授权

US08653594B2 Double diffused metal oxide semiconductor device and manufacturing method thereof 有权
公开(公告)号：US08653594B2
公开(公告)日：2014-02-18
申请号：US13066622
申请日：2011-04-20
申请人： Ching-Yao Yang , Tsung-Yi Huang , Huan-Ping Chu , Hung-Der Su
发明人： Ching-Yao Yang , Tsung-Yi Huang , Huan-Ping Chu , Hung-Der Su
IPC分类号： H01L29/66
CPC分类号： H01L29/4238 , H01L21/28114 , H01L21/823425 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/086 , H01L29/0865 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/66689 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.

62. 发明申请

US20120181653A1 SEMICONDUCTOR PN JUNCTION STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体PN结结构及其制造方法
公开(公告)号：US20120181653A1
公开(公告)日：2012-07-19
申请号：US13005754
申请日：2011-01-13
申请人： TSUNG-YI HUANG , Hung-Der Su , Kuo-Cheng Chang , Chun-Yi Hung , Kuo-Hsuan Lo , Jeng Gong
发明人： TSUNG-YI HUANG , Hung-Der Su , Kuo-Cheng Chang , Chun-Yi Hung , Kuo-Hsuan Lo , Jeng Gong
IPC分类号： H01L29/06 , H01L21/04
CPC分类号： H01L29/0688 , H01L29/0634 , H01L29/0692
摘要： The present invention discloses a semiconductor PN junction structure and a manufacturing method thereof. From top view, the PN junction includes a staggered comb-teeth structure. The PN junction forms a depletion region with enhanced breakdown voltage, hence broadening the applications of a semiconductor device having such PN junction.
摘要翻译：本发明公开了一种半导体PN结结构及其制造方法。从顶视图，PN结包括交错的梳齿结构。 PN结形成具有增强的击穿电压的耗尽区，因此拓宽了具有这种PN结的半导体器件的应用。

63. 发明授权

US07839197B2 Level shift circuit 有权
标题翻译：电平移位电路
公开(公告)号：US07839197B2
公开(公告)日：2010-11-23
申请号：US12230953
申请日：2008-09-09
申请人： An-Tung Chen , Li-Wen Fang , Hung-Der Su
发明人： An-Tung Chen , Li-Wen Fang , Hung-Der Su
IPC分类号： H03L5/00
CPC分类号： H03K3/012 , H03K3/35613
摘要： A level shift circuit includes an input stage and an output stage coupled to each other by two nodes. The input stage changes the voltages on the nodes according to an input signal, and the output stage determines an output signal according to the voltages on the two nodes. In a transition state, the input stage provides a large current to charge or discharge the first node or the second node so as to quickly change the voltage thereon. In a steady state, the input stage lowers the current so as to reduce power consumption.
摘要翻译：电平移位电路包括由两个节点彼此耦合的输入级和输出级。输入级根据输入信号改变节点上的电压，输出级根据两个节点上的电压来确定输出信号。在过渡状态下，输入级提供大电流以对第一节点或第二节点进行充电或放电，以便快速地改变其上的电压。在稳定状态下，输入级降低电流，从而降低功耗。

64. 发明授权

US06444511B1 CMOS output circuit with enhanced ESD protection using drain side implantation 有权
标题翻译： CMOS输出电路采用漏极侧注入增强ESD保护
公开(公告)号：US06444511B1
公开(公告)日：2002-09-03
申请号：US09867562
申请日：2001-05-31
申请人： Yi-Hsu Wu , Hung-Der Su , Jian-Hsing Lee , Boon-Khim Liew
发明人： Yi-Hsu Wu , Hung-Der Su , Jian-Hsing Lee , Boon-Khim Liew
IPC分类号： H01L218238
CPC分类号： H01L27/092 , H01L21/823814 , H01L27/0266
摘要： A new cascaded NMOS transistor output circuit with enhanced ESD protection is achieved. A driver PMOS transistor has the source connected to a voltage supply, the gate connected to the input signal, and the drain connected to the output pad. A dummy PMOS transistor has the source and the gate connected to the voltage supply, and the drain connected to the output pad. A driver NMOS cascaded stack comprises first and second NMOS transistors. The first NMOS transistor has the source connected to ground and the gate connected to the input signal. The second NMOS transistor has the gate connected to the voltage supply, the source connected to the first NMOS transistor drain, and the drain connected to the output pad. A p− implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source. A dummy NMOS cascaded stack comprises third and fourth NMOS transistors. The third NMOS transistor has the gate and the source connected to ground. The fourth NMOS transistor has the gate connected to the voltage supply, the source connected to the third MOS transistor drain, and the drain connected to the output pad. A p− implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source.
摘要翻译：实现了具有增强ESD保护的新型级联NMOS晶体管输出电路。驱动器PMOS晶体管的源极连接到电源，栅极连接到输入信号，漏极连接到输出焊盘。虚设PMOS晶体管的源极和栅极连接到电源，漏极连接到输出焊盘。驱动器NMOS级联堆叠包括第一和第二NMOS晶体管。第一个NMOS晶体管的源极连接到地，栅极连接到输入信号。第二个NMOS晶体管的栅极连接到电源，源极连接到第一个NMOS晶体管漏极，漏极连接到输出焊盘。 p-注入区域位于漏极的n +区域的下面，但不在源极的n +区域的下面。虚设NMOS级联堆叠包括第三和第四NMOS晶体管。第三个NMOS晶体管的栅极和源极接地。第四个NMOS晶体管的栅极连接到电源，源极连接到第三个MOS晶体管漏极，漏极连接到输出焊盘。 p-注入区域位于漏极的n +区域的下面，但不在源极的n +区域的下面。

65. 发明授权

US6133096A Process for simultaneously fabricating a stack gate flash memory cell and salicided periphereral devices 失效
标题翻译：用于同时制造堆叠栅极闪存单元和浸液式周边器件的工艺
公开(公告)号：US6133096A
公开(公告)日：2000-10-17
申请号：US208917
申请日：1998-12-10
申请人： Hung-Der Su , Jong Chen , Chrong-Jung Lin , Di-Son Kuo
发明人： Hung-Der Su , Jong Chen , Chrong-Jung Lin , Di-Son Kuo
IPC分类号： H01L21/8247 , H01L27/105 , H01L21/336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11534
摘要： A process for integrating the fabrication of a flash memory cell, on a first region of a semiconductor substrate, with the fabrication of salicided peripheral devices, on a second region of the semiconductor substrate, has been developed. The flash memory cell features SAC contact structures, located between stacked gate structures, contacting underlying source/drain regions. The stack gate structures are comprised of a polycide control gate shape, on a dielectric layer, overlying a polysilicon floating gate shape. The performance of the peripheral devices are increased via use of metal silicide layers, located on the top surface of a polysilicon gate structure, as well as on the adjacent heavily doped source/drain regions.
摘要翻译：已经开发了在半导体衬底的第二区域上将闪存单元的制造在半导体衬底的第一区域上与制造水银外围器件进行集成的工艺。闪存单元具有位于层叠栅极结构之间的SAC接触结构，接触下层的源/漏区。堆叠栅极结构由覆盖多晶硅浮栅形状的介电层上的多晶硅控制栅极形状构成。通过使用位于多晶硅栅极结构的顶表面上的金属硅化物层以及相邻的重掺杂源极/漏极区域来增加外围器件的性能。

66. 发明授权

US6074915A Method of making embedded flash memory with salicide and sac structure 有权
标题翻译：制造具有自杀和囊结构的嵌入式闪存的方法
公开(公告)号：US6074915A
公开(公告)日：2000-06-13
申请号：US135044
申请日：1998-08-17
申请人： Jong Chen , Chrong Jung Lin , Hung-Der Su , Di-Son Kuo
发明人： Jong Chen , Chrong Jung Lin , Hung-Der Su , Di-Son Kuo
IPC分类号： H01L21/8247
CPC分类号： H01L27/11526 , H01L27/11536
摘要： A combined method of fabricating embedded flash memory cells having salicide and self-aligned contact (SAC) structures is disclosed. The SAC structure of the cell region and the salicide contacts of the peripheral region of the semiconductor device are formed using a single mask. This is accomplished by a judicious sequence of formation and removal of the various layers including the doped first and second polysilicon layers in the memory cell and of the intrinsic polysilicon layer used in the peripheral circuits. Thus, the etching of the self-aligned contact hole of the memory cell is accomplished at the same time the salicided contact hole of the peripheral region is formed. Furthermore, the thin and thick portions of the dual-gate oxide of the two regions are formed as a natural part of the total process without having to resort to photoresist masking of one portion of the gate oxide layer with the attendant contamination problems while removing the portion of the gate oxide in the other region of the substrate.
摘要翻译：公开了一种制造具有自对准接触（SAC）结构的嵌入式闪存单元的组合方法。半导体器件的周边区域的单元区域和硅化物触点的SAC结构使用单个掩模形成。这是通过明确的形成和去除包括存储单元中的掺杂的第一和第二多晶硅层以及在外围电路中使用的本征多晶硅层的各种层的顺序来实现的。因此，存储单元的自对准接触孔的蚀刻同时实现了周边区域的浸渍接触孔。此外，两个区域的双栅极氧化物的薄而厚的部分形成为总工艺的天然部分，而不必诉诸于栅极氧化物层的一部分的光致抗蚀剂掩模以及伴随的污染问题，同时去除栅极氧化物在衬底的另一区域中的部分。

67. 发明授权

US6028324A Test structures for monitoring gate oxide defect densities and the plasma antenna effect 失效
标题翻译：用于监测栅极氧化物缺陷密度和等离子体天线效应的测试结构
公开(公告)号：US6028324A
公开(公告)日：2000-02-22
申请号：US813758
申请日：1997-03-07
申请人： Hung-Der Su , Jian-Hsing Lee , Di-Son Kuo
发明人： Hung-Der Su , Jian-Hsing Lee , Di-Son Kuo
IPC分类号： H01L23/544 , H01L23/58 , H01L27/108
CPC分类号： H01L22/34 , H01L2924/0002
摘要： An ensemble of test structures comprising arrays of polysilicon plate MOS capacitors for the measurement of electrical quality of the MOSFET gate insulation is described. The test structures also measure plasma damage to these gate insulators incurred during metal etching and plasma ashing of photoresist. The structures are formed, either on test wafers or in designated areas of wafers containing integrated circuit chips. One of the test structures is designed primarily to minimize plasma damage so that oxide quality, and defect densities may be measured unhampered by interface traps created by plasma exposure. Other structures provide different antenna-to-oxide area ratios, useful for assessing plasma induced oxide damage and breakdown. The current-voltage characteristics of the MOS capacitors are measured by probing the structures on the wafer, thereby providing timely process monitoring capability.
摘要翻译：描述了包括用于测量MOSFET栅极绝缘的电气质量的多晶硅板MOS电容器阵列的测试结构的集合。测试结构还测量在金属蚀刻和光致抗蚀剂的等离子体灰化期间引起的这些栅绝缘体的等离子体损伤。在测试晶片上或在包含集成电路芯片的晶片的指定区域中形成结构。其中一个测试结构主要设计为最小化等离子体损伤，从而可以通过等离子体暴露产生的界面陷阱来测量氧化物质量和缺陷密度。其他结构提供不同的天线到氧化物面积比，可用于评估等离子体诱导的氧化物损伤和击穿。通过探测晶片上的结构来测量MOS电容器的电流 - 电压特性，从而提供及时的过程监控能力。

68. 发明申请

US20150079755A1 DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：双重扩散金属氧化物半导体器件及其制造方法
公开(公告)号：US20150079755A1
公开(公告)日：2015-03-19
申请号：US14559542
申请日：2014-12-03
申请人： Tzu-Cheng Kao , Jian-Hsing Lee , Jin-Lian Su , Huan-Ping Chu , Hung-Der Su
发明人： Tzu-Cheng Kao , Jian-Hsing Lee , Jin-Lian Su , Huan-Ping Chu , Hung-Der Su
IPC分类号： H01L29/66
CPC分类号： H01L29/66681 , H01L29/0696 , H01L29/1095 , H01L29/66689 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.
摘要翻译：本发明公开了一种双扩散金属氧化物半导体（DMOS）器件及其制造方法。 DMOS器件包括：第一导电类型衬底，第二导电型高压阱，栅极，第一导电类型体区域，第二导电类型源极，第二导电类型漏极，第一导电型体电极和第一导电型浮动区域。浮动区域形成在电气浮动并且与源极和栅极电隔离的体区中，使得减轻静电放电（ESD）效应。

69. 发明授权

US08981429B2 High electron mobility transistor and manufacturing method thereof 有权
标题翻译：高电子迁移率晶体管及其制造方法
公开(公告)号：US08981429B2
公开(公告)日：2015-03-17
申请号：US13898374
申请日：2013-05-20
申请人： Chih-Fang Huang , Po-Chin Peng , Tsung-Chieh Hsiao , Ya-Hsien Liu , K. C. Chang , Hung-Der Su , Chien-Wei Chiu , Tsung-Yi Huang , Tsung-Yu Yang , Ting-Fu Chang
发明人： Chih-Fang Huang , Po-Chin Peng , Tsung-Chieh Hsiao , Ya-Hsien Liu , K. C. Chang , Hung-Der Su , Chien-Wei Chiu , Tsung-Yi Huang , Tsung-Yu Yang , Ting-Fu Chang
IPC分类号： H01L29/66 , H01L29/778 , H01L29/20
CPC分类号： H01L29/66462 , H01L29/0657 , H01L29/2003 , H01L29/66431 , H01L29/7789
摘要： The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT device includes: a substrate, a first gallium nitride (GaN) layer; a P-type GaN layer, a second GaN layer, a barrier layer, a gate, a source, and a drain. The first GaN layer is formed on the substrate, and has a stepped contour from a cross-section view. The P-type GaN layer is formed on an upper step surface of the stepped contour, and has a vertical sidewall. The second GaN layer is formed on the P-type GaN layer. The barrier layer is formed on the second GaN layer. two dimensional electron gas regions are formed at junctions between the barrier layer and the first and second GaN layers. The gate is formed on an outer side of the vertical sidewall.
摘要翻译：本发明公开了一种高电子迁移率晶体管（HEMT）及其制造方法。 HEMT器件包括：衬底，第一氮化镓（GaN）层; P型GaN层，第二GaN层，势垒层，栅极，源极和漏极。第一GaN层形成在基板上，并且具有从横截面视图的阶梯状轮廓。 P型GaN层形成在阶梯状轮廓的上台阶面上，具有垂直侧壁。第二GaN层形成在P型GaN层上。阻挡层形成在第二GaN层上。在阻挡层与第一和第二GaN层之间的接合处形成二维电子气体区域。门形成在垂直侧壁的外侧。

70. 发明授权

US08928078B2 Double diffused metal oxide semiconductor device and manufacturing method thereof 有权
标题翻译：双扩散金属氧化物半导体器件及其制造方法
公开(公告)号：US08928078B2
公开(公告)日：2015-01-06
申请号：US13726579
申请日：2012-12-25
申请人： Tzu-Cheng Kao , Jian-Hsing Lee , Jin-Lian Su , Huan-Ping Chu , Hung-Der Su
发明人： Tzu-Cheng Kao , Jian-Hsing Lee , Jin-Lian Su , Huan-Ping Chu , Hung-Der Su
IPC分类号： H01L29/76 , H01L29/94 , H01L29/78 , H01L29/66
CPC分类号： H01L29/66681 , H01L29/0696 , H01L29/1095 , H01L29/66689 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.
摘要翻译：本发明公开了一种双扩散金属氧化物半导体（DMOS）器件及其制造方法。 DMOS器件包括：第一导电类型衬底，第二导电型高压阱，栅极，第一导电类型体区域，第二导电类型源极，第二导电类型漏极，第一导电型体电极和第一导电型浮动区域。浮动区域形成在电气浮动并且与源极和栅极电隔离的体区中，使得减轻静电放电（ESD）效应。

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