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61. 发明授权

US06583000B1 Process integration of Si1-xGex CMOS with Si1-xGex relaxation after STI formation 失效
标题翻译： STI形成后Si1-xGex CMOS与Si1-xGex弛豫过程的整合
公开(公告)号：US06583000B1
公开(公告)日：2003-06-24
申请号：US10072183
申请日：2002-02-07
申请人： Sheng Teng Hsu , Jong-Jan Lee , Jer-shen Maa , Douglas James Tweet
发明人： Sheng Teng Hsu , Jong-Jan Lee , Jer-shen Maa , Douglas James Tweet
IPC分类号： H01L218238
CPC分类号： H01L21/823807 , H01L21/76224 , H01L21/823878
摘要： A method of forming a CMOS device includes preparing a silicon substrate, including forming plural device regions on the substrate; epitaxially forming a strained SiGe layer on the substrate, wherein the SiGe layer has a germanium content of between about 20% and 40%; forming a silicon cap layer epitaxially on the SiGe layer; depositing a gate oxide layer; depositing a first polysilicon layer; implanting H+ ions to a depth below the SiGe layer; forming a trench by shallow trench isolation which extends into the substrate; annealing the structure at a temperature of between about 700° C. to 900° C. for between about five minutes to sixty minutes; depositing an oxide layer and a second polysilicon layer, thereby filling the trench; planarizing the structure to the top of the level of the portion of the second polysilicon layer which is located in the trench; and completing the CMOS device.
摘要翻译：形成CMOS器件的方法包括制备硅衬底，包括在衬底上形成多个器件区域; 在衬底上外延地形成应变SiGe层，其中SiGe层的锗含量在约20％和40％之间; 在SiGe层上外延地形成硅帽层; 沉积栅氧化层; 沉积第一多晶硅层; 将H +离子注入SiGe层以下的深度; 通过延伸到衬底中的浅沟槽隔离形成沟槽; 在约700℃至900℃的温度下退火结构约5分钟至60分钟; 沉积氧化物层和第二多晶硅层，从而填充沟槽; 将结构平面化到位于沟槽中的第二多晶硅层的部分的顶部的顶部; 并完成CMOS设备。

62. 发明授权

US07378309B2 Method of fabricating local interconnects on a silicon-germanium 3D CMOS 有权
标题翻译：在硅 - 锗3D CMOS上制造局部互连的方法
公开(公告)号：US07378309B2
公开(公告)日：2008-05-27
申请号：US11376542
申请日：2006-03-15
申请人： Jong-Jan Lee , Paul J. Schuele , Sheng Teng Hsu , Jer-Shen Maa
发明人： Jong-Jan Lee , Paul J. Schuele , Sheng Teng Hsu , Jer-Shen Maa
IPC分类号： H01L21/8234
CPC分类号： H01L21/823871 , H01L21/02532 , H01L21/02667 , H01L21/28525 , H01L21/76895 , H01L27/11 , H01L27/1108
摘要： A method of fabricating local interconnect on a silicon-germanium 3D CMOS includes fabricating an active silicon CMOS device on a silicon substrate. An insulator layer is deposited on the silicon substrate and a seed window is opened through the insulator layer to the silicon substrate and to a silicon CMOS device gate. A germanium thin film is deposited on the insulator layer and into windows, forming a contact between the germanium thin film and the silicon device. The germanium thin film is encapsulated in a dielectric material. The wafer is heated at a temperature sufficient to flow the germanium, while maintaining the other layers in a solid condition. The wafer is cooled to solidify the germanium as single crystal germanium and as polycrystalline germanium, which provides local interconnects. Germanium CMOS devices may be fabricated on the single crystal germanium thin film.
摘要翻译：在硅 - 锗3D CMOS上制造局部互连的方法包括在硅衬底上制造有源硅CMOS器件。绝缘体层沉积在硅衬底上，并且晶种窗通过绝缘体层向硅衬底和硅CMOS器件栅极打开。在绝缘体层和窗口上沉积锗薄膜，形成锗薄膜和硅器件之间的接触。锗薄膜被封装在电介质材料中。在足以使锗流动的温度下加热晶片，同时将其它层保持在固体状态。将晶片冷却以将锗固化为单晶锗和作为多晶锗，其提供局部互连。可以在单晶锗薄膜上制造锗CMOS器件。

63. 发明授权

US07226504B2 Method to form thick relaxed SiGe layer with trench structure 失效
标题翻译：形成具有沟槽结构的厚松弛SiGe层的方法
公开(公告)号：US07226504B2
公开(公告)日：2007-06-05
申请号：US10062336
申请日：2002-01-31
申请人： Jer-Shen Maa , Douglas James Tweet , Tingkai Li , Jong-Jan Lee , Sheng Teng Hsu
发明人： Jer-Shen Maa , Douglas James Tweet , Tingkai Li , Jong-Jan Lee , Sheng Teng Hsu
IPC分类号： C30B33/02
CPC分类号： H01L21/3247 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02694 , H01L21/324
摘要： A method of forming a SiGe layer having a relatively high germanium content and a relatively low threading dislocation density includes preparing a silicon substrate; depositing a layer of SiGe to a thickness of between about 100 nm to 500 nm, wherein the germanium content of the SiGe layer is greater than 20%, by atomic ratio; implanting H+ ions into the SiGe layer at a dose of between about 1·1016 cm−2 to 5·1016 cm−2, at an energy of between about 20 keV to 45 keV; patterning the SiGe layer with photoresist; plasma etching the structure to form trenches about regions; removing the photoresist; and thermal annealing the substrate and SiGe layer, to relax the SiGe layer, in an inert atmosphere at a temperature of between about 650° C. to 950° C. for between about 30 seconds and 30 minutes.
摘要翻译：形成具有较高锗含量和较低穿透位错密度的SiGe层的方法包括制备硅衬底; 将SiGe层沉积至约100nm至500nm的厚度，其中SiGe层的锗含量按原子比大于20％; 将H +离子以约1.10×16cm -2至0.0010±0.2cm的剂量注入SiGe层中， SUP>，在约20keV至45keV之间的能量; 用光致抗蚀剂图案化SiGe层; 等离子体蚀刻结构以形成关于区域的沟槽; 去除光致抗蚀剂; 以及对基板和SiGe层进行热退火，以在惰性气氛中在约650℃至950℃的温度下放置SiGe层约30秒至30分钟。

64. 发明授权

US07176072B2 Strained silicon devices transfer to glass for display applications 失效
标题翻译：应变硅器件转移到玻璃上进行显示应用
公开(公告)号：US07176072B2
公开(公告)日：2007-02-13
申请号：US11046411
申请日：2005-01-28
申请人： Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu
发明人： Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu
IPC分类号： H01L21/84 , H01L21/00 , H01L21/658
CPC分类号： H01L27/1266 , H01L27/1203 , H01L27/1214 , H01L29/78687
摘要： A method of fabricating strained silicon devices for transfer to glass for display applications includes preparing a wafer having a silicon substrate thereon; forming a relaxed SiGe layer on the silicon substrate; forming a strained silicon layer on the relaxed SiGe layer; fabricating an IC device on the strained silicon layer; depositing a dielectric layer on the wafer to cover a gate module of the IC device; smoothing the dielectric; implanting ions to form a defect layer; cutting the wafer into individual silicon dies; preparing a glass panel and the silicon dies for bonding; bonding the silicon dies onto the glass panel to form a bonded structure; annealing the bonded structure; splitting the bonded structure along the defect layer; removing the remaining silicon layer from the silicon substrate and relaxed SiGe layer on the silicon die on the glass panel; and completing the glass panel circuitry.
摘要翻译：制造用于转移到用于显示器应用的玻璃的应变硅器件的方法包括制备其上具有硅衬底的晶片; 在硅衬底上形成松弛的SiGe层; 在松弛的SiGe层上形成应变硅层; 在应变硅层上制造IC器件; 在所述晶片上沉积介电层以覆盖所述IC器件的栅极模块; 平滑电介质; 注入离子以形成缺陷层; 将晶片切割成单独的硅模具; 制备玻璃面板和用于接合的硅模具; 将硅模具接合到玻璃面板上以形成接合结构; 退火键合结构; 沿着缺陷层分离粘结结构; 从硅衬底去除剩余的硅层并在玻璃面板上的硅晶片上松弛SiGe层; 并完成玻璃面板电路。

65. 发明授权

US07800148B2 CMOS active pixel sensor 有权
标题翻译： CMOS有源像素传感器
公开(公告)号：US07800148B2
公开(公告)日：2010-09-21
申请号：US12178169
申请日：2008-07-23
申请人： Jong-Jan Lee , Sheng Teng Hsu , Douglas James Tweet , Jer-Shen Maa
发明人： Jong-Jan Lee , Sheng Teng Hsu , Douglas James Tweet , Jer-Shen Maa
IPC分类号： H01L31/062
CPC分类号： H01L27/14647
摘要： A CMOS active pixel sensor includes a silicon-on-insulator substrate having a silicon substrate with an insulator layer formed thereon and a top silicon layer formed on the insulator layer. A stacked pixel sensor cell includes a bottom photodiode fabricated on the silicon substrate, for sensing light of a longest wavelength; a middle photodiode fabricated on the silicon substrate, for sensing light of a medium wavelength, which is stacked above the bottom photodiode; and a top photodiode fabricated on the top silicon layer, for sensing light of a shorter wavelength, which is stacked above the middle and bottom photodiodes. Pixel transistor sets are fabricated on the top silicon layer and are associated with each pixel sensor cell by electrical connections which extend between each of the photodiodes and respective pixel transistor(s). CMOS control circuitry is fabricated adjacent to an array of active pixel sensor cells and electrically connected thereto.
摘要翻译： CMOS有源像素传感器包括具有在其上形成有绝缘体层的硅衬底和形成在绝缘体层上的顶部硅层的绝缘体上硅衬底。层叠像素传感器单元包括：制造在硅衬底上的底部光电二极管，用于感测最长波长的光; 制造在硅衬底上的中间光电二极管，用于感测中等波长的光; 和制造在顶部硅层上的顶部光电二极管，用于感测较短波长的光，该光被层叠在中间和底部光电二极管的上方。像素晶体管组被制造在顶部硅层上，并且通过在每个光电二极管和相应的像素晶体管之间延伸的电连接与每个像素传感器单元相关联。 CMOS控制电路与有源像素传感器单元的阵列相邻并且与其电连接。

66. 发明申请

US20080164577A1 Patterned silicon submicron tubes 失效
标题翻译：图案硅亚微米管
公开(公告)号：US20080164577A1
公开(公告)日：2008-07-10
申请号：US11649634
申请日：2007-01-04
申请人： Tingkai Li , Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu
发明人： Tingkai Li , Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu
IPC分类号： H01L21/3065 , H01L29/06
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/306 , H01L29/0669 , H01L29/0673 , Y10S977/743
摘要： An array of submicron silicon (Si) tubes is provided with a method for patterning submicron Si tubes. The method provides a Si substrate, and forms a silicon dioxide film overlying the Si substrate. An array of silicon dioxide rods is formed from the silicon dioxide film, and Si3N4 tubes are formed surrounding the silicon dioxide rods. The silicon dioxide rods are etched away. Then, exposed regions of the Si substrate are etched, forming Si tubes underlying the Si3N4 tubes. Finally, the Si3N4 tubes are removed.
摘要翻译：亚微米硅（Si）管的阵列具有用于构图亚微米Si管的方法。该方法提供Si衬底，并形成覆盖Si衬底的二氧化硅膜。由二氧化硅膜形成二氧化硅棒的阵列，并且在二氧化硅棒周围形成Si 3 N 4 N 4管。二氧化硅棒被蚀刻掉。然后，蚀刻Si衬底的暴露区域，形成Si 3 N 4 N 4管子下面的Si管。最后，去除Si 3 N 4 N 4管。

67. 发明授权

US07514282B2 Patterned silicon submicron tubes 失效
标题翻译：图案硅亚微米管
公开(公告)号：US07514282B2
公开(公告)日：2009-04-07
申请号：US11649634
申请日：2007-01-04
申请人： Tingkai Li , Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu
发明人： Tingkai Li , Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu
IPC分类号： H01L21/00
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/306 , H01L29/0669 , H01L29/0673 , Y10S977/743
摘要： An array of submicron silicon (Si) tubes is provided with a method for patterning submicron Si tubes. The method provides a Si substrate, and forms a silicon dioxide film overlying the Si substrate. An array of silicon dioxide rods is formed from the silicon dioxide film, and Si3N4 tubes are formed surrounding the silicon dioxide rods. The silicon dioxide rods are etched away. Then, exposed regions of the Si substrate are etched, forming Si tubes underlying the Si3N4 tubes. Finally, the Si3N4 tubes are removed.
摘要翻译：亚微米硅（Si）管的阵列具有用于构图亚微米Si管的方法。该方法提供Si衬底，并形成覆盖Si衬底的二氧化硅膜。由二氧化硅膜形成二氧化硅棒阵列，在二氧化硅棒周围形成Si 3 N 4管。二氧化硅棒被蚀刻掉。然后，蚀刻Si衬底的暴露区域，形成Si 3 N 4管下面的Si管。最后，去除Si3N4管。

68. 发明申请

US20080303072A1 CMOS Active Pixel Sensor 有权
标题翻译： CMOS有源像素传感器
公开(公告)号：US20080303072A1
公开(公告)日：2008-12-11
申请号：US12178169
申请日：2008-07-23
申请人： Jong-Jan Lee , Sheng Teng Hsu , Douglas James Tweet , Jer-Shen Maa
发明人： Jong-Jan Lee , Sheng Teng Hsu , Douglas James Tweet , Jer-Shen Maa
IPC分类号： H01L31/113
CPC分类号： H01L27/14647
摘要： A CMOS active pixel sensor includes a silicon-on-insulator substrate having a silicon substrate with an insulator layer formed thereon and a top silicon layer formed on the insulator layer. A stacked pixel sensor cell includes a bottom photodiode fabricated on the silicon substrate, for sensing light of a longest wavelength; a middle photodiode fabricated on the silicon substrate, for sensing light of a medium wavelength, which is stacked above the bottom photodiode; and a top photodiode fabricated on the top silicon layer, for sensing light of a shorter wavelength, which is stacked above the middle and bottom photodiodes. Pixel transistor sets are fabricated on the top silicon layer and are associated with each pixel sensor cell by electrical connections which extend between each of the photodiodes and respective pixel transistor(s). CMOS control circuitry is fabricated adjacent to an array of active pixel sensor cells and electrically connected thereto.
摘要翻译： CMOS有源像素传感器包括具有在其上形成有绝缘体层的硅衬底和形成在绝缘体层上的顶部硅层的绝缘体上硅衬底。层叠像素传感器单元包括：制造在硅衬底上的底部光电二极管，用于感测最长波长的光; 制造在硅衬底上的中间光电二极管，用于感测中等波长的光; 和制造在顶部硅层上的顶部光电二极管，用于感测较短波长的光，该光被层叠在中间和底部光电二极管的上方。像素晶体管组被制造在顶部硅层上，并且通过在每个光电二极管和相应的像素晶体管之间延伸的电连接与每个像素传感器单元相关联。 CMOS控制电路与有源像素传感器单元的阵列相邻并且与其电连接。

69. 发明授权

US07608874B2 Fully isolated photodiode stack 失效
标题翻译：全隔离光电二极管堆叠
公开(公告)号：US07608874B2
公开(公告)日：2009-10-27
申请号：US11657152
申请日：2007-01-24
申请人： Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
发明人： Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
IPC分类号： H01L31/062 , H01L31/113
CPC分类号： H01L27/14647 , H01L27/1463 , H01L27/14689
摘要： An array of fully isolated multi-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cells is provided, together with an associated fabrication method. The method provides a bulk silicon (Si) substrate. A plurality of color imager cells are formed, either in the Si substrate, or in a single epitaxial Si layer formed over the substrate. Each color imager cell includes a photodiode set with a first, second, and third photodiode formed as a stacked multi-junction structure. A U-shaped (in cross-section) well liner, fully isolates the photodiode set from adjacent photodiode sets in the array. For example, each photodiode is formed from a p doped Si layer physically interfaced to a first wall. A well bottom physically interfaces to the first wall, and the p doped Si layer of the third, bottom-most, photodiode is part of the well bottom. Then, the photodiode sets may be formed from an n/p/n/p/n/p or n/p/p−/p/p−/p layered structure.
摘要翻译：提供了完全隔离的多结互补金属氧化物半导体（CMOS）无滤膜彩色成像器单元的阵列，以及相关的制造方法。该方法提供体硅（Si）衬底。在Si衬底中或在衬底上形成的单个外延Si层中形成多个彩色成像器单元。每个彩色成像器单元包括具有形成为堆叠多结结构的第一，第二和第三光电二极管。 U形（横截面）井衬管，将阵列中的光电二极管组与相邻的光电二极管组完全隔离。例如，每个光电二极管由物理上与第一壁物理连接的p掺杂Si层形成。阱底部与第一壁物理接口，第三，最底部的光电二极管的p掺杂Si层是阱底部的一部分。然后，光电二极管组可以由n / p / n / p / n / p或n / p / p / p / p / p层叠结构形成。

70. 发明授权

US07651883B2 High energy implant photodiode stack 失效
标题翻译：高能注入光电二极管叠层
公开(公告)号：US07651883B2
公开(公告)日：2010-01-26
申请号：US11801320
申请日：2007-05-09
申请人： Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
发明人： Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
IPC分类号： H01L21/00
CPC分类号： H01L27/14647 , H01L27/1463 , H01L27/14689
摘要： An array of fully isolated multi-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cells is provided, with a corresponding fabrication process. The color imager cell array is formed from a bulk silicon (Si) substrate without an overlying epitaxial Si layer. A plurality of color imager cells are formed in the bulk Si substrate, where each color imager cell includes a photodiode set and a U-shaped well liner. The photodiode set includes first, second, and third photodiode formed as a stacked multi-junction structure, while the U-shaped well liner fully isolates the photodiode set from adjacent photodiode sets in the array. The U-shaped well liner includes a physically interfacing doped well liner bottom and first wall. The well liner bottom is interposed between the substrate and the photodiode set, and the first wall physically interfaces each doped layer of each photodiode in the photodiode set.
摘要翻译：提供了完全隔离的多结互补金属氧化物半导体（CMOS）无滤膜彩色成像器单元的阵列，具有相应的制造工艺。彩色成像器单元阵列由体硅（Si）衬底形成，而不具有上覆的外延Si层。在本体Si衬底中形成多个彩色成像器单元，其中每个彩色成像器单元包括光电二极管组和U形衬管。光电二极管组包括形成为堆叠多结结构的第一，第二和第三光电二极管，而U形阱衬套将光电二极管组与阵列中的相邻光电二极管组完全隔离。 U形井衬管包括物理接口掺杂的井筒底部和第一壁。阱衬底位于衬底和光电二极管组之间，并且第一壁物理地连接光电二极管组中每个光电二极管的每个掺杂层。

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