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61. 发明授权

US07240322B2 Method of adding fabrication monitors to integrated circuit chips 有权
标题翻译：将制造监控器添加到集成电路芯片的方法
公开(公告)号：US07240322B2
公开(公告)日：2007-07-03
申请号：US10907494
申请日：2005-04-04
申请人： James W. Adkisson , Greg Bazan , John M. Cohn , Matthew S. Grady , Thomas G. Sopchak , David P. Vallett
发明人： James W. Adkisson , Greg Bazan , John M. Cohn , Matthew S. Grady , Thomas G. Sopchak , David P. Vallett
IPC分类号： G06F17/50
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.
摘要翻译：一种用于设计的集成电路，方法和系统以及制造集成电路的方法。该方法包括：（a）生成集成电路的集成电路设计的光掩模级设计，光掩模级设计包括多个集成电路元件形状; （b）指定相邻集成电路元件形状之间的光掩模级设计的区域，指定区域足够大以至于基于填充形状规则需要在相邻集成电路元件之间放置填充形状，集成电路; 以及（c）将监视器结构的一个或多个监视器结构形状放置在指定区域中的至少一个中，该集成电路的操作不需要监视器结构。

62. 发明授权

US07217968B2 Recessed gate for an image sensor 有权
标题翻译：嵌入式门用于图像传感器
公开(公告)号：US07217968B2
公开(公告)日：2007-05-15
申请号：US10905097
申请日：2004-12-15
申请人： James W. Adkisson , John Ellis-Monaghan , Mark D. Jaffe , Jerome B. Lasky
发明人： James W. Adkisson , John Ellis-Monaghan , Mark D. Jaffe , Jerome B. Lasky
IPC分类号： H01L31/062
CPC分类号： H01L27/14603 , H01L27/14601 , H01L27/14689 , H01L29/66621
摘要： A novel image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate, a gate comprising a dielectric layer and gate conductor formed on the dielectric layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side of the gate conductor, a pinning layer of a second conductivity type formed atop the collection well at the substrate surface, and a diffusion region of a first conductivity type formed adjacent a second side of the gate conductor, the gate conductor forming a channel region between the collection well layer and the diffusion region. Part of the gate conductor bottom is recessed below the surface of the substrate. Preferably, a portion of the gate conductor is recessed at or below a bottom surface of the pinning layer to a depth such that the collection well intersects the channel region.
摘要翻译：一种新颖的图像传感器单元结构及其制造方法。成像传感器包括基板，包括电介质层和形成在电介质层上的栅极导体的栅极，形成在与栅极导体的第一侧相邻的基板的表面下面的第一导电类型的收集阱层，钉扎层在基板表面上形成在集合阱顶部的第二导电类型的第一导电类型的扩散区和在栅极导体的第二侧附近形成的第一导电类型的扩散区，栅极导体在集电阱层和扩散区之间形成沟道区。栅极导体底部的一部分凹陷在基板的表面下方。优选地，栅极导体的一部分在钉扎层的底表面处或下方凹陷到使得收集阱与沟道区相交的深度。

63. 发明授权

US07089514B2 Defect diagnosis for semiconductor integrated circuits 失效
标题翻译：半导体集成电路缺陷诊断
公开(公告)号：US07089514B2
公开(公告)日：2006-08-08
申请号：US10710879
申请日：2004-08-10
申请人： James W. Adkisson , Greg Bazan , John M. Cohn , Francis Gravel , Leendert M. Huisman , Phillip J. Nigh , Leah M. P. Pastel , Kenneth Rowe , Thomas G. Sopchak , David E. Sweenor
发明人： James W. Adkisson , Greg Bazan , John M. Cohn , Francis Gravel , Leendert M. Huisman , Phillip J. Nigh , Leah M. P. Pastel , Kenneth Rowe , Thomas G. Sopchak , David E. Sweenor
IPC分类号： G06F17/50
CPC分类号： G01R31/31718 , G01R31/318342
摘要： A method for defect diagnosis of semiconductor chip. The method comprises the steps of (a) identifying M design structures and N physical characteristics of the circuit design, wherein M and N are positive integers, wherein each design structure of the M design structures is testable as to pass or fail, and wherein each physical characteristic of the N physical characteristics is present in at least one design structure of the M design structures; (b) for each design structure of the M design structures of the circuit design, determining a fail rate and determining whether the fail rate is high or low; and (c) if every design structure of the M design structures in which a physical characteristic of the N physical characteristics is present has a high fail rate, then flagging the physical characteristic as being likely to contain at least a defect.
摘要翻译：一种半导体芯片缺陷诊断方法。该方法包括以下步骤：（a）识别电路设计的M个设计结构和N个物理特性，其中M和N是正整数，其中M个设计结构的每个设计结构可以通过或失败，并且其中每个 N物理特性的物理特性存在于M设计结构的至少一个设计结构中; （b）对于电路设计的M设计结构的每个设计结构，确定故障率并确定故障率是高还是低; 和（c）如果存在N个物理特性的物理特性的M设计结构的每个设计结构具有高故障率，则将物理特性标记为可能至少包含缺陷。

64. 发明授权

US07009237B2 Out of the box vertical transistor for eDRAM on SOI 有权
标题翻译：在SOI上用于eDRAM的开箱式垂直晶体管
公开(公告)号：US07009237B2
公开(公告)日：2006-03-07
申请号：US10709450
申请日：2004-05-06
申请人： James W. Adkisson , Gary B. Bronner , Dureseti Chidambarrao , Ramachandra Divakaruni , Carl J. Radens
发明人： James W. Adkisson , Gary B. Bronner , Dureseti Chidambarrao , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L27/108
CPC分类号： H01L27/10841 , H01L27/10864 , H01L27/10867
摘要： The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.
摘要翻译：本发明提供了一种形成在绝缘体上硅衬底上的垂直存储器件，其中接触绝缘体上硅衬底的上表面的位线通过上带扩散区域电连接到垂直存储器件掩埋氧化层。上带扩散区域通过横向蚀刻掩埋氧化物区域的一部分而形成，其中沉积掺杂多晶硅。上带区域扩散区域还为垂直存储器件的垂直晶体管提供源极。垂直存储器件还可以与具有形成在绝缘体上硅衬底上的逻辑器件的支撑区域集成。

65. 发明授权

US06960744B2 Electrically tunable on-chip resistor 失效
标题翻译：电可调片上电阻
公开(公告)号：US06960744B2
公开(公告)日：2005-11-01
申请号：US10604609
申请日：2003-08-04
申请人： James W. Adkisson , Anthony Kendall Stamper
发明人： James W. Adkisson , Anthony Kendall Stamper
IPC分类号： H01C10/00 , H01L27/08 , H05B1/02
CPC分类号： H01C10/00 , H01L27/0802
摘要： A device having a resistor and a heater disposed proximate to the resistor and capable of raising the temperature of the resistor. The device further includes a dieletric disposed between the heater and the resistor and a tuner electrically coupled to the resistor. The heater adjusts the resistance of the resistor in response to the tuner.
摘要翻译：一种具有电阻器和靠近电阻器设置并能够提高电阻器温度的加热器的器件。该装置还包括设置在加热器和电阻器之间的小孔，以及电耦合到电阻器的调谐器。加热器根据调谐器调节电阻的电阻。

66. 发明授权

US06670255B2 Method of fabricating lateral diodes and bipolar transistors 有权
标题翻译：制造横向二极管和双极晶体管的方法
公开(公告)号：US06670255B2
公开(公告)日：2003-12-30
申请号：US09965289
申请日：2001-09-27
申请人： James W. Adkisson , Jeffrey P. Gambino , Peter B. Gray , Anthony K. Stamper
发明人： James W. Adkisson , Jeffrey P. Gambino , Peter B. Gray , Anthony K. Stamper
IPC分类号： H01L21331
CPC分类号： H01L27/1203 , H01L27/0664
摘要： Disclosed is a method of fabricating a lateral semiconductor device, comprising: providing a substrate, having at least an upper silicon portion forming at least one first dopant type region and at least one second dopant type region in the upper portion of the substrate, at least one of the first dopant type regions abutting at least one of the second dopant type regions and thereby forming at least one PN junction; and forming at least one protective island on a top surface of the upper silicon portion, the protective island extending the length of the PN junction and overlapping a portion of the first dopant type region and a portion of an abutting second dopant type region.
摘要翻译：公开了一种制造横向半导体器件的方法，包括：提供衬底，至少具有在衬底的上部中至少形成至少一个第一掺杂剂型区域和至少一个第二掺杂剂类型区域的上硅部分，至少第一掺杂剂类型区域中的一个与第二掺杂剂类型区域中的至少一个邻接，从而形成至少一个PN结; 以及在所述上硅部分的顶表面上形成至少一个保护岛，所述保护岛延伸所述PN结的长度并与所述第一掺杂剂型区域的一部分和邻接的第二掺杂剂型区域的一部分重叠。

67. 发明授权

US06350653B1 Embedded DRAM on silicon-on-insulator substrate 有权
标题翻译：绝缘体上硅衬底上的嵌入式DRAM
公开(公告)号：US06350653B1
公开(公告)日：2002-02-26
申请号：US09689096
申请日：2000-10-12
申请人： James W. Adkisson , Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman
发明人： James W. Adkisson , Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman
IPC分类号： H01L21336
CPC分类号： H01L27/10864 , H01L21/84 , H01L27/1087 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is presented which is directed to a method of forming embedded DRAM and logic devices, where the DRAM devices are formed in bulk, single crystalline semiconductor regions and logic devices are formed in silicon-on-insulator (“SOI”) regions and where buried, doped glass is used as a mask to form deep trenches for storage in the bulk region. The resulting structure is also disclosed.
摘要翻译：提出了一种半导体器件，其涉及一种形成嵌入式DRAM和逻辑器件的方法，其中DRAM器件以块状形成，单晶半导体区域和逻辑器件形成在绝缘体上硅（“SOI”）区域中，其中掩埋的掺杂玻璃用作掩模以形成用于存储在本体区域中的深沟槽。还公开了所得到的结构。

68. 发明授权

US09225311B2 Method of manufacturing switchable filters 有权
标题翻译：制造可切换过滤器的方法
公开(公告)号：US09225311B2
公开(公告)日：2015-12-29
申请号：US13401418
申请日：2012-02-21
申请人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
发明人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
IPC分类号： H03H3/02 , H03H3/007 , H03H9/56 , H03H9/10 , H03H9/24 , H03H3/08 , H03H9/02 , G06F17/50 , H03H9/15
CPC分类号： H03H3/007 , G06F17/5063 , H03H3/02 , H03H3/08 , H03H9/02007 , H03H9/02244 , H03H9/02992 , H03H9/1071 , H03H9/2447 , H03H9/2452 , H03H9/2457 , H03H9/2463 , H03H9/54 , H03H9/56 , H03H9/64 , H03H2003/022 , H03H2003/023 , H03H2003/027 , H03H2009/155 , Y10T29/42 , Y10T29/49005 , Y10T29/49155
摘要： Switchable and/or tunable filters, methods of manufacture and design structures are provided. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed to be in contact with at least one piezoelectric substrate. The method further includes forming a micro-electro-mechanical structure (MEMS) comprising a MEMS beam in which, upon actuation, the MEMS beam will turn on the at least one piezoelectric filter structure by interleaving electrodes in contact with the piezoelectric substrate or sandwiching the at least one piezoelectric substrate between the electrodes.
摘要翻译：提供可切换和/或可调滤波器，制造方法和设计结构。形成滤波器的方法包括形成至少一个压电滤波器结构，其包括形成为与至少一个压电基板接触的多个电极。该方法还包括形成包括MEMS光束的微电子机械结构（MEMS），其中，在致动时，MEMS光束将通过交替与压电基板接触的电极或者将电极之间的至少一个压电基板。

69. 发明授权

US09048809B2 Method of manufacturing switchable filters 有权
标题翻译：制造可切换过滤器的方法
公开(公告)号：US09048809B2
公开(公告)日：2015-06-02
申请号：US13342375
申请日：2012-01-03
申请人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
发明人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
IPC分类号： H03H3/08 , H03H9/05 , H03H9/10 , H01L41/09 , H03H9/64
CPC分类号： H03H3/04 , B81B7/008 , B81B7/02 , G06F17/5045 , H01L41/094 , H01L41/0973 , H03H3/08 , H03H9/0542 , H03H9/0547 , H03H9/1064 , H03H9/1092 , H03H9/48 , H03H9/542 , H03H9/6403 , H03H9/6423 , Y10T29/42 , Y10T29/49005 , Y10T29/49126 , Y10T29/49147 , Y10T29/49156
摘要： Switchable and/or tunable filters and methods of manufacture. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed on a piezoelectric substrate. The method further includes forming a micro-electro-mechanical structure (MEMS) comprising a MEMS beam formed above the piezoelectric substrate and at a location in which, upon actuation, the MEMS beam shorts the piezoelectric filter structure by contacting at least one of the plurality of electrodes.
摘要翻译：可切换和/或可调滤波器和制造方法。形成滤波器的方法包括形成至少一个包括形成在压电基片上的多个电极的压电滤波器结构。该方法还包括形成微电子机械结构（MEMS），该微机电结构（MEMS）包括形成在压电基板上方的MEMS光束，并且在致动时，MEMS光束通过使多个或多个之中的至少一个接触而使压电滤波器结构短路的位置的电极。

70. 发明授权

US08900954B2 Blanket short channel roll-up implant with non-angled long channel compensating implant through patterned opening 有权
标题翻译：毯子短通道卷起植入物，具有通过图案化开口的非角度长通道补偿植入物
公开(公告)号：US08900954B2
公开(公告)日：2014-12-02
申请号：US13289051
申请日：2011-11-04
申请人： James W. Adkisson , Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： James W. Adkisson , Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/772 , H01L21/336 , H01L21/28 , H01L29/66 , H01L29/10 , H01L21/265
CPC分类号： H01L29/1041 , H01L21/2652 , H01L21/26586 , H01L21/28026 , H01L29/0847 , H01L29/1045 , H01L29/36 , H01L29/66537 , H01L29/66583 , H01L29/6659 , H01L29/78
摘要： A method that forms a structure implants a well implant into a substrate, patterns a mask on the substrate (to have at least one opening that exposes a channel region of the substrate) and forms a conformal dielectric layer on the mask and to line the opening. The conformal dielectric layer covers the channel region of the substrate. The method also forms a conformal gate metal layer on the conformal dielectric layer, implants a compensating implant through the conformal gate metal layer and the conformal dielectric layer into the channel region of the substrate, and forms a gate conductor on the conformal gate metal layer. Additionally, the method removes the mask to leave a gate stack on the substrate, forms sidewall spacers on the gate stack, and then forms source/drain regions in the substrate partially below the sidewall spacers.
摘要翻译：一种形成将衬底植入衬底的结构的方法，在衬底上图案掩模（具有暴露衬底的沟道区的至少一个开口），并在掩模上形成共形电介质层并使开口。保形介电层覆盖衬底的沟道区。该方法还在保形电介质层上形成共形栅极金属层，通过共形栅极金属层和共形绝缘层将补偿注入植入衬底的沟道区，并在共形栅极金属层上形成栅极导体。此外，该方法去除掩模以在衬底上留下栅极堆叠，在栅极堆叠上形成侧壁间隔物，然后在衬底中部分地在侧壁间隔物下方形成源极/漏极区域。

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