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61. 发明申请

US20100013009A1 Structure and Method for Forming Trench Gate Transistors with Low Gate Resistance 审中-公开
标题翻译：用于形成具有低栅极电阻的沟槽栅极晶体管的结构和方法
公开(公告)号：US20100013009A1
公开(公告)日：2010-01-21
申请号：US12333707
申请日：2008-12-12
申请人： James Pan
发明人： James Pan
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66727 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/4958 , H01L29/4966 , H01L29/66734 , H01L29/7397
摘要： A field effect transistor includes body regions of a first conductivity type over a semiconductor region of a second conductivity type such that the body regions form p-n junctions with the semiconductor region. Trenches extend through the body region and terminate within the semiconductor region. Source regions of the second conductivity type extend over the body regions adjacent the trenches such that the source regions form p-n junctions with the body regions. A gate dielectric layer lines sidewalls of each trench. A metal liner lines the gate dielectric layer in each trench. A gate electrode comprising metallic material is disposed in each trench.
摘要翻译：场效应晶体管包括在第二导电类型的半导体区域上的第一导电类型的主体区域，使得主体区域与半导体区域形成p-n结。沟槽延伸穿过身体区域并终止在半导体区域内。第二导电类型的源极区域在与沟槽相邻的主体区域上延伸，使得源极区域与主体区域形成p-n结。栅极电介质层对每个沟槽的侧壁进行排列。金属衬垫在每个沟槽中排列栅极电介质层。包括金属材料的栅电极设置在每个沟槽中。

62. 发明申请

US20090315083A1 Structure and Method for Forming a Thick Bottom Dielectric (TBD) for Trench-Gate Devices 有权
标题翻译：用于形成用于沟槽栅极器件的厚底电介质（TBD）的结构和方法
公开(公告)号：US20090315083A1
公开(公告)日：2009-12-24
申请号：US12143510
申请日：2008-06-20
申请人： James Pan , Christopher Lawrence Rexer
发明人： James Pan , Christopher Lawrence Rexer
IPC分类号： H01L29/00 , H01L21/76
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/8725
摘要： A semiconductor structure which includes a trench gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD.
摘要翻译：包括沟槽栅极FET的半导体结构如下形成。使用掩模在半导体区域中形成多个沟槽。掩模包括（i）半导体区域的表面上的第一绝缘层，（ii）第一绝缘层上的第一氧化阻挡层，以及（iii）第一氧化阻挡层上的第二绝缘层。沿每个沟槽的底部形成厚底部电介质（TBD）。第一氧化阻挡层防止在形成TBD期间沿着半导体区域的表面形成电介质层。

63. 发明授权

US07622348B2 Methods for fabricating an integrated circuit 有权
标题翻译：制造集成电路的方法
公开(公告)号：US07622348B2
公开(公告)日：2009-11-24
申请号：US11616858
申请日：2006-12-28
申请人： James Pan
发明人： James Pan
IPC分类号： H01L21/8242
CPC分类号： H01L21/76897 , H01L21/28568 , H01L21/288 , H01L27/10855 , H01L27/10888 , H01L27/10894
摘要： Methods are provided for reducing the aspect ratio of contacts to bit lines in fabricating an IC including logic and memory. The method includes the steps of forming a first group of device regions to be contacted by a first level of metal and a second group of memory bit lines to be contacted by a second level of metal, the first level separated from the second level by at least one layer of dielectric material. Conductive material is plated by electroless plating on the device regions and bit lines and first and second conductive plugs are formed overlying the conductive material. The first conductive plugs are contacted by the first level of metal and the second conductive plugs are contacted by the second level of metal. The thickness of the plated conductive material provides a self aligned process for reducing the aspect ratio of the conductive plugs.
摘要翻译：提供了用于在制造包括逻辑和存储器的IC中减小与位线的触点的纵横比的方法。该方法包括以下步骤：形成将由金属的第一级接触的第一组器件区域和与第二级金属接触的第二组存储器位线，该第一级与第二级与第二级分开至少一层介电材料。导电材料通过化学镀在器件区域和位线上进行电镀，并且第一和第二导电插塞形成在导电材料上。第一导电插头与第一级金属接触，第二导电插头与第二级金属接触。镀覆的导电材料的厚度提供了一种自对准的方法，用于减小导电插头的纵横比。

64. 发明申请

US20090194811A1 Structure and Method for Forming Field Effect Transistor with Low Resistance Channel Region 有权
标题翻译：用于形成具有低电阻通道区域的场效应晶体管的结构和方法
公开(公告)号：US20090194811A1
公开(公告)日：2009-08-06
申请号：US12330273
申请日：2008-12-08
申请人： James Pan , Qi Wang
发明人： James Pan , Qi Wang
IPC分类号： H01L29/78
CPC分类号： H01L29/165 , H01L21/26506 , H01L29/407 , H01L29/42368 , H01L29/66712 , H01L29/66719 , H01L29/66734 , H01L29/7397 , H01L29/7802 , H01L29/7813
摘要： A trench-gate field effect transistor includes trenches extending into a silicon region of a first conductivity type, and a gate electrodes in each trench. Body regions of second conductivity type extend over the silicon region between adjacent trenches. Each body region forms a first PN junction with the silicon region, and each body region includes a silicon-germanium layer of the second conductivity type laterally extending between adjacent trenches. Source regions of the first conductivity flank the trenches, and each source region forms a second PN junction with one of the body regions. Channel regions extend in the body regions along sidewalls of the trenches between the source regions and a bottom surface of the body regions. The silicon-germanium layers extend into corresponding channel regions to thereby reduce the channel resistance.
摘要翻译：沟槽栅场效应晶体管包括延伸到第一导电类型的硅区域的沟槽和每个沟槽中的栅电极。第二导电类型的主体区域延伸在相邻沟槽之间的硅区域上。每个体区与硅区形成第一PN结，并且每个体区包括在相邻沟槽之间横向延伸的第二导电类型的硅 - 锗层。第一导电体的源区在沟槽的侧面，并且每个源极区域与身体区域之一形成第二PN结。通道区域沿着源区域和身体区域的底表面之间的沟槽的侧壁在身体区域中延伸。硅 - 锗层延伸到相应的沟道区，从而降低沟道电阻。

65. 发明授权

US07563867B2 PRO4356 polypeptides 有权
标题翻译： PRO4356多肽
公开(公告)号：US07563867B2
公开(公告)日：2009-07-21
申请号：US10187595
申请日：2002-07-01
申请人： Kevin P. Baker , Jian Chen , Luc Desnoyers , Audrey Goddard , Paul J. Godowski , Austin L. Gurney , James Pan , Victoria Smith , Colin K. Watanabe , William I. Wood , Zemin Zhang
发明人： Kevin P. Baker , Jian Chen , Luc Desnoyers , Audrey Goddard , Paul J. Godowski , Austin L. Gurney , James Pan , Victoria Smith , Colin K. Watanabe , William I. Wood , Zemin Zhang
IPC分类号： A61K38/00 , A61K38/17 , C07K14/00
CPC分类号： C07K14/47 , A01K2217/075 , A01K2227/105 , A61K38/00 , C07K14/4748 , C07K14/705 , C07K14/82 , C07K16/28 , C07K2319/30 , C12Q1/6816 , C12Q1/6883 , C12Q1/6886 , C12Q2600/136 , C12Q2600/158 , G01N33/5082 , G01N33/5308 , G01N33/574 , G01N33/57419 , G01N33/57423 , G01N33/57434 , G01N33/57484 , G01N33/57488 , G01N33/57492 , G01N2500/00 , C12Q2563/131 , C12Q2527/137
摘要： The present invention is directed to novel polypeptides and to nucleic acid molecules encoding those polypeptides. Also provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptide molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention and to methods for producing the polypeptides of the present invention.
摘要翻译：本发明涉及新型多肽和编码那些多肽的核酸分子。本文还提供了包含那些核酸序列的载体和宿主细胞，包含与异源多肽序列融合的本发明的多肽的嵌合多肽分子，与本发明的多肽结合的抗体以及本发明的多肽的制备方法发明。

66. 发明申请

US20080182275A1 Secreted and transmembrane polypeptides and nucleic acids encoding the same 审中-公开
公开(公告)号：US20080182275A1
公开(公告)日：2008-07-31
申请号：US11786466
申请日：2007-04-10
申请人： Avi J Ashkenazi , Kevin P. Baker , David Botstein , Luc Desnoyers , Dan L. Eaton , Napoleone Ferrara , Ellen Filvaroff , Sherman Fong , Wei-Qiang Gao , Hanspeter Gerber , Mary E. Gerritsen , Audrey Goddard , Paul J. Godowski , J. Christopher Grimaldi , Austin L. Gurney , Kenneth J. Hillan , Ivar J. Kljavin , Sophia S. Kuo , Mary A. Napier , James Pan , Nicholas F. Paoni , Margaret Ann Roy , David L. Shelton , Timothy A. Stewart , Daniel Tumas , P. Mickey Williams , William I. Wood
发明人： Avi J Ashkenazi , Kevin P. Baker , David Botstein , Luc Desnoyers , Dan L. Eaton , Napoleone Ferrara , Ellen Filvaroff , Sherman Fong , Wei-Qiang Gao , Hanspeter Gerber , Mary E. Gerritsen , Audrey Goddard , Paul J. Godowski , J. Christopher Grimaldi , Austin L. Gurney , Kenneth J. Hillan , Ivar J. Kljavin , Sophia S. Kuo , Mary A. Napier , James Pan , Nicholas F. Paoni , Margaret Ann Roy , David L. Shelton , Timothy A. Stewart , Daniel Tumas , P. Mickey Williams , William I. Wood
IPC分类号： G01N33/53 , C07H21/04 , C12N15/63 , C12N5/06 , C12N5/16 , C12N1/21 , C12N1/19 , C12P21/00 , C07K2/00 , C07K16/46 , C07K16/18 , G01N33/566
CPC分类号： C07K14/47 , G01N33/6872
摘要： The present invention is directed to novel polypeptides and to nucleic acid molecules encoding those polypeptides. Also provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptide molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention and to methods for producing the polypeptides of the present invention.

67. 发明申请

US20080102571A1 METHODS FOR FABRICATING A STRESS ENHANCED MOS TRANSISTOR 有权
标题翻译：制造应力增强MOS晶体管的方法
公开(公告)号：US20080102571A1
公开(公告)日：2008-05-01
申请号：US11552582
申请日：2006-10-25
申请人： James Pan
发明人： James Pan
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/66545 , H01L29/66636 , H01L29/78 , H01L29/7843 , H01L29/7848
摘要： Methods are provided for fabricating a stress enhanced MOS transistor. One such method comprises the steps of depositing and patterning a layer of sacrificial material to form a dummy gate electrode and replacing the dummy gate electrode with a stressed gate electrode. After the stressed gate electrode has been formed by a replacement process, a stress liner is deposited overlying the stressed gate electrode.
摘要翻译：提供了制造应力增强型MOS晶体管的方法。一种这样的方法包括以下步骤：沉积和图案化牺牲材料层以形成伪栅电极，并用应力栅电极代替伪栅电极。在通过更换工艺形成应力栅电极之后，将应力衬垫沉积在应力栅极上。

68. 发明授权

US07339226B2 Dual-level stacked flash memory cell with a MOSFET storage transistor 有权
标题翻译：具有MOSFET存储晶体管的双电平堆叠闪存单元
公开(公告)号：US07339226B2
公开(公告)日：2008-03-04
申请号：US11154070
申请日：2005-06-16
申请人： James Pan , Ning Cheng , Christy Mein Chu Woo
发明人： James Pan , Ning Cheng , Christy Mein Chu Woo
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , G11C16/0475 , H01L29/4234 , H01L29/66825 , H01L29/7923
摘要： The present invention is a dual-level flash memory cell design that stores 3 or more bits of information per transistor. The dual-level memory cell stores two lower bits in a first level and stores an upper bit in a second level. The lower bits are programmed, erased and read by alternate modes of operation wherein active regions operate as source and drain, and then drain and source. The upper bit is programmed and erased independent of the lower bits. However, reading of the upper bit depends upon read values of the lower bits. Additional levels are employed to store more than 3 bits of information.
摘要翻译：本发明是一种双电平闪存单元设计，其存储每个晶体管3个或更多位的信息。双级存储器单元存储第一级中的两个较低位，并将高位存储在第二级。低位通过可选的工作模式进行编程，擦除和读取，其中有源区域作为源极和漏极，然后漏极和源极工作。高位被编程和擦除，独立于低位。然而，读取较高位取决于较低位的读取值。采用附加级别来存储超过3位的信息。

69. 发明授权

US07329582B1 Methods for fabricating a semiconductor device, which include selectively depositing an electrically conductive material 有权
标题翻译：制造半导体器件的方法，其包括选择性地沉积导电材料
公开(公告)号：US07329582B1
公开(公告)日：2008-02-12
申请号：US11154785
申请日：2005-06-15
申请人： James Pan , Jonathan Byron Smith , Ming-Ren Lin
发明人： James Pan , Jonathan Byron Smith , Ming-Ren Lin
IPC分类号： H01L21/335
CPC分类号： H01L29/41775 , H01L21/2652 , H01L21/28247 , H01L21/28568 , H01L21/288 , H01L23/485 , H01L29/41783 , H01L29/66575 , H01L2924/0002 , H01L2924/00
摘要： Methods are provided for fabricating a semiconductor device having an impurity doped region in a silicon substrate. The method comprises forming a metal silicide layer electrically contacting the impurity doped region and depositing a conductive layer overlying and electrically contacting the metal silicide layer. A dielectric layer is deposited overlying the conductive layer and an opening is etched through the dielectric layer to expose a portion of the conductive layer. A conductive material is selectively deposited to fill the opening and to electrically contact the impurity doped region.
摘要翻译：提供了制造在硅衬底中具有杂质掺杂区的半导体器件的方法。该方法包括形成与杂质掺杂区电接触的金属硅化物层，并沉积覆盖并电接触金属硅化物层的导电层。沉积覆盖导电层的电介质层，并且通过电介质层蚀刻开口以暴露导电层的一部分。选择性地沉积导电材料以填充开口并与杂质掺杂区域电接触。

70. 发明申请

US20070260045A1 Secreted and transmembrane polypeptides and nucleic acids encoding the same 有权
公开(公告)号：US20070260045A1
公开(公告)日：2007-11-08
申请号：US11258348
申请日：2005-10-24
申请人： Kevin Baker , Jian Chen , Luc Desnoyers , Audrey Goddard , Paul Godowski , Austin Gurney , James Pan , Victoria Smith , Colin Watanabe , William Wood , Zemin Zhang
发明人： Kevin Baker , Jian Chen , Luc Desnoyers , Audrey Goddard , Paul Godowski , Austin Gurney , James Pan , Victoria Smith , Colin Watanabe , William Wood , Zemin Zhang
IPC分类号： C07K16/18 , C07K14/00
CPC分类号： C07K14/47 , A01K2217/075 , A01K2227/105 , A61K38/00 , C07K14/4748 , C07K14/705 , C07K14/82 , C07K16/28 , C07K2319/30 , C12Q1/6816 , C12Q1/6883 , C12Q1/6886 , C12Q2600/136 , C12Q2600/158 , G01N33/5082 , G01N33/5308 , G01N33/574 , G01N33/57419 , G01N33/57423 , G01N33/57434 , G01N33/57484 , G01N33/57488 , G01N33/57492 , G01N2500/00 , C12Q2563/131 , C12Q2527/137
摘要： The present invention is directed to novel polypeptides and to nucleic acid molecules encoding those polypeptides. Also provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptide molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention and to methods for producing the polypeptides of the present invention.

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