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61. 发明授权

US6091263A Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM 失效
公开(公告)号：US6091263A
公开(公告)日：2000-07-18
申请号：US989746
申请日：1997-12-12
申请人： Bernard J. New , Robert Anders Johnson , Ralph Wittig , Sundararajarao Mohan
发明人： Bernard J. New , Robert Anders Johnson , Ralph Wittig , Sundararajarao Mohan
IPC分类号： H03K19/177 , H03K19/173
CPC分类号： H03K19/17752 , H03K19/17756 , H03K19/1776 , H03K19/17796
摘要： A field programmable gate array (FPGA) which includes first and second arrays of configurable logic blocks, and first and second configuration cache memories coupled to the first and second arrays of configurable logic blocks, respectively. The first configuration cache memory array can either store values for reconfiguring the first array of configurable logic blocks, or operate as a RAM. Similarly, the second configuration cache array can either store values for reconfiguring the second array of configurable logic blocks, or operate as a RAM. The first configuration cache memory array and the second configuration cache memory array are independently controlled, such that partial reconfiguration of the FPGA can be accomplished. In addition, the second configuration cache memory array can store values for reconfiguring the first (rather than the second) array of configurable logic blocks, thereby providing a second-level reconfiguration cache memory.

62. 发明授权

US6054871A Method for self-reconfiguration of logic in a field programmable gate array 失效
标题翻译：用于现场可编程门阵列中逻辑的自重构的方法
公开(公告)号：US6054871A
公开(公告)日：2000-04-25
申请号：US989930
申请日：1997-12-12
申请人： Bernard J. New
发明人： Bernard J. New
IPC分类号： G06F17/50 , H03K19/177
CPC分类号： G06F17/5054
摘要： A method for controlling the operation of an FPGA. Initially, a function generator of the FPGA is configured as a ROM look up table which holds a first set of data values. These data values are selectively routed to an output terminal of the function generator in response to a plurality of input signals which are provided to the function generator. The first set of data values is selected to define a first function implemented by the function generator. Subsequently, the function generator is reconfigured as a user RAM, thereby enabling a second set of data values to be written to the function generator. The function generator is then reconfigured as a ROM look up table which holds the second set of data values. These data values are selectively routed to the output terminal of the function generator in response to the input signals provided the function generator. The second set of data values is selected to define a second function implemented by the function generator. In the foregoing manner, the function generator is dynamically reconfigured to perform different functions during normal operation of the FPGA. The function generator is reconfigured in response to configuration data stored in a local memory, thereby enabling the reconfiguration to be performed in a relatively short time period. The ability to dynamically reconfigure the function generator such that the function generator performs different functions effectively enables an increased logic density with respect to conventional FPGAs.
摘要翻译：一种用于控制FPGA操作的方法。最初，FPGA的函数发生器被配置为保持第一组数据值的ROM查找表。响应于提供给功能发生器的多个输入信号，这些数据值被选择性地路由到功能发生器的输出端。选择第一组数据值以定义由函数发生器实现的第一函数。随后，将功能发生器重新配置为用户RAM，从而使第二组数据值能够写入函数发生器。然后，函数发生器被重新配置为ROM查找表，其保存第二组数据值。响应于提供函数发生器的输入信号，这些数据值被选择性地路由到函数发生器的输出端。选择第二组数据值以定义由函数发生器实现的第二函数。以上述方式，功能发生器被动态地重新配置以在FPGA的正常操作期间执行不同的功能。响应于存储在本地存储器中的配置数据来重新配置功能发生器，从而使得能够在相对短的时间段内执行重新配置。动态重新配置函数发生器的能力使得函数发生器执行不同的功能有效地实现了相对于常规FPGA增加的逻辑密度。

63. 发明授权

US6020756A Multiplexer enhanced configurable logic block 失效
标题翻译：多路复用器增强型可配置逻辑块
公开(公告)号：US6020756A
公开(公告)日：2000-02-01
申请号：US34892
申请日：1998-03-03
申请人： Bernard J. New
发明人： Bernard J. New
IPC分类号： H03K19/177
CPC分类号： H03K19/17728 , H03K19/17732
摘要： A configurable logic block (CLB) which includes a function generator, carry logic and a first multiplexer. To operate the CLB as a multiplier, the function generator and the carry logic are each coupled to receive a first multiplier bit, a second multiplier bit and a carry signal. The function generator and carry logic are configured to provide a sum signal and a carry signal, respectively, in response to these input signals. The first multiplexer is coupled to receive the sum signal, the first multiplier bit, the second multiplier bit and a logic zero signal. The first multiplexer is controlled to pass a selected one of these signals in response to a first multiplicand bit and a second multiplicand bit. As a result, the CLB effectively creates and adds the partial products which result from multiplying the first and second multiplier bits and the first and second multiplicand bits. The carry logic takes into account the carry result from a less significant position and provides a carry result to a more significant position. The CLB can also operate as a relatively large multiplexer. In the multiplexer mode, the function generator is effectively bypassed in favor of the first multiplexer, which provides a larger multiplexing function than that normally available from the function generator. In another mode, the first multiplexer is effectively bypassed, such that the CLB operates as a conventional CLB.
摘要翻译：包括功能发生器，进位逻辑和第一多路复用器的可配置逻辑块（CLB）。为了操作CLB作为乘法器，函数发生器和进位逻辑分别被耦合以接收第一乘法器位，第二乘法器位和进位信号。函数发生器和进位逻辑被配置为分别响应于这些输入信号提供和信号和进位信号。第一多路复用器被耦合以接收和信号，第一乘法器位，第二乘法器位和逻辑零信号。控制第一复用器以响应于第一被乘数位和第二被乘数位来传递这些信号中的所选择的一个。结果，CLB有效地创建并添加由第一和第二乘法器位与第一和第二被乘数位相乘而产生的部分乘积。进位逻辑从较不重要的位置考虑进位结果，并将进位结果提供给更重要的位置。 CLB也可以作为相对较大的多路复用器工作。在多路复用器模式下，功能发生器有效地被绕过有利于第一多路复用器，其提供比通常可从函数发生器获得的更大的复用功能。在另一种模式中，第一复用器被有效地旁路，使得CLB作为传统的CLB工作。

64. 发明授权

US5956748A Asynchronous, dual-port, RAM-based FIFO with bi-directional address synchronization 失效
标题翻译：具有双向地址同步的异步，双端口，基于RAM的FIFO
公开(公告)号：US5956748A
公开(公告)日：1999-09-21
申请号：US791317
申请日：1997-01-30
申请人： Bernard J. New
发明人： Bernard J. New
IPC分类号： G06F5/10 , G11C7/00
CPC分类号： G06F5/10
摘要： A memory system having a dual port first in, first out (FIFO) memory which performs read operations in synchronism with a read clock signal and write operations in synchronism with a write clock signal. The read clock signal is asynchronous with respect to the write clock signal. A synchronizing engine is provided to synchronize a current write address with the read clock signal, thereby creating a synchronized write address. The synchronizing engine further synchronizes a current read address with the write clock signal, thereby creating a synchronized read address. The synchronized write address is compared to the current read address to determine if a FIFO empty condition exists. Similarly, the synchronized read address is compared to the current write address to determine if a FIFO full condition exists.
摘要翻译：一种具有双端口先进先出（FIFO）存储器的存储器系统，其与读时钟信号同步地执行读操作，并且与写时钟信号同步地进行写操作。读时钟信号相对于写时钟信号是异步的。提供同步引擎以使当前写入地址与读取的时钟信号同步，从而创建同步的写入地址。同步引擎进一步使当前读取地址与写入时钟信号同步，从而创建同步的读取地址。将同步写入地址与当前读取地址进行比较，以确定是否存在FIFO空条件。类似地，同步读地址与当前写地址进行比较，以确定是否存在FIFO满状态。

65. 发明授权

US5675262A Fast carry-out scheme in a field programmable gate array 失效
标题翻译：在现场可编程门阵列中的快速执行方案
公开(公告)号：US5675262A
公开(公告)日：1997-10-07
申请号：US548775
申请日：1995-10-26
申请人： Khue Duong , Stephen M. Trimberger , Bernard J. New
发明人： Khue Duong , Stephen M. Trimberger , Bernard J. New
IPC分类号： H03K19/177
CPC分类号： H03K19/17748 , H03K19/17704 , H03K19/17736
摘要： A fast carry-out scheme in a field programmable logic array. The configurable logic blocks (CLBs) are arranged in columns. The carry-out signals are routed from the bottom CLB of a column to the top CLB of that column. The carry-out from the top-most CLB is then multiplexed onto a clock line that is normally used to conduct clocking signals to the CLBs. Instead of conducting clocking signals, the existing clock line is now used to route the carry-out signal onto a vertical longline spanning the entire height of the column. Eventually, the carry-out signal is routed from the longline to its destination CLB of the adjacent column via local interconnect resources.
摘要翻译：现场可编程逻辑阵列中的快速实现方案。可配置逻辑块（CLB）按列排列。进位信号从列的底部CLB路由到该列的顶部CLB。然后，最顶层CLB的进位复用到通常用于向CLB传送时钟信号的时钟线上。现在的时钟线代替传输时钟信号，而不是用于将进位信号路由到跨越列的整个高度的垂直延长线。最终，进位信号通过局部互连资源从延长线路路由到相邻列的目的地CLB。

66. 发明授权

US5629886A Method and structure for providing fast propagation of a carry signal in a field programmable gate array 失效
标题翻译：用于提供现场可编程门阵列中进位信号的快速传播的方法和结构
公开(公告)号：US5629886A
公开(公告)日：1997-05-13
申请号：US494131
申请日：1995-06-23
申请人： Bernard J. New
发明人： Bernard J. New
IPC分类号： G06F7/50 , G06F7/503 , H03K19/173
CPC分类号： G06F7/503 , G06F7/507 , H03K19/1737 , H03K19/17728 , H03K19/17736 , G06F2207/4812
摘要： A carry logic circuit for a field programmable gate array (FPGA) which allows a carry input signal to be propagated through the carry logic circuit without passing through a multiplexer of another series connected circuit element. The carry logic circuit uses a function generator of the FPGA to provide a propagate signal in response to first and second input signals provided to the carry logic circuit. Also described are methods for performing a carry logic function in an FPGA.
摘要翻译：用于现场可编程门阵列（FPGA）的进位逻辑电路，其允许进位输入信号通过进位逻辑电路传播而不通过另一串联电路元件的多路复用器。进位逻辑电路使用FPGA的函数发生器来响应于提供给进位逻辑电路的第一和第二输入信号来提供传播信号。还描述了在FPGA中执行进位逻辑功能的方法。

67. 发明授权

US5578946A Input synchronization mechanism for inside/outside clock 失效
标题翻译：内/外时钟输入同步机制
公开(公告)号：US5578946A
公开(公告)日：1996-11-26
申请号：US539982
申请日：1995-10-06
申请人： Richard A. Carberry , Bernard J. New
发明人： Richard A. Carberry , Bernard J. New
IPC分类号： G06F1/12 , H03K19/096 , H03K19/177
CPC分类号： G06F1/12
摘要： A synchronization mechanism for synchronizing an outside clock with a delayed inside clock is provided. The delayed inside clock is distributed across a network of clock lines within the integrated circuit to deskew the clock signal at the supply points. Although the inside clock signal is deskewed, it is nevertheless delayed compared to an input clock signal provided by a pad of the integrated circuit. A distribution line provided on the periphery of the integrated circuit supplies an outside clock signal that is not substantially delayed compared to the input clock signal at the IC's pad. The synchronization mechanism provides synchronization between the outside clock, as received by an input/output block, and the inside clock. The synchronization is required because configurable logic blocks (CLBs) of the IC are typically referenced by the delayed inside clock. The IC can offer significantly reduced chip hold time on input data by referencing the outside clock while supplying data internally using the inside clock reference.
摘要翻译：提供了一种用于使外部时钟与延迟的内部时钟同步的同步机制。延迟的内部时钟分布在集成电路内的时钟线网络上以使供电点处的时钟信号偏斜。虽然内部时钟信号是去校正的，但是与由集成电路的焊盘提供的输入时钟信号相比，它仍然被延迟。设置在集成电路的外围的配电线路提供与IC芯片的输入时钟信号相比基本不延迟的外部时钟信号。同步机制提供由输入/输出块接收的外部时钟与内部时钟之间的同步。需要同步，因为IC的可配置逻辑块（CLB）通常由延迟的内部时钟引用。通过参考外部时钟，IC可以在内部使用内部时钟参考提供数据的同时，在输入数据上大大减少芯片保持时间。

68. 发明授权

US5553301A Programmable sequencher having internal components which are microprocessor read/write interfacable 失效
标题翻译：具有内部组件的可编程顺控程序，它们是微处理器读/写可互操作的
公开(公告)号：US5553301A
公开(公告)日：1996-09-03
申请号：US24819
申请日：1993-03-01
申请人： Bernard J. New , Philip Freidin
发明人： Bernard J. New , Philip Freidin
IPC分类号： G06F9/26 , G06F9/22 , G06F11/36 , G06F13/20
CPC分类号： G06F9/22 , G06F11/3648
摘要： A single-chip microprogrammable sequencer (10) provides a bus (12) for connection of an external microprocessor. The sequencer includes a register file (40) which consists of a number of registers accessible to the microprocessor by which the microprocessor can monitor and control operation of the sequencer. The sequencer also includes a writeable control store (52) which is accessible to the microprocessor. Microinstructions may be written to the store by the microprocessor so that selected programs or program segments will be executed by the sequencer. A breakpoint register (104), included in the register file, is used in conjunction with a program counter portion of the sequencer providing a breakpoint facility for the microprocessor. Similarly, start, halt, reset and single-step operations may be performed by the sequencer under control of the microprocessor.
摘要翻译：单片微程序定序器（10）提供用于连接外部微处理器的总线（12）。定序器包括寄存器文件（40），寄存器文件（40）由微处理器可访问的多个寄存器组成，微处理器可以通过该寄存器文件监视和控制定序器的操作。定序器还包括可由微处理器访问的可写控制存储器（52）。微指令可以由微处理器写入存储器，以便选定的程序或程序段将由定序器执行。包括在寄存器文件中的断点寄存器（104）与定序器的程序计数器部分结合使用，为微处理器提供断点设备。类似地，在微处理器的控制下，定序器可以执行启动，停止，复位和单步操作。

69. 发明授权

US5528169A Method and structure for providing a flip flop circuit with a configurable data input path 失效
标题翻译：提供具有可配置数据输入路径的触发电路的方法和结构
公开(公告)号：US5528169A
公开(公告)日：1996-06-18
申请号：US430510
申请日：1995-04-26
申请人： Bernard J. New
发明人： Bernard J. New
IPC分类号： H03K3/037 , H03K19/0175
CPC分类号： H03K3/037
摘要： A method and structure for a configurable flip flop circuit. The configurable flip flop circuit includes a flip flop, a first signal line for receiving a first signal, a second signal line for receiving a second signal, a first enable line for receiving a first enable signal, a second enable line for receiving a second enable signal, a programmable logic circuit and a multiplexer circuit. The programmable logic circuit receives the first and second enable signals from the first and second enable lines. In response, the programmable logic circuit generates multiplexer control signals which are provided to the multiplexer circuit. The multiplexer circuit selectably couples the first signal line, the second signal line, and the output terminal of the flip flop to the flip flop input terminal in response to the multiplexer control signals. The programmable logic circuit can be programmed to provide different multiplexer control signals in response to the same first and second enable signals, thereby advantageously allowing the priority of the first and second enable signals to be selected.
摘要翻译：一种可配置触发电路的方法和结构。可配置触发器电路包括触发器，用于接收第一信号的第一信号线，用于接收第二信号的第二信号线，用于接收第一使能信号的第一使能线，用于接收第二使能的第二使能线信号，可编程逻辑电路和多路复用器电路。可编程逻辑电路从第一和第二使能线接收第一和第二使能信号。作为响应，可编程逻辑电路产生提供给多路复用器电路的多路复用器控制信号。多路复用器电路响应于多路复用器控制信号将第一信号线，第二信号线和触发器的输出端可选地耦合到触发器输入端。可编程逻辑电路可被编程为响应于相同的第一和第二使能信号而提供不同的多路复用器控制信号，从而有利地允许选择第一和第二使能信号的优先级。

70. 发明授权

US5349250A Logic structure and circuit for fast carry 失效
标题翻译：逻辑结构和电路快速携带
公开(公告)号：US5349250A
公开(公告)日：1994-09-20
申请号：US116659
申请日：1993-09-02
申请人： Bernard J. New
发明人： Bernard J. New
IPC分类号： G06F7/50 , G06F7/503 , G06F7/506 , H03K19/173 , H03K19/177 , H03K19/00 , H03K17/693
CPC分类号： G06F7/503 , H03K19/1737 , H03K19/17704 , H03K19/17728 , H03K19/17732 , G06F2207/4812
摘要： Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The invention takes advantage of the fact that a carry signal to be added to two bits can be propagated to the next more significant bit when the two binary bits to be added are unequal, and that one of the bits can serve as the carry signal when the bits are equal. For each bit, a carry propagate signal is generated by a lookup table programmable function generator and is used by dedicated hardware to generate the carry signal.
摘要翻译：使用包括组合函数发生器和存储元件的多个块并且通过可编程互连结构互连的可编程逻辑器件，用于执行使用用于产生进位功能的逻辑的算术功能。当要处理大量的位时，进位功能通常会导致显着的延迟或需要大量附加组件以高速获得结果。本发明提供逻辑块内的专用硬件，用于快速执行进位功能并具有最少数量的部件。本发明利用以下事实：当要添加的两个二进制位不相等时，要添加到两个位的进位信号可以被传播到下一个更高有效位，并且该位中的一个可以用作进位信号，当这些位是相等的。对于每个位，进位传播信号由查找表可编程函数发生器产生，并被专用硬件用于生成进位信号。

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