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61. 发明申请

US20120001249A1 ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE & METHOD OF MAKING THEREOF 有权
标题翻译：超高密度垂直NAND存储器件及其制造方法
公开(公告)号：US20120001249A1
公开(公告)日：2012-01-05
申请号：US12827761
申请日：2010-06-30
申请人： Johann Alsmeier , George Samachisa
发明人： Johann Alsmeier , George Samachisa
IPC分类号： H01L27/115 , H01L29/792 , H01L21/8246 , H01L21/8247 , H01L29/788
CPC分类号： H01L27/11582 , H01L21/28273 , H01L21/28282 , H01L27/11517 , H01L27/11519 , H01L27/11551 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11578 , H01L29/42324 , H01L29/4234 , H01L29/4916 , H01L29/495 , H01L29/66825 , H01L29/66833 , H01L29/7883 , H01L29/7889 , H01L29/7926
摘要： Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.
摘要翻译：单片三维NAND串包括半导体通道，半导体通道的至少一个端部基本上垂直于基板的主表面延伸，多个控制栅电极具有基本上平行于基板的主表面延伸的带状衬底，所述阻挡电介质包括多个阻挡电介质段，多个离散电荷存储段和位于所述多个离散电荷存储段和所述半导体通道中的每一个之间的隧道电介质。

62. 发明授权

US07256440B2 Semiconductor memory cell having a trench and a planar selection transistor and method for producing the same 有权
标题翻译：具有沟槽和平面选择晶体管的半导体存储单元及其制造方法
公开(公告)号：US07256440B2
公开(公告)日：2007-08-14
申请号：US10913797
申请日：2004-08-06
申请人： Johann Alsmeier
发明人： Johann Alsmeier
IPC分类号： H01L27/108
CPC分类号： H01L27/10867 , H01L21/26506 , H01L21/26586
摘要： A trench (12) of a semiconductor memory cell (1) has an insulation collar (44), which is open toward the substrate (42) on just one side (50). On the other side (52), the insulation collar (44, 47, 55) rises all the way up to the insulation cover (62). There is therefore no need for a shallow trench isolation. The contact (70) which is buried on one side is formed by oblique implantation, for example with N2 or argon, the implantation taking place from a fixedly predetermined direction with an angle of inclination of between 15 and 40°. The implantation substances effect different etching or oxidation properties, etc., of the implanted materials. In combination with this method, it becomes possible to realize a new layout for the semiconductor memory cell (1), in which the structures for forming the active areas form long lines (31) extending over a plurality of adjacent semiconductor memory cells.
摘要翻译：半导体存储单元（1）的沟槽（12）具有绝缘套环（44），其仅在一侧（50）朝向衬底（42）开口。在另一侧（52）上，绝缘套环（44,47,55）一直上升到绝缘盖（62）。因此，不需要浅沟槽隔离。埋设在一侧的触点（70）通过倾斜注入形成，例如用N 2或氩形成的，注入是从固定的预定方向发生，倾斜角介于15和 40°。植入物质影响植入材料的不同蚀刻或氧化性能等。结合该方法，可以实现用于形成有源区域的结构形成在多个相邻半导体存储单元上延伸的长线（31）的半导体存储单元（1）的新布局。

63. 发明申请

US20050148178A1 METHOD FOR FABRICATING A P-CHANNEL FIELD-EFFECT TRANSISTOR ON A SEMICONDUCTOR SUBSTRATE 失效
标题翻译：在半导体基板上制造P沟道场效应晶体管的方法
公开(公告)号：US20050148178A1
公开(公告)日：2005-07-07
申请号：US10372989
申请日：2003-02-24
申请人： Johann Alsmeier , Jurgen Faul
发明人： Johann Alsmeier , Jurgen Faul
IPC分类号： H01L21/8238 , H01L29/49 , H01L29/78 , H01L21/302 , H01L21/461
CPC分类号： H01L29/4916 , H01L21/823842 , H01L29/7838 , Y10S438/91 , Y10S438/918 , Y10S438/919
摘要： A p-channel field-effect transistor is formed on a semiconductor substrate. The transistor has an n-doped gate electrode, a buried channel, a p-doped source and a p-doped drain. The transistor is fabricated by a procedure in which, after an implantation for defining an n-type well, an oxidation is performed to form a gate-oxide layer and n-doped polysilicon is subsequently deposited. The latter is doped with boron or boron fluoride particles either in situ or by a dedicated implantation step. In a thermal process, the boron acceptors penetrate through the oxide layer into the substrate of the n-type well, where they form a p-doped zone, which serves for counter doping and sets the threshold voltage. This results in a steep profile that permits a shallow buried channel. The control of the number particles penetrating through the oxide layer is achieved by nitriding the oxide layer in an N2O atmosphere.
摘要翻译：在半导体衬底上形成p沟道场效应晶体管。晶体管具有n掺杂栅电极，掩埋沟道，p掺杂源和p掺杂漏极。晶体管的制造方法是，在用于限定n型阱的注入之后，执行氧化以形成栅氧化层，随后沉积n掺杂多晶硅。后者在原位或通过专用注入步骤掺杂硼或氟化硼颗粒。在热处理中，硼受体穿过氧化物层进入n型阱的衬底，其中它们形成p掺杂区，用于反掺杂并设置阈值电压。这导致一个陡峭的轮廓，允许一个浅埋的通道。穿过氧化物层的数量颗粒的控制通过在N 2 O 2气氛中氮化氧化物层来实现。

64. 发明授权

US06518145B1 Methods to control the threshold voltage of a deep trench corner device 失效
标题翻译：控制深沟槽角设备阈值电压的方法
公开(公告)号：US06518145B1
公开(公告)日：2003-02-11
申请号：US09130226
申请日：1998-08-06
申请人： Johann Alsmeier , George R. Goth , Max G. Levy , Victor R. Nastasi , James A. O'Neill , Paul C. Parries
发明人： Johann Alsmeier , George R. Goth , Max G. Levy , Victor R. Nastasi , James A. O'Neill , Paul C. Parries
IPC分类号： H01L2176
CPC分类号： H01L21/763 , H01L21/823481
摘要： A method of manufacturing a semiconductor trench device comprises forming a dielectric on a substrate, the dielectric having an underlying oxide layer adjacent the substrate, etching a trench in the dielectric and the substrate, forming a recess in the underlying oxide layer, filling the recess with a nitride plug, filling the trench a conductive material and oxidizing the dielectric and the conductive material, wherein the nitride plug controls a shape of a corner of the trench.
摘要翻译：制造半导体沟槽器件的方法包括在衬底上形成电介质，所述电介质具有与衬底相邻的下面的氧化物层，蚀刻电介质和衬底中的沟槽，在下面的氧化物层中形成凹陷，用氮化物塞，将沟槽填充导电材料并氧化电介质和导电材料，其中氮化物塞控制沟槽角部的形状。

65. 发明授权

US06399977B1 Reducing oxidation stress in the fabrication of devices 失效
标题翻译：在器件制造中减少氧化应力
公开(公告)号：US06399977B1
公开(公告)日：2002-06-04
申请号：US09452217
申请日：1999-12-01
申请人： Johann Alsmeier
发明人： Johann Alsmeier
IPC分类号： H01L27108
CPC分类号： H01L27/10861 , H01L27/10829
摘要： A random access memory cell having a trench capacitor formed below the surface of the substrate. A shallow trench isolation is provided to isolate the memory cell from other memory cells of a memory array. The shallow trench isolation includes a top surface raised above the substrate to reduce oxidation stress.
摘要翻译：一种随机存取存储单元，其具有形成在衬底表面下方的沟槽电容器。提供浅沟槽隔离以将存储器单元与存储器阵列的其它存储器单元隔离。浅沟槽隔离包括在衬底上方升高的顶表面以减少氧化应力。

66. 发明授权

US06355954B1 Device with asymmetrical channel dopant profile 有权
标题翻译：具有不对称沟道掺杂剂分布的器件
公开(公告)号：US06355954B1
公开(公告)日：2002-03-12
申请号：US09251616
申请日：1999-02-17
申请人： Martin Gall , Johann Alsmeier
发明人： Martin Gall , Johann Alsmeier
IPC分类号： H01L21108
CPC分类号： H01L27/10861 , H01L21/26586 , H01L27/10829 , H01L27/10867 , H01L27/10873 , H01L27/10888 , H01L29/1045 , H01L29/66181 , H01L29/66492 , H01L29/66537 , Y10S257/905
摘要： A method for fabricating a bit line junction in a DRAM array device which improves the doping profile in the channel region. The method includes contradoping via ion implantation through the bit line contact opening made in the device during processing. This particular doping method increases the concentration of dopants in the channel region on the bit line side of the array, without a corresponding increase of dopants on the buried strap side. Such a doping profile results in an improvement in the off current behavior of the device. Depending on the aspect ratio of the contact opening, tilt angles for the ion implantation are possible and can be adjusted for maximum off current efficiency.
摘要翻译：一种在DRAM阵列器件中制造位线结的方法，其改善了沟道区中的掺杂分布。该方法包括通过在处理期间在器件中形成的位线接触开口的离子注入相矛盾。这种特殊的掺杂方法增加阵列位线侧的沟道区中的掺杂剂的浓度，而不会使掩埋带侧上的掺杂剂相应增加。这种掺杂特征导致器件的截止电流特性的改善。根据接触开口的纵横比，用于离子注入的倾斜角是可能的，并且可以针对最大关断电流效率进行调整。

67. 发明授权

US06339239B1 DRAM cell layout for node capacitance enhancement 失效
标题翻译： DRAM单元布局用于节点电容增强
公开(公告)号：US06339239B1
公开(公告)日：2002-01-15
申请号：US09603439
申请日：2000-06-23
申请人： Johann Alsmeier , Carl John Radens
发明人： Johann Alsmeier , Carl John Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10841 , H01L27/10829
摘要： A layout pattern for increasing the spacing between the deep trenches of one cell pair and the deep trenches of an adjacent cell pair in an array of semiconductor DRAM cell pairs each of which cell pairs share a common bitline contact to bitlines arranged in one direction and each of which cell pairs are coupled to gate conductors arranged orthogonal to the bitlines. The layout pattern is formed by positioning the deep trenches of all of said pairs along alternate bitlines so they are offset from said bitlines along gate conductors in opposing directions. The deep trenches of all of the remaining bitlines are offset from said bitlines in opposing directions opposite to the opposing directions of said trenches along said alternate bitlines so as to form a herringbone pattern of cells.
摘要翻译：一种用于增加一个单元对的深沟槽和半导体DRAM单元对阵列中的相邻单元对的深沟槽之间的间隔的布局图案，每个单元对中的每一个单元对共享与沿一个方向排列的位线的公共位线接触其中单元对耦合到正交于位线布置的栅极导体。通过将所有对的深沟槽沿着交替位线定位，使得它们沿相反方向沿着栅极导体偏离所述位线而形成布局图案。所有剩余位线的深沟槽在与所述沟槽沿着所述替代位线的相反方向相反的相对方向上偏离所述位线，以便形成单元格的人字形图案。

68. 发明授权

US06235574B1 High performance DRAM and method of manufacture 失效
标题翻译：高性能DRAM及其制造方法
公开(公告)号：US06235574B1
公开(公告)日：2001-05-22
申请号：US09568064
申请日：2000-05-10
申请人： Dirk Többen , Johann Alsmeier
发明人： Dirk Többen , Johann Alsmeier
IPC分类号： H01L27108
CPC分类号： H01L27/10894
摘要： A process for forming a DRAM in a silicon chip that includes N-MOSFETs of the memory cells in its central area and C-MOSFETs of the support circuitry in the peripheral area. By the inclusion of a masking oxide layer over the peripheral area during the formation of the memory cells, there are formed N-MOSFETs that use N-doped polycide gates and P-MOSFETs that use P-doped polycide gates. The sources and drains include self-aligned silicide contacts.
摘要翻译：一种用于在硅芯片中形成DRAM的方法，该芯片包括其中心区域中的存储器单元的N-MOSFET和外围区域中的支持电路的C-MOSFET。通过在存储单元的形成期间在外围区域上包括掩蔽氧化物层，形成使用N掺杂多晶硅栅极的N-MOSFET和使用P掺杂多晶硅栅极的P-MOSFET。源极和漏极包括自对准硅化物触点。

69. 发明授权

US06174756B1 Spacers to block deep junction implants and silicide formation in integrated circuits 失效
标题翻译：在集成电路中阻挡深结植入物和硅化物形成的间隔物
公开(公告)号：US06174756B1
公开(公告)日：2001-01-16
申请号：US08940236
申请日：1997-09-30
申请人： Jeffrey P. Gambino , Johann Alsmeier , Gary Bronner
发明人： Jeffrey P. Gambino , Johann Alsmeier , Gary Bronner
IPC分类号： H01L2100
CPC分类号： H01L27/10844 , H01L21/823418
摘要： An efficient method of forming deep junction implants in one region without affecting the implant of a second region of an integrated circuit is provided. This is achieved by forming spacers of deep junction devices with the same material used to fill the gaps of shallow junction devices.
摘要翻译：提供了在一个区域内形成深结植入物而不影响集成电路的第二区域的植入的有效方法。这通过用与填充浅结设备的间隙的相同材料形成深接合器件的间隔件来实现。

70. 发明授权

US6080618A Controllability of a buried device layer 失效
标题翻译：埋设器层的可控性
公开(公告)号：US6080618A
公开(公告)日：2000-06-27
申请号：US52683
申请日：1998-03-31
申请人： Wolfgang Bergner , Johann Alsmeier
发明人： Wolfgang Bergner , Johann Alsmeier
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L2/8242
CPC分类号： H01L27/10867
摘要： Reduced variations in buried layer across the chip is provided. The reduction in variation is achieved by defining the top surface of the buried layer and then the lower surface of the buried layer. This results in improved control buried strap variations, thereby improving performance of the IC.
摘要翻译：提供了跨芯片的掩埋层的减小的变化。通过限定掩埋层的顶表面，然后限定掩埋层的下表面来实现变化的减小。这导致改进的控制掩埋带变化，从而提高IC的性能。

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