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61. 发明申请

US20080279017A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20080279017A1
公开(公告)日：2008-11-13
申请号：US12149549
申请日：2008-05-05
申请人： Hiroki Shimano , Kazutami Arimoto
发明人： Hiroki Shimano , Kazutami Arimoto
IPC分类号： G11C7/00 , G11C5/14 , G11C8/00
CPC分类号： G11C5/14 , G11C5/063 , G11C5/148 , G11C11/406 , G11C11/4074 , G11C2211/4067
摘要： During a stand-by state in which power supply is cut off, a high-voltage power supply control circuit isolates a global negative voltage line transmitting a negative voltage and a local negative voltage line provided corresponding to each respective sub array block from each other and isolates a global ground line and a local ground line transmitting a ground voltage from each other. These local ground line and local negative voltage line are charged to a high voltage level through a high voltage line before cut-off from the corresponding power supply. A leakage current path from a word line to the negative voltage line or the ground line is cut off, so that the word line in a non-selected state can reliably be maintained at a non-selection voltage. Thus, in a low power consumption stand-by mode, data stored in a memory cell can be held in a stable manner.
摘要翻译：在电源被切断的待机状态下，高电压电源控制电路将发送负电压的全局负电压线与对应于每个各个子阵列块的局部负电压线相互隔离，隔离全球接地线和传输地电压的局部接地线。这些本地接地线和局部负电压线在从相应电源切断之前通过高压线充电到高电压电平。从字线到负电压线或接地线的漏电流路径被切断，使得未选择状态的字线可以可靠地保持在非选择电压。因此，在低功耗待机模式中，可以以稳定的方式保存存储在存储单元中的数据。

62. 发明申请

US20080175038A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20080175038A1
公开(公告)日：2008-07-24
申请号：US11819583
申请日：2007-06-28
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C11/24 , G11C5/10
CPC分类号： G11C7/18 , G11C8/14 , G11C11/4085 , G11C11/4087 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/108 , H01L27/1085 , H01L27/10873 , H01L27/10882
摘要： Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus. a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.
摘要翻译：构成存储单元板的导体线的导电线和构成存储单元板电极的导线被形成在包括多个存储单元的存储器件的同一互连层中，每个存储单元均包括用于以电荷形式存储数据的电容器。通过将存储单元的电容器形成为平面电容器配置，由于电容器而导致的步骤被去除。从而。可以通过CMOS工艺形成动态半导体存储器件，并且实现适合于与逻辑并入的动态半导体存储器件。 1位的数据由两个存储单元存储，即使由于平面型电容器而使存储单元的电容值减小，也可以可靠地存储数据。

63. 发明申请

US20060193164A1 Semiconductor memory device 失效
公开(公告)号：US20060193164A1
公开(公告)日：2006-08-31
申请号：US11397811
申请日：2006-04-05
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C11/24
CPC分类号： G11C7/18 , G11C8/14 , G11C11/4085 , G11C11/4087 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/108 , H01L27/1085 , H01L27/10873 , H01L27/10882
摘要： Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus. a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.

64. 发明申请

US20050018471A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20050018471A1
公开(公告)日：2005-01-27
申请号：US10922936
申请日：2004-08-23
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C11/401 , G11C11/404 , G11C11/405 , G11C11/407 , G11C11/409 , G11C11/4097 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C11/24
CPC分类号： G11C7/18 , G11C8/14 , G11C11/4085 , G11C11/4087 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/108 , H01L27/1085 , H01L27/10873 , H01L27/10882
摘要： Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus, a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.
摘要翻译：构成存储单元板的导体线的导电线和构成存储单元板电极的导线被形成在包括多个存储单元的存储器件的同一互连层中，每个存储单元均包括用于以电荷形式存储数据的电容器。通过将存储单元的电容器形成为平面电容器配置，由于电容器而导致的步骤被去除。因此，可以通过CMOS工艺形成动态半导体存储器件，并且实现适合于与逻辑合并的动态半导体存储器件。 1位的数据由两个存储单元存储，即使由于平面型电容器而使存储单元的电容值减小也可以可靠地存储数据。

65. 发明授权

US06597599B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US06597599B2
公开(公告)日：2003-07-22
申请号：US10188977
申请日：2002-07-05
申请人： Toshinori Morihara , Hiroki Shimano , Katsumi Dosaka , Kazutami Arimoto
发明人： Toshinori Morihara , Hiroki Shimano , Katsumi Dosaka , Kazutami Arimoto
IPC分类号： G11C1124
CPC分类号： H01L27/10805 , H01L27/0207 , H01L27/10897
摘要： In a semiconductor memory in which memory cells where a bit line is connected with the impurity diffused area of MOS transistors are arranged in a close packed layout in order to reduce the gate capacitance and junction capacitance of the impurity diffused area of the MOS transistor, the width W1 of the active region of the MOS transistor of field pattern FL constituting the memory cell is formed narrower than the width W2 of the active region of the capacitor.
摘要翻译：在半导体存储器中，其中位线与MOS晶体管的杂质扩散区域连接的存储器单元以紧密堆积布置布置，以便降低MOS晶体管的杂质扩散区域的栅极电容和结电容，构成存储单元的场图案FL的MOS晶体管的有源区域的宽度W1形成为比电容器的有源区域的宽度W2窄。

66. 发明授权

US06477108B2 Semiconductor device including memory with reduced current consumption 失效
标题翻译：包括具有降低的电流消耗的存储器的半导体器件
公开(公告)号：US06477108B2
公开(公告)日：2002-11-05
申请号：US09775712
申请日：2001-02-05
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C800
CPC分类号： G11C7/225 , G11C7/1072 , G11C7/22 , G11C8/18 , G11C11/4076 , G11C11/4082 , G11C11/4087 , G11C2207/104
摘要： When a row active command ACT_CMD is externally input, an internal clock control circuit activates a signal int.CKE, so that an external clock signal ext.CLK is responsively supplied to an internal memory array as signal int.CLK. Thus, clock control is meticulously conducted, whereby a system LSI with reduced current consumption in the memory array can be realized.
摘要翻译：当外部输入一行有效命令ACT_CMD时，内部时钟控制电路激活信号int.CKE，使外部时钟信号ext.CLK作为信号int.CLK响应地提供给内部存储器阵列。因此，精确地进行时钟控制，由此可以实现在存储器阵列中具有降低的电流消耗的系统LSI。

67. 发明授权

US06414890B2 Semiconductor memory device capable of reliably performing burn-in test at wafer level 失效
标题翻译：能够在晶片级可靠地进行老化测试的半导体存储器件
公开(公告)号：US06414890B2
公开(公告)日：2002-07-02
申请号：US09739350
申请日：2000-12-19
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C700
CPC分类号： G11C29/28 , G11C11/401 , G11C29/50
摘要： In a word line drive circuit for driving a word line to a boosted voltage level, a drive signal that is activated in response to a wafer burn-in signal is applied to the gate of a transistor for preventing the floating state of the word line. Even if a boost signal is transmitted to a corresponding word line through a word line driver circuit, the floating state prevention transistor can be turned off at high speed, an electric charge flow path can be cut off, and the word line can be driven reliably to the boosted voltage level. Therefore, reliable burn-in can be implemented.
摘要翻译：在用于将字线驱动到升压电压电平的字线驱动电路中，响应于晶片老化信号而被激活的驱动信号被施加到用于防止字线的浮置状态的晶体管的栅极。即使通过字线驱动电路将升压信号发送到对应的字线，也可以高速关闭浮置状态防止晶体管，能够切断电荷流路，可以可靠地驱动字线到升压电平。因此，可以实现可靠的老化。

68. 发明授权

US06400628B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06400628B2
公开(公告)日：2002-06-04
申请号：US09748139
申请日：2000-12-27
申请人： Katsumi Dosaka , Hiroki Shimano , Hiroki Sugano , Kazutami Arimoto
发明人： Katsumi Dosaka , Hiroki Shimano , Hiroki Sugano , Kazutami Arimoto
IPC分类号： G11C702
CPC分类号： H01L27/10882 , G11C7/12 , G11C7/14 , G11C7/18 , H01L27/10885 , H01L27/10894
摘要： A dummy bit line is formed from the same layer as and separately from a bit line, and is running in parallel with the bit line. Capacitor is formed on the layer upper than bit line and has a cell plate. An intermediate interconnection is formed on the layer upper than capacitor and is electrically connected to cell plate and dummy bit line. Thus, a semiconductor memory device is obtained in which a cell plate voltage can reliably be fed to a cell plate while preventing the increase of the area of a chip.
摘要翻译：虚位线与位线相同层分开形成，与位线并行运行。电容器形成在比位线上方的层上并且具有单元板。中间互连形成在电容层上方，电连接到单元板和虚拟位线。因此，获得半导体存储器件，其中可以可靠地将电池板电压馈送到电池板，同时防止芯片面积的增加。

69. 发明授权

US06178122B1 Boosted-voltage drive circuit operable with high reliability and semiconductor memory device employing the same 失效
公开(公告)号：US06178122B1
公开(公告)日：2001-01-23
申请号：US09212313
申请日：1998-12-16
申请人： Shigeki Tomishima , Tsukasa Ooishi , Hiroki Shimano
发明人： Shigeki Tomishima , Tsukasa Ooishi , Hiroki Shimano
IPC分类号： G11C700
CPC分类号： G11C8/08 , G11C11/4076 , G11C11/4085
摘要： A sub word line is selected when an associated word line and any of sub decode lines are driven to attain a boosted potential. In a sub decoder selectively driving any of the sub decode lines, the pull-down transistors allowing the sub decode line to discharge are turned on successively with time in a pulsing manner.

70. 发明授权

US5249215A X-ray exposure system with curved reflecting mirrors 失效
标题翻译：具有弯曲反射镜的X射线曝光系统
公开(公告)号：US5249215A
公开(公告)日：1993-09-28
申请号：US848312
申请日：1992-03-09
申请人： Hiroki Shimano
发明人： Hiroki Shimano
IPC分类号： G03F7/20 , G21K1/06 , H01L21/027 , H01L21/30 , H05H13/04
CPC分类号： G03F7/702
摘要： X-ray exposure equipment which can effectively converge a synchrotron radiation, which tends to diverge to a great extent in a horizontal direction, to assure a sufficiently high intensity on a lithographic plane and can irradiate X-rays perpendicularly to a full lateral extent of the lithographic plane over an entire exposure area. The X-ray exposure equipment comprises a point X-ray source and a first reflecting mirror having first and second point focuses and disposed such that the first focal point coincides with the location of the X-ray source so as to focus X-rays to the second focal point. A second reflecting mirror is disposed such that the focus thereof substantially coincides with the second focal point of the first reflecting mirror so as to collimate X-rays received from the first reflecting mirror by way of the focusing property thereof in parallel to a principal optical axis of an optical system for X-rays which includes the first and second reflecting mirrors. The parallel X-rays from the second reflecting mirror are irradiated perpendicularly to a lithographic plane.
摘要翻译：可以有效地收敛在水平方向上大幅度分散的同步加速器辐射的X射线曝光设备，以确保在平版印刷平面上具有足够高的强度，并能够垂直于X射线的全部横向辐射X射线在整个曝光区域的平版印刷平面。 X射线曝光设备包括点X射线源和具有第一和第二点聚焦的第一反射镜，并且被布置成使得第一焦点与X射线源的位置一致，以将X射线聚焦到第二个焦点。第二反射镜被设置为使得其焦点基本上与第一反射镜的第二焦点重合，以便通过其聚焦特性将从第一反射镜接收到的X射线平行于主光轴包括第一和第二反射镜的用于X射线的光学系统。来自第二反射镜的平行X射线垂直于光刻平面照射。

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