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1. 发明授权

US06597599B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US06597599B2
公开(公告)日：2003-07-22
申请号：US10188977
申请日：2002-07-05
申请人： Toshinori Morihara , Hiroki Shimano , Katsumi Dosaka , Kazutami Arimoto
发明人： Toshinori Morihara , Hiroki Shimano , Katsumi Dosaka , Kazutami Arimoto
IPC分类号： G11C1124
CPC分类号： H01L27/10805 , H01L27/0207 , H01L27/10897
摘要： In a semiconductor memory in which memory cells where a bit line is connected with the impurity diffused area of MOS transistors are arranged in a close packed layout in order to reduce the gate capacitance and junction capacitance of the impurity diffused area of the MOS transistor, the width W1 of the active region of the MOS transistor of field pattern FL constituting the memory cell is formed narrower than the width W2 of the active region of the capacitor.
摘要翻译：在半导体存储器中，其中位线与MOS晶体管的杂质扩散区域连接的存储器单元以紧密堆积布置布置，以便降低MOS晶体管的杂质扩散区域的栅极电容和结电容，构成存储单元的场图案FL的MOS晶体管的有源区域的宽度W1形成为比电容器的有源区域的宽度W2窄。

2. 发明授权

US06459113B1 Semiconductor integrated circuit device and method of manufacturing the same, and cell size calculation method for DRAM memory cells 失效
标题翻译：半导体集成电路器件及其制造方法，以及DRAM存储单元的单元尺寸计算方法
公开(公告)号：US06459113B1
公开(公告)日：2002-10-01
申请号：US09760804
申请日：2001-01-17
申请人： Toshinori Morihara , Hiroki Shimano , Kazutami Arimoto
发明人： Toshinori Morihara , Hiroki Shimano , Kazutami Arimoto
IPC分类号： H01L27108
CPC分类号： H01L27/10805 , H01L27/0207
摘要： There is provided a semiconductor integrated circuit device comprising: a field placement creating a field pattern in an array form by closest packing on a first conductance-type semiconductor substrate, the field pattern including a plurality of memory cells which define an active area and a device isolation region of a field effect transistor, and which are arranged in a predetermined pitch in the longitudinal and transverse directions, respectively, each memory cell having a pattern of a certain length-to-width size; a cell plate placement providing a capacitor structure between a second conductance-type diffusion region formed by an impurity implant to the active area and a cell plate electrode formed so as to cover part of the active area with a predetermined cell plate pattern through a capacitor dielectric, the cell plate pattern extending in the transverse direction with a certain length size; and a word line placement in which a word line pattern is arranged in the transverse direction of a vacant zone of the active area in which the cell plate electrode is not formed and serves as a gate electrode of the field effect transistor on the active area, the word line pattern being formed through a gate oxide at a predetermined interval, wherein the layout of a cell array of the memory cells is provided by a closest packing cell configuration.
摘要翻译：提供了一种半导体集成电路器件，包括：场放置，通过在第一导电型半导体衬底上的最密堆积产生阵列形式的场图案，场图案包括限定有源区域的多个存储单元和器件隔离区域，并且分别以纵向和横向方向以预定间距布置，每个存储单元具有一定长度至宽度尺寸的图案; 在通过杂质注入形成的第二电导型扩散区域与有源区域之间提供电容器结构的单元板布置和通过电容器电介质以预定的单元板图案覆盖部分有源区域形成的单元板电极，细胞板图案以一定的长度尺寸在横向上延伸; 以及字线图案，其中在没有形成单元板电极的有源区域的空白区域的横向上布置字线图案，并且用作有源区域上的场效应晶体管的栅电极，所述字线图案是以预定间隔通过栅极氧化物形成的，其中所述存储单元的单元阵列的布局由最接近的封装单元配置提供。

3. 发明授权

US06377483B1 Semiconductor memory device having improved memory cell and bit line pitch 失效
公开(公告)号：US06377483B1
公开(公告)日：2002-04-23
申请号：US09769416
申请日：2001-01-26
申请人： Kazutami Arimoto , Hiroki Shimano , Toshinori Morihara
发明人： Kazutami Arimoto , Hiroki Shimano , Toshinori Morihara
IPC分类号： G11C1124
CPC分类号： G11C5/063 , G11C7/18 , G11C8/14 , H01L27/10897
摘要： Tow bit lines are arranged in each column in which memory cells are disposed. For selecting a first group sub-word line, only a sense amplifier on one sense amplifier band is activated and for selecting a second group sub-word line, only a sense amplifier on the other sense amplifier band is activated. A storage node is formed under a bit line.

4. 发明授权

US06487105B2 Test circuit for semiconductor integrated circuit which detects an abnormal contact resistance 失效
标题翻译：用于检测异常接触电阻的半导体集成电路的测试电路
公开(公告)号：US06487105B2
公开(公告)日：2002-11-26
申请号：US09741998
申请日：2000-12-22
申请人： Toshinori Morihara , Hiroki Shimano
发明人： Toshinori Morihara , Hiroki Shimano
IPC分类号： G11C1124
CPC分类号： G11C29/50 , G11C5/063 , G11C11/401
摘要： There is provided a semiconductor integrated circuit having a multi level interconnect structure comprising: a first wiring connected to a transistor region formed in a semiconductor substrate; an interlayer dielectric formed on this topography; first and second contacts formed in the interlayer dielectric; and a second wiring connected electrically to the first wiring via the first and second contacts, this circuit further including switching means, connected to said first and second wirings respectively, for feeding a high potential and a low potential alternately.
摘要翻译：提供一种具有多电平互连结构的半导体集成电路，包括：连接到形成在半导体衬底中的晶体管区域的第一布线; 在该形貌上形成的层间电介质; 在层间电介质中形成的第一和第二触点; 以及经由第一和第二触点与第一布线电连接的第二布线，该电路还包括分别连接到所述第一和第二布线的开关装置，用于交替地馈送高电位和低电位。

5. 发明授权

US06756267B2 Method of manufacturing a semiconductor device including a capacitor with a roughened-surface electrode 失效
标题翻译：制造包括具有粗糙表面电极的电容器的半导体器件的方法
公开(公告)号：US06756267B2
公开(公告)日：2004-06-29
申请号：US10302857
申请日：2002-11-25
申请人： Masahiro Shimizu , Takashi Miyajima , Toshinori Morihara
发明人： Masahiro Shimizu , Takashi Miyajima , Toshinori Morihara
IPC分类号： H01L218242
CPC分类号： H01L28/91 , H01L21/3212 , H01L27/10814 , H01L27/10852 , H01L28/84 , Y10S438/964
摘要： A method of manufacturing a semiconductor device is provided. A polysilicon film and a rough-surfaced polysilicon film are formed on inter-layer insulating film including side and bottom surfaces of openings formed in inter-layer insulating film. A photoresist is formed on the rough-surfaced polysilicon film. The photoresist, the rough-surfaced polysilicon film and the polysilicon film that are located on the top surface of inter-layer insulating film are removed by the CMP method. The polysilicon film and rough-surfaced polysilicon film are etched in a predetermined atmosphere to make the position of the top end of storage nodes lower than the top surface of inter-layer insulating film.
摘要翻译：提供一种制造半导体器件的方法。在层间绝缘膜上形成多晶硅膜和粗糙表面的多晶硅膜，该层间绝缘膜包括在层间绝缘膜中形成的开口的侧面和底面。在粗糙表面的多晶硅膜上形成光致抗蚀剂。通过CMP方法去除位于层间绝缘膜的顶表面上的光致抗蚀剂，粗糙表面多晶硅膜和多晶硅膜。在预定的气氛中蚀刻多晶硅膜和粗糙表面的多晶硅膜，使存储节点的顶端的位置比层间绝缘膜的上表面低。

6. 发明授权

US06495418B2 Method of manufacturing a semiconductor device having a capacitor 失效
标题翻译：制造具有电容器的半导体器件的方法
公开(公告)号：US06495418B2
公开(公告)日：2002-12-17
申请号：US09754120
申请日：2001-01-05
申请人： Masahiro Shimizu , Takashi Miyajima , Toshinori Morihara
发明人： Masahiro Shimizu , Takashi Miyajima , Toshinori Morihara
IPC分类号： H01L218242
CPC分类号： H01L28/91 , H01L21/3212 , H01L27/10814 , H01L27/10852 , H01L28/84 , Y10S438/964
摘要： A method of manufacturing a semiconductor device is provided. A polysilicon film and a rough-surfaced polysilicon film are formed on inter-layer insulating film including side and bottom surfaces of openings formed in inter-layer insulating film. A photoresist is formed on the rough-surfaced polysilicon film. The photoresist, the rough-surfaced polysilicon film and the polysilicon film that are located on the top surface of inter-layer insulating film are removed by the CMP method. The polysilicon film and rough-surfaced polysilicon film are etched in a predetermined atmosphere to make the position of the top end of storage nodes lower than the top surface of inter-layer insulating film.
摘要翻译：提供一种制造半导体器件的方法。在层间绝缘膜上形成多晶硅膜和粗糙表面的多晶硅膜，该层间绝缘膜包括在层间绝缘膜中形成的开口的侧面和底面。在粗糙表面的多晶硅膜上形成光致抗蚀剂。通过CMP方法去除位于层间绝缘膜的顶表面上的光致抗蚀剂，粗糙表面多晶硅膜和多晶硅膜。在预定的气氛中蚀刻多晶硅膜和粗糙表面的多晶硅膜，使存储节点的顶端的位置比层间绝缘膜的上表面低。

7. 发明授权

US5888854A Method of manufacturing a DRAM having an SOI structure 失效
标题翻译：制造具有SOI结构的DRAM的方法
公开(公告)号：US5888854A
公开(公告)日：1999-03-30
申请号：US571482
申请日：1995-12-13
申请人： Toshinori Morihara
发明人： Toshinori Morihara
IPC分类号： H01L27/04 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L21/84 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/78 , H01L29/786 , H01L21/00
CPC分类号： H01L27/10852 , H01L21/76877 , H01L21/84 , H01L27/10808 , H01L27/105
摘要： A dielectric layer is formed on a main surface of a semiconductor substrate. A silicon layer is formed on dielectric layer. MOS transistors are formed in silicon layer and include impurity regions in a semiconductor layer. A capacitor is formed by cooperation of the impurity region, the dielectric layer, and the semiconductor substrate. The dielectric layer also serves as an insulating film of an SOI structure. Thus, a semiconductor memory device which achieves high performance and allows high integration can easily be obtained in a DRAM having an SOI structure.
摘要翻译：在半导体衬底的主表面上形成介电层。在电介质层上形成硅层。 MOS晶体管形成在硅层中，并且在半导体层中包括杂质区。通过杂质区，电介质层和半导体衬底的配合形成电容器。电介质层也用作SOI结构的绝缘膜。因此，在具有SOI结构的DRAM中可以容易地获得实现高性能并且允许高集成度的半导体存储器件。

8. 发明授权

US06541807B1 Semiconductor device having capacitor and method of manufacturing the same 失效
标题翻译：具有电容器的半导体装置及其制造方法
公开(公告)号：US06541807B1
公开(公告)日：2003-04-01
申请号：US09706697
申请日：2000-11-07
申请人： Toshinori Morihara
发明人： Toshinori Morihara
IPC分类号： H01L2120
CPC分类号： H01L28/84 , H01L27/10814
摘要： A storage node electrically connected to one of source/drain regions of a MOS transistor is formed along the side wall and the bottom wall of an opening provided through a silicon nitride film, a BPTEOS film and a TEOS film. The surface of this storage node is roughened. Thus, a semiconductor device having high reliability and a method of manufacturing the same are obtained.
摘要翻译：电连接到MOS晶体管的源/漏区之一的存储节点沿着通过氮化硅膜，BPTEOS膜和TEOS膜提供的开口的侧壁和底壁形成。该存储节点的表面被粗糙化。因此，获得了具有高可靠性的半导体器件及其制造方法。

9. 发明授权

US06271564B1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06271564B1
公开(公告)日：2001-08-07
申请号：US09304053
申请日：1999-05-04
申请人： Toshinori Morihara , Yoshinori Tanaka
发明人： Toshinori Morihara , Yoshinori Tanaka
IPC分类号： H01L31062
CPC分类号： H01L21/76897 , H01L21/76832 , H01L21/76834 , H01L21/823425 , H01L21/823468 , H01L21/823481 , H01L27/10852 , H01L27/10873 , H01L28/60 , H01L29/6656 , H01L29/6659
摘要： When sidewalls (10) are formed by anisotropic etching, an insulating film (9) serves as a protective film for a major surface of a semiconductor substrate (100) and therefore prevents the major surface from suffering etching damage. That relieves an electric field concentration in a pn junction, to effectively take advantage of an LDD structure. Since a portion of the insulating film (9) extending off the sidewalls (10) is removed, there is no need for etching of the insulating film (9) when the contact holes (12) are formed and only an insulating film (11) is etched. That prevents a short circuit between main electrodes (13) and a gate electrode (7) and makes it possible to determine the spacing between the contact holes (12) narrower than the width of the gate electrode (7).
摘要翻译：当通过各向异性蚀刻形成侧壁（10）时，绝缘膜（9）用作半导体衬底（100）的主表面的保护膜，因此防止主表面遭受蚀刻损伤。这减轻了pn结中的电场浓度，从而有效地利用了LDD结构。由于离开侧壁（10）的绝缘膜（9）的一部分被去除，所以当形成接触孔（12）并且只有绝缘膜（11）不需要蚀刻绝缘膜（9）被蚀刻。这防止主电极（13）和栅电极（7）之间的短路，并且可以确定接触孔（12）之间的间距比栅电极（7）的宽度窄。

10. 发明授权

US06635538B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06635538B2
公开(公告)日：2003-10-21
申请号：US09866708
申请日：2001-05-30
申请人： Toshinori Morihara , Yoshinori Tanaka
发明人： Toshinori Morihara , Yoshinori Tanaka
IPC分类号： H01L21336
CPC分类号： H01L21/76897 , H01L21/76832 , H01L21/76834 , H01L21/823425 , H01L21/823468 , H01L21/823481 , H01L27/10852 , H01L27/10873 , H01L28/60 , H01L29/6656 , H01L29/6659
摘要： When sidewalls (10) are formed by anisotropic etching, an insulating film (9) serves as a protective film for a major surface of a semiconductor substrate (100) and therefore prevents the major surface from suffering etching damage. That relieves an electric field concentration in a pn junction, to effectively take advantage of an LDD structure. Since a portion of the insulating film (9) extending off the sidewalls (10) is removed, there is no need for etching of the insulating film (9) when the contact holes (12) are formed and only an insulating film (11) is etched. That prevents a short circuit between main electrodes (13) and a gate electrode (7) and makes it possible to determine the spacing between the contact holes (12) narrower than the width of the gate electrode (7).
摘要翻译：当通过各向异性蚀刻形成侧壁（10）时，绝缘膜（9）用作半导体衬底（100）的主表面的保护膜，因此防止主表面遭受蚀刻损伤。这减轻了pn结中的电场浓度，从而有效地利用了LDD结构。由于离开侧壁（10）的绝缘膜（9）的一部分被去除，所以当形成接触孔（12）并且只有绝缘膜（11）不需要蚀刻绝缘膜（9）被蚀刻。这防止主电极（13）和栅电极（7）之间的短路，并且可以确定接触孔（12）之间的间距比栅电极（7）的宽度窄。

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