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1. 发明授权

US09065443B2 Inverter drive device 有权
标题翻译：变频器驱动装置
公开(公告)号：US09065443B2
公开(公告)日：2015-06-23
申请号：US14119091
申请日：2012-05-21
申请人： Hiroki Shimano , Koichi Yahata , Yoshio Akaishi , Yasuo Noto
发明人： Hiroki Shimano , Koichi Yahata , Yoshio Akaishi , Yasuo Noto
IPC分类号： H02M1/32 , H03K17/08 , H02M1/08 , H02M7/5387
CPC分类号： H03K17/08 , H02M1/08 , H02M1/32 , H02M7/5387
摘要： An inverter drive device includes a drive circuit that outputs a gate voltage signal of a power semiconductor element; and a Zener clamping protection circuit that acquires an emitter electrode side voltage of the power semiconductor element, and, if that voltage is greater than a predetermined voltage value, performs clamping of the gate voltage of the drive circuit after a predetermined time interval has elapsed from the acquisition of the emitter electrode side voltage. The Zener clamping protection circuit includes a latch circuit that, after the emitter electrode side voltage has been acquired, continues the clamping of the gate voltage by the Zener clamping protection circuit during an interval.
摘要翻译：逆变器驱动装置包括：输出功率半导体元件的栅极电压信号的驱动电路; 以及获取功率半导体元件的发射极侧电压的齐纳钳位保护电路，如果该电压大于预定电压值，则在经过预定时间间隔之后，驱动电路的栅极电压被钳位采集发射极电极侧电压。齐纳钳位保护电路包括一个锁存电路，其在获得发射极电极侧电压之后，在间隔期间通过齐纳钳位保护电路继续钳位栅极电压。

2. 发明授权

US07626883B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07626883B2
公开(公告)日：2009-12-01
申请号：US12149549
申请日：2008-05-05
申请人： Hiroki Shimano , Kazutami Arimoto
发明人： Hiroki Shimano , Kazutami Arimoto
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C5/063 , G11C5/148 , G11C11/406 , G11C11/4074 , G11C2211/4067
摘要： During a stand-by state in which power supply is cut off, a high-voltage power supply control circuit isolates a global negative voltage line transmitting a negative voltage and a local negative voltage line provided corresponding to each respective sub array block from each other and isolates a global ground line and a local ground line transmitting a ground voltage from each other. These local ground line and local negative voltage line are charged to a high voltage level through a high voltage line before cut-off from the corresponding power supply. A leakage current path from a word line to the negative voltage line or the ground line is cut off, so that the word line in a non-selected state can reliably be maintained at a non-selection voltage. Thus, in a low power consumption stand-by mode, data stored in a memory cell can be held in a stable manner.
摘要翻译：在电源被切断的待机状态下，高电压电源控制电路将发送负电压的全局负电压线与对应于每个各个子阵列块的局部负电压线相互隔离，隔离全球接地线和传输地电压的局部接地线。这些本地接地线和局部负电压线在从相应电源切断之前通过高压线充电到高电压电平。从字线到负电压线或接地线的漏电流路径被切断，使得未选择状态的字线可以可靠地保持在非选择电压。因此，在低功耗待机模式中，可以以稳定的方式保存存储在存储单元中的数据。

3. 发明申请

US20050009269A1 Semiconductor device and method of manufacturing semiconductor device 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050009269A1
公开(公告)日：2005-01-13
申请号：US10850051
申请日：2004-05-21
申请人： Hiroki Shinkawata , Atsushi Hachisuka , Hiroki Shimano
发明人： Hiroki Shinkawata , Atsushi Hachisuka , Hiroki Shimano
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/06
CPC分类号： H01L28/84 , H01L27/0629 , H01L27/10861 , H01L27/10894
摘要： An isolation film is formed in a surface of a substrate 1 in which active regions are formed, to separate the active regions from each other. Subsequently, a portion of the isolation film is removed, to form a recess, which is then filled with a portion of an upper electrode. Also, an insulating film 8 is interposed between the upper electrode and the substrate.
摘要翻译：在基板1的形成有活性区域的表面中形成隔离膜，以将活性区域彼此分离。随后，去除隔离膜的一部分，形成凹部，然后用一部分上部电极填充。此外，在上电极和基板之间插入绝缘膜8。

4. 发明授权

US06807077B2 Content addressable memory capable of stably storing ternary data 有权
公开(公告)号：US06807077B2
公开(公告)日：2004-10-19
申请号：US10442986
申请日：2003-05-22
申请人： Hideyuki Noda , Hiroki Shimano
发明人： Hideyuki Noda , Hiroki Shimano
IPC分类号： G11C1500
CPC分类号： G11C15/043
摘要： A data storage unit of a ternary content addressable memory (TCAM) cell is constructed by two twin cells each having DRAM cells of two bits, and complementary data are stored in each of the twin cells. One of storage nodes is selected from each of the twin cells. A comparing circuit compares complementary search data on a search data line pair with the selected stored data. In a DRAM cell, a planar metal-insulator-semiconductor (MIS) transistor is used. According to such configuration, the chip area and cost of a ternary content addressable memory are reduced and high-speed writing is achieved.

5. 发明授权

US06785157B2 Semiconductor memory device having a memory cell structure of reduced occupying area 失效
标题翻译：具有占用面积减小的存储单元结构的半导体存储器件
公开(公告)号：US06785157B2
公开(公告)日：2004-08-31
申请号：US10119094
申请日：2002-04-10
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C1124
CPC分类号： G11C7/18 , G11C8/14 , G11C11/4085 , G11C11/4087 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/108 , H01L27/1085 , H01L27/10873 , H01L27/10882
摘要： Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus, a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.
摘要翻译：构成存储单元板的导体线的导电线和构成存储单元板电极的导线被形成在包括多个存储单元的存储器件的同一互连层中，每个存储单元均包括用于以电荷形式存储数据的电容器。通过将存储单元的电容器形成为平面电容器配置，由于电容器而导致的步骤被去除。因此，可以通过CMOS工艺形成动态半导体存储器件，并且实现适合于与逻辑合并的动态半导体存储器件。 1位的数据由两个存储单元存储，即使由于平面型电容器而使存储单元的电容值减小，也可以可靠地存储数据。

6. 发明授权

US06636454B2 Low-power consumption semiconductor memory device 失效
公开(公告)号：US06636454B2
公开(公告)日：2003-10-21
申请号：US09756272
申请日：2001-01-09
申请人： Takeshi Fujino , Kazutami Arimoto , Hiroki Shimano
发明人： Takeshi Fujino , Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C700
CPC分类号： G11C11/4094 , G11C7/12
摘要： A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit lines are precharged to a voltage (Vccs or GND) corresponding to the data stored in the memory cell unit. Refresh-free, low-current-consumption semiconductor memory device operating stably even under a low power supply voltage can be implemented.

7. 发明授权

US06573613B2 Semiconductor memory device having cell plate electrodes allowing independent power supply for each redundant replacement unit 有权
公开(公告)号：US06573613B2
公开(公告)日：2003-06-03
申请号：US10118433
申请日：2002-04-09
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： H01L27108
CPC分类号： G11C29/83 , G11C29/832 , H01L27/10897
摘要： A word line and a cell plate electrode line are formed at a common interconnection layer. A redundant replacement unit for a faulty row is set corresponding to the cell plate electrode line. For each redundant replacement unit, a program element is arranged for stopping supply of a cell plate voltage from the cell plate voltage line to the cell plate electrode line. The program element corresponding to the cell plate electrode line short-circuited to the word line nonvolatilely changes from the on state to the off state in response to an externally supplied input instruction.

8. 发明授权

US06545926B2 Antifuse address detecting circuit programmable by applying a high voltage and semiconductor integrated circuit device provided with the same 失效
标题翻译：防漏地址检测电路通过应用高电压和半导体集成电路器件可编程
公开(公告)号：US06545926B2
公开(公告)日：2003-04-08
申请号：US09197566
申请日：1998-11-23
申请人： Tsukasa Ooishi , Hiroki Shimano , Hideto Hidaka , Shigeki Tomishima
发明人： Tsukasa Ooishi , Hiroki Shimano , Hideto Hidaka , Shigeki Tomishima
IPC分类号： G11C700
CPC分类号： G11C29/70
摘要： An input protective circuit in a semiconductor integrated circuit device includes a bipolar transistor arranged for an interconnection layer. An N-type active region in the bipolar transistor is connected to an electrode of a program element. The electrode is connected to the interconnection layer. The interconnection layer supplies a high voltage for breaking a dielectric of a program element. A voltage on a P-type well is externally adjusted via a resistance element. Thereby, erroneous program due to serge entering at the interconnection layer can be avoided.
摘要翻译：半导体集成电路器件中的输入保护电路包括布置成互连层的双极晶体管。双极晶体管中的N型有源区连接到程序元件的电极。电极连接到互连层。互连层提供用于断开程序元件的电介质的高电压。通过电阻元件外部调整P型阱上的电压。因此，可以避免由于在互连层处进入的错误程序。

9. 发明授权

US06456560B2 Semiconductor integrated circuit device with test interface circuit for performing test on embedded memory from outside 失效
标题翻译：具有用于从外部对嵌入式存储器进行测试的测试接口电路的半导体集成电路器件
公开(公告)号：US06456560B2
公开(公告)日：2002-09-24
申请号：US09782286
申请日：2001-02-14
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C800
CPC分类号： G11C29/50012 , G11C11/401 , G11C29/14 , G11C29/48 , G11C29/50
摘要： A first test clock signal and a second test clock signal are generated from a common basic test clock signal using a delay line with a changeable delay time and a delay stage with a fixed delay time. A memory circuit is operated in synchronization with one of the first and second test clock signals, and the memory circuit is provided with a signal/data according to the other test clock signal. Thus, the set-up time and the hold time of a signal for the memory can be measured with accuracy in a memory-merged system LSI.
摘要翻译：使用具有可变延迟时间的延迟线和具有固定延迟时间的延迟级，从公共基本测试时钟信号产生第一测试时钟信号和第二测试时钟信号。存储器电路与第一和第二测试时钟信号中的一个同步地操作，并且根据另一个测试时钟信号向存储器电路提供信号/数据。因此，可以在存储器合并系统LSI中精确地测量存储器的信号的建立时间和保持时间。

10. 发明授权

US06388929B1 Semiconductor memory device performing redundancy repair based on operation test and semiconductor integrated circuit device having the same 失效
标题翻译：基于操作测试执行冗余修复的半导体存储器件和具有该半导体集成电路器件
公开(公告)号：US06388929B1
公开(公告)日：2002-05-14
申请号：US09906654
申请日：2001-07-18
申请人： Hiroki Shimano , Kazutami Arimoto
发明人： Hiroki Shimano , Kazutami Arimoto
IPC分类号： G11C2900
CPC分类号： G11C29/70 , G11C29/44
摘要： A BIST circuit conducts an operation test on a memory cell array to detect a defective memory cell when power is turned on. On the basis of a result of the operation test, the BIST circuit generates a redundancy code indicative of a defect address corresponding to a defective memory cell. The redundancy code is transmitted to a repair determining circuit in a decoding circuit. The repair determining circuit stores the redundancy code in a volatile manner during the power is on. When an input address coincides with the redundancy code to be stored on the inside, the repair determining circuit executes an access to a corresponding spare memory cell area.
摘要翻译： BIST电路在存储单元阵列上进行操作测试，以在电源接通时检测缺陷存储单元。基于操作测试的结果，BIST电路产生指示与缺陷存储单元对应的缺陷地址的冗余码。冗余码被传送到解码电路中的修复确定电路。修复确定电路在电源接通期间以易失性的方式存储冗余码。当输入地址与要存储在内部的冗余码一致时，修复确定电路执行对相应的备用存储单元区的访问。

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