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61. 发明授权

US6150695A Multilevel transistor formation employing a local substrate formed within a shallow trench 失效
标题翻译：使用在浅沟槽内形成的局部衬底的多晶体管形成
公开(公告)号：US6150695A
公开(公告)日：2000-11-21
申请号：US741812
申请日：1996-10-30
申请人： Mark Gardner , Daniel Kadosh , Derick J. Wristers
发明人： Mark Gardner , Daniel Kadosh , Derick J. Wristers
IPC分类号： H01L21/822 , H01L27/06 , H01L27/01
CPC分类号： H01L27/0688 , H01L21/8221
摘要： A dual level transistor and a fabrication technique. The dual level transistor is an integrated circuit in which a first transistor is formed on an upper surface of a global dielectric and a second transistor is formed on an upper surface of a first local substrate such that the second transistor is vertically displaced from the first transistor. The first local substrate is formed within a local trench etched into a first inter-substrate dielectric. By vertically displacing the first and second transistors, the lateral separation required to isolate first and second transistors in a typical single plane process is eliminated. The integrated circuit includes a semiconductor global substrate and a first transistor formed on the global substrate. The first transistor includes a first gate dielectric formed on an upper surface of the global substrate and a first conductive gate structure formed on an upper surface of the first dielectric. The integrated circuit further includes a first inter-substrate dielectric that is formed on the first conductive gate structure and the global substrate. The first inter-substrate dielectric includes a local trench. A first local substrate is formed within the local trench. A second transistor is located within the first local substrate. The second transistor includes a second gate dielectric formed on an upper surface of the first local substrate and a second conductive gate structure formed on an upper surface of the second gate dielectric.
摘要翻译：双级晶体管和制造技术。双电平晶体管是集成电路，其中第一晶体管形成在全局电介质的上表面上，并且第二晶体管形成在第一局部衬底的上表面上，使得第二晶体管垂直从第一晶体管。第一局部衬底形成在蚀刻到第一衬底间电介质中的局部沟槽内。通过垂直移位第一和第二晶体管，消除了在典型的单平面工艺中隔离第一和第二晶体管所需的横向分离。集成电路包括半导体全局基板和形成在全局基板上的第一晶体管。第一晶体管包括形成在全局衬底的上表面上的第一栅极电介质和形成在第一电介质的上表面上的第一导电栅极结构。集成电路还包括形成在第一导电栅极结构和全局基板上的第一基板间电介质。第一基板间电介质包括局部沟槽。第一局部衬底形成在局部沟槽内。第二晶体管位于第一局部衬底内。第二晶体管包括形成在第一局部衬底的上表面上的第二栅极电介质和形成在第二栅极电介质的上表面上的第二导电栅极结构。

62. 发明授权

US6107130A CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions 有权
标题翻译： CMOS集成电路具有用于产生与PMOS源极/漏极结不相似的分级NMOS源极/漏极结的牺牲金属间隔物
公开(公告)号：US6107130A
公开(公告)日：2000-08-22
申请号：US189235
申请日：1998-11-10
申请人： H. Jim Fulford, Jr. , Mark I. Gardner , Derick J. Wristers
发明人： H. Jim Fulford, Jr. , Mark I. Gardner , Derick J. Wristers
IPC分类号： H01L21/8238 , H01L29/78
CPC分类号： H01L29/7833 , H01L21/823814 , Y10S257/90
摘要： An integrated circuit is formed whereby junction of NMOS transistors are formed dissimilar to junctions of PMOS transistors. The NMOS transistors include an LDD area, an MDD area and a heavy concentration source/drain area. Conversely, the PMOS transistor include an LDD area and a source/drain area. The NMOS transistor junction is formed dissimilar from the PMOS transistor junction to take into account the less mobile nature of the junction dopants relative to the PMOS dopants. Thus, a lessening of the LDD area and the inclusion of an MDD area provide lower source/drain resistance and higher ohmic connectivity in the NMOS device. The PMOS junction includes a relatively large LDD area so as to draw the highly mobile, heavy concentration boron atoms away from the PMOS channel.
摘要翻译：形成集成电路，其中NMOS晶体管的结形成为不同于PMOS晶体管的结。 NMOS晶体管包括LDD区域，MDD区域和重的浓度源极/漏极区域。相反，PMOS晶体管包括LDD区域和源极/漏极区域。 NMOS晶体管结形成为不同于PMOS晶体管结，以考虑到相掺杂剂相对于PMOS掺杂剂的移动性较小。因此，LDD面积的减小和包含MDD面积在NMOS器件中提供更低的源极/漏极电阻和更高的欧姆连接性。 PMOS结包括相对较大的LDD面积，以便将高度移动的，高浓度的硼原子从PMOS沟道拉出。

63. 发明授权

US6103559A Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication 有权
标题翻译：为源/漏和LDD注入和随后的栅极制造做一次性通道掩蔽的方法
公开(公告)号：US6103559A
公开(公告)日：2000-08-15
申请号：US282033
申请日：1999-03-30
申请人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/336 , H01L21/822 , H01L21/8238 , H01L27/06 , H01L29/51 , H01L21/338 , H01L21/3205
CPC分类号： H01L21/28194 , H01L21/28052 , H01L21/28123 , H01L21/8221 , H01L21/823814 , H01L21/823828 , H01L27/0688 , H01L29/517 , H01L29/6659 , H01L21/28202 , H01L29/518 , H01L29/66545
摘要： A method is provided for fabricating a semiconductor device, the method including forming a first dielectric layer above a structure and forming an island of a sacrificial layer above the first dielectric layer. The method also includes introducing a first dopant into first portions of the structure, leaving a second portion of the structure protected by the island, and removing first portions of the island leaving a second portion of the island. The method further includes introducing a second dopant into the first portions and third portions of the structure, leaving a fourth portion of the structure protected by the second portion of the island. The method additionally includes forming a second dielectric layer adjacent the second portion of the island, removing the second portion of the island, forming a gate dielectric above the fourth portion of the structure and forming a gate conductor above the gate dielectric.
摘要翻译：提供了一种用于制造半导体器件的方法，所述方法包括在结构之上形成第一介电层，并在第一介电层上形成牺牲层的岛。该方法还包括将第一掺杂剂引入到结构的第一部分中，留下由岛保护的结构的第二部分，以及去除离开岛的第二部分的岛的第一部分。该方法还包括将第二掺杂剂引入到结构的第一部分和第三部分中，留下结构的第四部分被岛的第二部分保护。该方法还包括形成与岛的第二部分相邻的第二电介质层，去除岛的第二部分，在结构的第四部分之上形成栅极电介质，并在栅极电介质上方形成栅极导体。

64. 发明授权

US6060345A Method of making NMOS and PMOS devices with reduced masking steps 失效
标题翻译：制造具有减少掩蔽步骤的NMOS和PMOS器件的方法
公开(公告)号：US6060345A
公开(公告)日：2000-05-09
申请号：US844924
申请日：1997-04-21
申请人： Frederick N. Hause , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Frederick N. Hause , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823814
摘要： A method of making NMOS and PMOS devices with reduced masking steps is disclosed. The method includes providing a semiconductor substrate with a first active region of first conductivity type and a second active region of second conductivity type, forming a gate material over the first and second active regions, forming a first masking layer over the gate material, etching the gate material using the first masking layer as an etch mask to form a first gate over the first active region and a second gate over the second active region, implanting a dopant of second conductivity type into the first and second active regions using the first masking layer as an implant mask, forming a second masking layer that covers the first active region and includes an opening above the second active region, and implanting a dopant of first conductivity type into the second active region using the first and second masking layers as an implant mask. Advantageously, the dopant of first conductivity type counterdopes the dopant of second conductivity type in the second active region, thereby providing source and drain regions of second conductivity type in the first active region and source and drain regions of first conductivity type in the second active region with a single masking step and without subjecting either gate to dopants of first and second conductivity type.
摘要翻译：公开了一种制造具有减小的掩蔽步骤的NMOS和PMOS器件的方法。该方法包括提供具有第一导电类型的第一有源区和第二导电类型的第二有源区的半导体衬底，在第一和第二有源区上形成栅极材料，在栅极材料上形成第一掩模层，栅极材料，使用第一掩模层作为蚀刻掩模，以在第一有源区上形成第一栅极，在第二有源区上形成第二栅极，使用第一掩模层将第二导电类型的掺杂剂注入到第一和第二有源区中作为注入掩模，形成覆盖第一有源区并且包括在第二有源区上方的开口的第二掩模层，以及使用第一和第二掩模层作为注入掩模将第一导电类型的掺杂剂注入到第二有源区中。有利地，第一导电类型的掺杂剂在第二有源区域中抵消第二导电类型的掺杂剂，从而在第一有源区域中提供第二导电类型的源极和漏极区域，并且在第二有源区域中提供第一导电类型的源极和漏极区域具有单个掩蔽步骤，并且不对任一个栅极施加第一和第二导电类型的掺杂剂。

65. 发明授权

US6051459A Method of making N-channel and P-channel IGFETs using selective doping and activation for the N-channel gate 失效
标题翻译：使用N沟道栅极的选择性掺杂和激活来制造N沟道和P沟道IGFET的方法
公开(公告)号：US6051459A
公开(公告)日：2000-04-18
申请号：US803730
申请日：1997-02-21
申请人： Mark I. Gardner , Daniel Kadosh , Frederick N. Hause , Derick J. Wristers
发明人： Mark I. Gardner , Daniel Kadosh , Frederick N. Hause , Derick J. Wristers
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A method of making N-channel and P-channel IGFETs is disclosed. The method includes providing a semiconductor substrate with N-type and P-type active regions, forming a gate material over the N-type and P-type active regions, forming a first masking layer over the gate material, wherein the first masking layer includes an opening above a first portion of the gate material over the P-type active region, and the first masking layer covers a second portion of the gate material over the N-type active region, introducing an N-type dopant into the first portion of the gate material without introducing the N-type dopant into the second portion of the gate material, applying a thermal cycle to drive-in and activate the N-type dopant in the first portion of the gate material before introducing any doping into the second portion of the gate material, before introducing any source/drain doping into the N-type active region, and before introducing any source/drain doping into the P-type active region, forming a second masking layer over the gate material, wherein the second masking layer covers portions of the first and second portions of the gate material, applying an etch to form first and second gates from unetched portions of the first and second portions of the gate material, respectively, and forming an N-type source and drain in the P-type active region and forming a P-type source and drain in the N-type active region. Advantageously, a dopant in the gate for the N-channel IGFET can be driven-in and activated at a relatively high temperature without subjecting any source/drain doping to this temperature.
摘要翻译：公开了制造N沟道和P沟道IGFET的方法。该方法包括提供具有N型和P型有源区的半导体衬底，在N型和P型有源区上形成栅极材料，在栅极材料上形成第一掩模层，其中第一掩模层包括在P型有源区上方的栅极材料的第一部分上方的开口，并且第一掩模层覆盖N型有源区上的栅极材料的第二部分，将N型掺杂剂引入到第一部分栅极材料，而不将N型掺杂剂引入栅极材料的第二部分中，在引入任何掺杂到第二部分之前施加热循环以驱动和激活栅极材料的第一部分中的N型掺杂剂在向N型有源区域引入任何源极/漏极掺杂之前，在向P型有源区域引入任何源极/漏极掺杂之前，在栅极材料上形成第二掩模层，在第二掩模层中，分别覆盖栅极材料的第一和第二部分的部分，施加蚀刻以分别从栅极材料的第一和第二部分的未蚀刻部分形成第一和第二栅极，并形成N型源极并在P型有源区中漏极，并在N型有源区中形成P型源极和漏极。有利的是，用于N沟道IGFET的栅极中的掺杂剂可以被驱入并在相对较高的温度下被激活，而不会对该温度进行任何源极/漏极掺杂。

66. 发明授权

US6018179A Transistors having a scaled channel length and integrated spacers with enhanced silicidation properties 有权
标题翻译：具有缩放沟道长度的晶体管和具有增强的硅化特性的集成间隔物
公开(公告)号：US6018179A
公开(公告)日：2000-01-25
申请号：US187028
申请日：1998-11-05
申请人： Mark I. Gardner , Fred N. Hause , Derick J. Wristers
发明人： Mark I. Gardner , Fred N. Hause , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/311 , H01L21/321 , H01L21/336 , H01L29/423 , H01L29/51 , H01L27/088
CPC分类号： H01L21/28194 , H01L21/28114 , H01L21/28123 , H01L21/28202 , H01L21/31116 , H01L29/42376 , H01L29/513 , H01L29/518 , H01L29/66583 , H01L29/6659 , H01L21/3212 , Y10S257/90
摘要： A high speed MOS device has a scaled channel length and integrated spacers. The MOS device is formed on a substrate having active and isolation regions. In constructing the MOS device wells and Vt regions are formed as required. Then, a thin nitride layer is formed upon the substrate. Subsequently, an oxide layer is formed upon the nitride layer. Then, the oxide layer is pattern masked to expose gate regions. The gate regions are sloped etched to form slope etched voids. The slope etching may proceed to the nitride layer, through a portion of the nitride layer or fully through the nitride layer, depending upon the embodiment. In another embodiment, the nitride layer is not deposed and the oxide layer is either fully or partially slope etched to the silicon substrate. The patterned mask is then removed and remaining portions of the nitride layer may be converted to an oxynitride. Additionally, a gate oxide may be formed. The slope etched void is then filled with a gate conductor and the surface is planarized in a CMP process. The gate conductor then has a shape wherein its lower surface is smaller than its upper surface. Then, the substrate is isotropically etched to remove portions of the oxide layer and nitride layer unprotected by the gate conductor. The remaining structure includes integrally formed spacers. Active regions, LDD regions and punchthrough regions are then formed to complete formation of the transistor.
摘要翻译：高速MOS器件具有缩放的沟道长度和集成间隔物。 MOS器件形成在具有有源和隔离区域的衬底上。在构建MOS器件时，根据需要形成Vt区域。然后，在基板上形成薄的氮化物层。随后，在氮化物层上形成氧化物层。然后，将氧化层图案掩模以露出栅极区域。栅极区被倾斜蚀刻以形成斜坡蚀刻的空隙。根据实施例，倾斜蚀刻可以通过氮化物层的一部分或完全通过氮化物层而进行到氮化物层。在另一个实施例中，氮化物层不被沉积，并且氧化物层被完全或部分地倾斜蚀刻到硅衬底。然后去除图案化掩模，并且可以将氮化物层的剩余部分转化为氮氧化合物。另外，可以形成栅极氧化物。然后用栅极导体填充斜面蚀刻的空隙，并且在CMP工艺中平坦化表面。然后，栅极导体具有其下表面小于其上表面的形状。然后，各向同性蚀刻衬底，以除去未被栅极导体保护的氧化物层和氮化物层的部分。其余结构包括一体形成的间隔物。然后形成有源区，LDD区和穿透区，以完成晶体管的形成。

67. 发明授权

US5994193A Method of making high performance MOSFET with integrated poly/metal gate electrode 失效
标题翻译：制造具有集成多晶/金属栅电极的高性能MOSFET的方法
公开(公告)号：US5994193A
公开(公告)日：1999-11-30
申请号：US95088
申请日：1998-06-10
申请人： Mark I. Gardner , Derick J. Wristers , Jon D. Cheek
发明人： Mark I. Gardner , Derick J. Wristers , Jon D. Cheek
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L29/66575 , H01L21/28061 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： An integrated circuit transistor and method of making the same are provided. The transistor includes a substrate, first and second source/drain regions, and a gate electrode stack coupled to the substrate. The gate electrode stack is fabricated by forming a first insulating layer on the substrate, forming a first conductor layer on the first insulating layer, and forming a metal layer on the first conductor layer. A second insulating layer, such as an interlevel dielectric layer, is coupled to the substrate adjacent to the gate electrode stack. Sidewall spacers and LDD processing may be incorporated. The transistor and method integrate metal and polysilicon into a self-aligned gate electrode stack.
摘要翻译：提供集成电路晶体管及其制造方法。晶体管包括衬底，第一和第二源极/漏极区域以及耦合到衬底的栅电极堆叠。通过在基板上形成第一绝缘层，在第一绝缘层上形成第一导体层，在第一导体层上形成金属层，制作栅电极堆叠。诸如层间电介质层的第二绝缘层耦合到与栅电极堆叠相邻的衬底。可以并入侧壁间隔物和LDD处理。晶体管和方法将金属和多晶硅集成到自对准栅极电极堆叠中。

68. 发明授权

US5962894A Trench transistor with metal spacers 失效
标题翻译：沟槽晶体管与金属间隔
公开(公告)号：US5962894A
公开(公告)日：1999-10-05
申请号：US30052
申请日：1998-02-24
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/336 , H01L29/417 , H01L29/423 , H01L29/76 , H01L31/062
CPC分类号： H01L29/41775 , H01L29/66621 , H01L29/78
摘要： An IGFET with a gate electrode and metal spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, metal spacers adjacent to the sidewalls and the bottom surface, a gate insulator on the bottom surface between the metal spacers, protective insulators on the metal spacers, a gate electrode on the gate insulator and protective insulators, and a source and drain adjacent to the bottom surface. A method of forming the IGFET includes implanting a doped layer into the substrate, etching completely through the doped layer and partially through the substrate to form the trench and split the doped layer into source and drain regions, applying a high-temperature anneal to diffuse the source and drain regions beneath the bottom surface, depositing a blanket layer of conductive metal over the substrate and applying an anisotropic etch to form the metal spacers, depositing a continuous insulative layer over the substrate to provide the gate insulator and the protective insulators, depositing a blanket layer of gate electrode material over the substrate, and polishing the gate electrode material so that the gate electrode is substantially aligned with a top surface of the substrate. Advantageously, the channel length is significantly smaller than the trench length, and the metal spacers reduce the parasitic resistance of lightly doped source and drain regions.
摘要翻译：公开了具有沟槽中的栅电极和金属间隔物的IGFET。 IGFET包括具有相对的侧壁和半导体衬底中的底表面的沟槽，与侧壁和底表面相邻的金属间隔物，位于金属间隔物之间的底表面上的栅极绝缘体，金属间隔物上的保护绝缘体，栅电极在栅极绝缘体和保护绝缘体上，以及与底表面相邻的源极和漏极。形成IGFET的方法包括将掺杂层注入到衬底中，完全通过掺杂层蚀刻并部分地穿过衬底以形成沟槽并将掺杂层分裂成源极和漏极区域，施加高温退火以扩散在底表面下方的源极和漏极区域，在衬底上沉积导电金属的覆盖层，并施加各向异性蚀刻以形成金属间隔物，在衬底上沉积连续的绝缘层以提供栅极绝缘体和保护绝缘体，覆盖衬底上的栅电极材料层，并且对栅电极材料进行抛光，使得栅电极基本上与衬底的顶表面对准。有利地，沟道长度显着小于沟槽长度，并且金属间隔物减少了轻掺杂源极和漏极区域的寄生电阻。

69. 发明授权

US5930634A Method of making an IGFET with a multilevel gate 失效
标题翻译：制造具有多级门的IGFET的方法
公开(公告)号：US5930634A
公开(公告)日：1999-07-27
申请号：US844927
申请日：1997-04-21
申请人： Frederick N. Hause , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Frederick N. Hause , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66575 , H01L21/28035 , H01L21/28052 , H01L29/42376 , H01L29/4925 , H01L29/6659 , H01L29/7833
摘要： A method of making an IGFET with a multilevel gate that includes upper and lower gate levels is disclosed. The method includes providing a semiconductor substrate with an active region, forming a gate insulator on the active region, forming a first gate material with a thickness of at most 1000 angstroms on the gate inslator and over the active region, forming a first photoresist layer over the first gate material, irradiating the first photoresist layer with a first image pattern and removing irradiated portions of the first photoresist layer to provide openings above the active region, etching the first gate material through the openings in the first photoresist layer using the first photoresist layer as an etch mask for a portion of the first gate material that forms a lower gate level, removing the first photoresist layer, forming an upper gate level on the lower gate level after removing the first photoresist layer, and forming a source and drain in the active region. Advantageously, the first photoresist layer can be ultra-thin to enhance the accuracy in which the image pattern is replicated, thereby reducing variations in channel length and device performance.
摘要翻译：公开了一种制造具有包括上下栅极电平的多电平栅极的IGFET的方法。该方法包括提供具有有源区的半导体衬底，在有源区上形成栅极绝缘体，在栅极绝缘体上并在有源区上形成厚度至多为1000埃的第一栅极材料，形成第一光致抗蚀剂层第一栅极材料，用第一图案图案照射第一光致抗蚀剂层，并去除第一光致抗蚀剂层的照射部分以在有源区上方提供开口，使用第一光致抗蚀剂层蚀刻通过第一光致抗蚀剂层中的开口的第一栅极材料作为用于形成下栅极电平的第一栅极材料的一部分的蚀刻掩模，去除第一光致抗蚀剂层，在去除第一光致抗蚀剂层之后在下栅极电平上形成上栅极电平，并在其中形成源极和漏极活跃区域。有利地，第一光致抗蚀剂层可以是超薄的，以提高复制图像图案的精度，从而减少通道长度和器件性能的变化。

70. 发明授权

US5904534A Transistor formation with local interconnect overetch immunity 有权
标题翻译：晶体管形成与局部互连overetch免疫
公开(公告)号：US5904534A
公开(公告)日：1999-05-18
申请号：US134702
申请日：1998-08-14
申请人： Jon D. Cheek , Derick J. Wristers , H. Jim Fulford
发明人： Jon D. Cheek , Derick J. Wristers , H. Jim Fulford
IPC分类号： H01L21/762 , H01L21/768 , H01L21/336 , H01L21/76
CPC分类号： H01L21/76895 , H01L21/76224
摘要： An integrated circuit transistor and a method for making the same are provided. The transistor is resistant to junction shorts due to the overetch of local interconnect trenches. The transistor includes a source/drain region with a first junction and a second junction that is located deeper than the first junction in the portion of the active area susceptible to the overetch junction short phenomena. The second junction is established by ion implantation through a mask that is patterned to create an opening corresponding to the intersection of the layouts of the active area and the local interconnect trench. Using this method, the second junction is only established where needed to prevent shorting and does not impede transistor performance.
摘要翻译：提供一种集成电路晶体管及其制造方法。晶体管由于局部互连沟槽的过蚀刻而抵抗结短路。该晶体管包括具有第一结的源极/漏极区域和位于有源区域的易于经过过渡接合短路现象的部分中比第一结点更深的第二结点。第二结通过通过掩模的离子注入建立，其被图案化以产生对应于有源区和局部互连沟槽的布局的相交的开口。使用该方法，仅在需要防止短路并且不妨碍晶体管性能的情况下才建立第二结。

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