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61. 发明申请

US20050250315A1 Methods of forming electrical connections for semiconductor constructions 有权
标题翻译：形成半导体结构电连接的方法
公开(公告)号：US20050250315A1
公开(公告)日：2005-11-10
申请号：US10841708
申请日：2004-05-06
申请人： Luan Tran , Fred Fishburn
发明人： Luan Tran , Fred Fishburn
IPC分类号： H01L21/768 , H01L21/336
CPC分类号： H01L21/7681 , H01L21/76895 , H01L21/823475
摘要： The invention includes methods for forming electrical connections associated with semiconductor constructions. A semiconductor substrate is provided which has a conductive line thereover, and which has at least two diffusion regions adjacent the conductive line. A patterned etch stop is formed over the diffusion regions. The patterned etch stop has a pair of openings extending through it, with the openings being along a row substantially parallel to an axis of the line. An insulative material is formed over the etch stop. The insulative material is exposed to an etch to form a trench within the insulative material, and to extend the openings from the etch stop to the diffusion regions. At least a portion of the trench is directly over the openings and extends along the axis of the line. An electrically conductive material is formed within the openings and within the trench.
摘要翻译：本发明包括用于形成与半导体结构相关联的电连接的方法。提供一种半导体衬底，其具有其上的导电线，并且具有与导电线相邻的至少两个扩散区域。在扩散区域上形成图案化的蚀刻停止层。图案化蚀刻停止件具有延伸穿过其的一对开口，其中开口沿着大致平行于该线的轴线。在蚀刻停止点上形成绝缘材料。绝缘材料暴露于蚀刻以在绝缘材料内形成沟槽，并且将开口从蚀刻停止件延伸到扩散区域。沟槽的至少一部分直接在开口上方并且沿着线的轴线延伸。在开口内和沟槽内形成导电材料。

62. 发明申请

US20050239244A1 Methods of forming storage nodes for a DRAM array 有权
标题翻译：形成DRAM阵列的存储节点的方法
公开(公告)号：US20050239244A1
公开(公告)日：2005-10-27
申请号：US11111360
申请日：2005-04-21
申请人： Luan Tran , Fred Fishburn
发明人： Luan Tran , Fred Fishburn
IPC分类号： H01L21/8234 , H01L21/8239 , H01L21/8242 , H01L21/8247 , H01L27/108 , H01L27/115 , H01L27/24 , H01L29/76
CPC分类号： H01L27/10888 , H01L27/1052 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10894 , H01L27/10897 , H01L27/115 , H01L27/11521 , H01L27/11531 , H01L27/24 , Y10S257/906 , Y10S257/908
摘要： The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array fabrication, with the etch stop covering storage node contact locations while leaving openings to bitline contact locations. An insulative material can be formed over the etch stop and over the bitline contact locations, and trenches can be formed through the insulative material. Conductive material can be provided within the trenches to form bitline interconnect lines which are in electrical contact with the bitline contact locations, and which are electrically isolated from the storage node contact locations by the etch stop. In subsequent processing, openings can be formed through the etch stop to the storage node contact locations. Memory storage devices can then be formed within the openings and in electrical contact with the storage node contact locations.
摘要翻译：本发明包括可用于形成存储器阵列的存储器阵列和方法。在存储器阵列制造期间可以使用图案化蚀刻停止件，其中蚀刻停止覆盖存储节点接触位置，同时将开口留在位线接触位置。可以在蚀刻停止点上方和位线接触位置上形成绝缘材料，并且可以通过绝缘材料形成沟槽。可以在沟槽内提供导电材料以形成与位线接触位置电接触的位线互连线，并且通过蚀刻停止件与存储节点接触位置电隔离。在随后的处理中，可以通过蚀刻停止件向存储节点接触位置形成开口。然后可以在开口内形成存储器存储装置，并与存储节点接触位置电接触。

63. 发明申请

US20050009279A1 Methods of fabricating multiple sets of field effect transistors 失效
标题翻译：制造多组场效应晶体管的方法
公开(公告)号：US20050009279A1
公开(公告)日：2005-01-13
申请号：US10914822
申请日：2004-08-09
申请人： Fred Fishburn , Martin Roberts
发明人： Fred Fishburn , Martin Roberts
IPC分类号： H01L21/8234 , H01L21/8238
CPC分类号： H01L21/31053 , H01L21/32139 , H01L21/82345 , H01L21/823828 , H01L21/823842 , Y10S438/941
摘要： The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, the insulative capping layer, and the conductive gate layer are patterned and etched to form a first set of conductive gate constructions over the substrate. A dielectric material is formed and planarized over the first set of gate constructions. Thereafter, the insulative capping layer and the conductive gate layer are patterned and etched to form a second set of conductive gate constructions over the substrate. Other aspects and implementations are contemplated.
摘要翻译：本发明包括制造多组场效应晶体管的方法。在一个实施方案中，在绝缘覆盖层上形成蚀刻停止层，所述绝缘覆盖层形成在形成在衬底上的导电栅极层上。蚀刻停止层，绝缘覆盖层和导电栅极层被图案化和蚀刻以在衬底上形成第一组导电栅极结构。在第一组栅极结构上形成并平坦化介电材料。此后，对绝缘覆盖层和导电栅极层进行构图和蚀刻，以在衬底上形成第二组导电栅极结构。考虑了其他方面和实现。

64. 发明授权

US06787833B1 Integrated circuit having a barrier structure 有权
标题翻译：具有阻挡结构的集成电路
公开(公告)号：US06787833B1
公开(公告)日：2004-09-07
申请号：US09653640
申请日：2000-08-31
申请人： Fred Fishburn
发明人： Fred Fishburn
IPC分类号： H01L27108
CPC分类号： H01L21/76831 , H01L21/76802 , H01L21/7687 , H01L21/76877 , H01L27/10855 , H01L2924/0002 , H01L2924/00
摘要： This invention relates to contact structures for use in integrated circuits and methods of fabricating contact structures. In one embodiment, a contact structure includes a conductive layer, one or more barrier layers formed above the conductive layer, and a barrier structure encircling the polysilicon layer and the one or more barrier layers. In an alternate embodiment, a contact structure is fabricated by forming a polysilicon layer on a substrate, forming a tungsten nitride layer above the polysilicon layer, and etching the polysilicon layer and the tungsten nitride layer to a level below the surface of a substrate structure. A silicon nitride layer is formed above the tungsten nitride layer, and a ruthenium silicide layer is formed above the silicon nitride layer. The ruthenium silicide layer is then polished.
摘要翻译：本发明涉及用于集成电路的接触结构和制造接触结构的方法。在一个实施例中，接触结构包括导电层，形成在导电层之上的一个或多个阻挡层，以及环绕多晶硅层和一个或多个阻挡层的阻挡结构。在替代实施例中，通过在衬底上形成多晶硅层，在多晶硅层上形成氮化钨层，并将多晶硅层和氮化钨层蚀刻到衬底结构表面以下的水平来制造接触结构。在氮化硅层之上形成氮化硅层，在氮化硅层的上方形成硅化钌层。然后抛光钌化硅层。

65. 发明授权

US06707088B2 Method of forming integrated circuitry, method of forming a capacitor, method of forming DRAM integrated circuitry and DRAM integrated category 有权
标题翻译：集成电路，包括DRAM集成电路
公开(公告)号：US06707088B2
公开(公告)日：2004-03-16
申请号：US10209820
申请日：2002-07-31
申请人： Fred Fishburn
发明人： Fred Fishburn
IPC分类号： H01L27108
CPC分类号： H01L27/10852 , H01L27/10811 , H01L27/10814 , H01L27/10885 , H01L28/90 , Y10S257/906 , Y10S257/908
摘要： In one implementation, integrated circuitry includes a first capacitor electrode layer received over a substrate. A capacitor dielectric layer is received over the first capacitor electrode layer. The capacitor dielectric layer has an edge terminus. A second capacitor electrode layer is received over the capacitor dielectric layer. The first capacitor electrode layer and the second capacitor electrode layer, respectively, have opposing lateral edges. The capacitor dielectric layer edge terminus is laterally coincident with at least a portion of one of the opposing lateral edges of the second capacitor electrode layer. An insulative silicon nitride including cap is received over the capacitor dielectric layer edge terminus and the one opposing lateral edge of the second capacitor electrode layer. The cap does not contact any portion of the opposing lateral edges of the first capacitor electrode layer. Other aspects and implementations are disclosed.
摘要翻译：在一个实现中，集成电路包括接收在衬底上的第一电容器电极层。电容器电介质层被接收在第一电容器电极层上。电容器介电层具有边缘末端。第二电容器电极层被接收在电容器介电层上。第一电容器电极层和第二电容器电极层分别具有相对的横向边缘。电容器电介质层边缘终端与第二电容器电极层的相对横向边缘中的一个的至少一部分横向一致。包括盖的绝缘氮化硅被接收在电容器电介质层边缘末端和第二电容器电极层的一个相对侧边缘之上。盖不接触第一电容器电极层的相对侧边缘的任何部分。公开了其他方面和实现。

66. 发明授权

US06613671B1 Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby 失效
标题翻译：导电连接形成方法，氧化还原方法和由此形成的集成电路
公开(公告)号：US06613671B1
公开(公告)日：2003-09-02
申请号：US09518511
申请日：2000-03-03
申请人： Dinesh Chopra , Fred Fishburn
发明人： Dinesh Chopra , Fred Fishburn
IPC分类号： H01L2144
CPC分类号： H01L21/76849 , H01L21/76858 , H01L21/76867 , H01L21/76886 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/45 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05546 , H01L2224/05647 , H01L2224/13099 , H01L2224/45147 , H01L2224/48463 , H01L2224/48847 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01072 , H01L2924/01327 , H01L2924/05042 , H01L2924/14 , Y10T29/49156 , Y10T29/49165 , H01L2924/00014 , H01L2924/00
摘要： A conductive connection forming method includes forming a first layer including a first metal on a substrate and forming a second layer including a second metal different from the first metal on the first layer. At least a part of the first layer may be transformed to an alloy material including the first and second metals. A conductive connection may be formed to the alloy material. The alloy material may be less susceptible to formation of metal oxide compared to the first metal. By way of example, transforming the first layer may include annealing the first and second layer. An exemplary first metal includes copper, and an exemplary second metal includes aluminum, titanium, palladium, magnesium, or two or more such metals. The alloy material may be an intermetallic. A conductive connection may be formed to the alloy layer. An integrated circuit includes a semiconductive substrate, a layer including a first metal over the substrate, and a layer of alloy material within the first metal including layer. The alloy material layer may include the first metal and a second metal different from the first metal. The alloy material may be an intermetallic. A conductive connection may be formed on the alloy layer.
摘要翻译：导电连接形成方法包括在基板上形成包括第一金属的第一层，并在第一层上形成包含不同于第一金属的第二金属的第二层。可以将第一层的至少一部分转变成包括第一和第二金属的合金材料。可以对合金材料形成导电连接。与第一金属相比，合金材料可能不太容易形成金属氧化物。作为示例，转换第一层可以包括退火第一层和第二层。示例性的第一金属包括铜，并且示例性的第二金属包括铝，钛，钯，镁或两种或更多种这样的金属。合金材料可以是金属间化合物。可以向合金层形成导电连接。集成电路包括半导体衬底，在衬底上包括第一金属的层以及在第一金属包括层内的合金材料层。合金材料层可以包括第一金属和不同于第一金属的第二金属。合金材料可以是金属间化合物。可以在合金层上形成导电连接。

67. 发明申请

US20080113501A1 Methods of Forming Semiconductor Constructions 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US20080113501A1
公开(公告)日：2008-05-15
申请号：US11971747
申请日：2008-01-09
申请人： Terrence McDaniel , Scott Southwick , Fred Fishburn
发明人： Terrence McDaniel , Scott Southwick , Fred Fishburn
IPC分类号： H01L21/44
CPC分类号： H01L27/10885 , H01L27/10852 , H01L27/10894 , H01L27/10897 , H01L28/90
摘要： The invention includes methods of forming semiconductor constructions in which electrically conductive structures are formed between bitlines to electrically connect with storage node contacts. The bitlines can be formed within trenches having faceted top portions. The invention also includes semiconductor structures containing trenches with faceted top portions, and containing bitlines within the trenches.
摘要翻译：本发明包括形成半导体结构的方法，其中在位线之间形成导电结构以与存储节点接触电连接。位线可以形成在具有多边形顶部的沟槽内。本发明还包括含有具有多面顶部的沟槽并且在沟槽内包含位线的半导体结构。

68. 发明授权

US07329607B2 Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby 有权
标题翻译：导电连接形成方法，氧化还原方法和由此形成的集成电路
公开(公告)号：US07329607B2
公开(公告)日：2008-02-12
申请号：US10620468
申请日：2003-07-15
申请人： Dinesh Chopra , Fred Fishburn
发明人： Dinesh Chopra , Fred Fishburn
IPC分类号： H01L21/44
CPC分类号： H01L21/76849 , H01L21/76858 , H01L21/76867 , H01L21/76886 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/45 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05546 , H01L2224/05647 , H01L2224/13099 , H01L2224/45147 , H01L2224/48463 , H01L2224/48847 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01072 , H01L2924/01327 , H01L2924/05042 , H01L2924/14 , Y10T29/49156 , Y10T29/49165 , H01L2924/00014 , H01L2924/00
摘要： A conductive connection forming method includes forming a first layer comprising a first metal on a substrate and forming a second layer comprising a second metal different from the first metal on the first layer. At least a part of the first layer may be transformed to an alloy material comprising the first and second metals. A conductive connection may be formed to the alloy material. The alloy material may be less susceptible to formation of metal oxide compared to the first metal. By way of example, transforming the first layer may comprise annealing the first and second layer. An exemplary first metal comprises copper, and an exemplary second metal comprises aluminum, titanium, palladium, magnesium, or two or more such metals. The alloy material may be an intermetallic. A conductive connection may be formed to the alloy layer. An integrated circuit includes a semiconductive substrate, a layer comprising a first metal over the substrate, and a layer of alloy material within the first metal comprising layer. The alloy material layer may comprise the first metal and a second metal different from the first metal. The alloy material may be an intermetallic. A conductive connection may be formed on the alloy layer.
摘要翻译：导电连接形成方法包括在基板上形成包括第一金属的第一层，并在第一层上形成包含不同于第一金属的第二金属的第二层。可以将第一层的至少一部分转变成包含第一和第二金属的合金材料。可以对合金材料形成导电连接。与第一金属相比，合金材料可能不太容易形成金属氧化物。作为示例，转换第一层可以包括退火第一层和第二层。示例性的第一金属包括铜，并且示例性的第二金属包括铝，钛，钯，镁或两种或更多种这样的金属。合金材料可以是金属间化合物。可以向合金层形成导电连接。集成电路包括半导体衬底，在衬底上包括第一金属的层以及在第一金属包含层内的合金材料层。合金材料层可以包括第一金属和不同于第一金属的第二金属。合金材料可以是金属间化合物。可以在合金层上形成导电连接。

69. 发明申请

US20070141777A1 Method of forming a contact using a sacrificial structure 有权
公开(公告)号：US20070141777A1
公开(公告)日：2007-06-21
申请号：US11706690
申请日：2007-02-15
申请人： Fred Fishburn , Forest Chen , John Drynan
发明人： Fred Fishburn , Forest Chen , John Drynan
IPC分类号： H01L21/8242
CPC分类号： H01L21/7687 , H01L23/485 , H01L27/10814 , H01L27/10855 , H01L28/84 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a double-sided capacitor using at least one sacrificial structure, such as a sacrificial liner or a sacrificial plug. A sacrificial liner is formed along sidewalls of at least one opening in an insulating layer on a semiconductor wafer. A first conductive layer is then formed over the sacrificial liner. The sacrificial liner is then selectively removed to expose a first surface of the first conductive layer without damaging exposed components on the semiconductor wafer. Removing the sacrificial liner forms an open space adjacent to the first surface of the first conductive layer. A dielectric layer and a second conductive layer are formed in the open space, producing the double-sided capacitor. Methods of forming a double-sided capacitor having increased capacitance and a contact are also disclosed. In addition, an intermediate semiconductor device structure including at least one sacrificial structure is also disclosed.

70. 发明授权

US07220663B2 Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby 有权
标题翻译：导电连接形成方法，氧化还原方法和由此形成的集成电路
公开(公告)号：US07220663B2
公开(公告)日：2007-05-22
申请号：US10916751
申请日：2004-08-11
申请人： Dinesh Chopra , Fred Fishburn
发明人： Dinesh Chopra , Fred Fishburn
IPC分类号： H01L21/44
CPC分类号： H01L21/76849 , H01L21/76858 , H01L21/76867 , H01L21/76886 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/45 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05546 , H01L2224/05647 , H01L2224/13099 , H01L2224/45147 , H01L2224/48463 , H01L2224/48847 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01072 , H01L2924/01327 , H01L2924/05042 , H01L2924/14 , Y10T29/49156 , Y10T29/49165 , H01L2924/00014 , H01L2924/00
摘要： A conductive connection forming method includes forming a first layer comprising a first metal on a substrate and forming a second layer comprising a second metal different from the first metal on the first layer. At least a part of the first layer may be transformed to an alloy material comprising the first and second metals. A conductive connection may be formed to the alloy material. The alloy material may be less susceptible to formation of metal oxide compared to the first metal. By way of example, transforming the first layer may comprise annealing the first and second layer. An exemplary first metal comprises copper, and an exemplary second metal comprises aluminum, titanium, palladium, magnesium, or two or more such metals. The alloy material may be an intermetallic. A conductive connection may be formed to the alloy layer. An integrated circuit includes a semiconductive substrate, a layer comprising a first metal over the substrate, and a layer of alloy material within the first metal comprising layer. The alloy material layer may comprise the first metal and a second metal different from the first metal. The alloy material may be an intermetallic. A conductive connection may be formed on the alloy layer.
摘要翻译：导电连接形成方法包括在基板上形成包括第一金属的第一层，并在第一层上形成包含不同于第一金属的第二金属的第二层。可以将第一层的至少一部分转变成包含第一和第二金属的合金材料。可以对合金材料形成导电连接。与第一金属相比，合金材料可能不太容易形成金属氧化物。作为示例，转换第一层可以包括退火第一层和第二层。示例性的第一金属包括铜，并且示例性的第二金属包括铝，钛，钯，镁或两种或更多种这样的金属。合金材料可以是金属间化合物。可以向合金层形成导电连接。集成电路包括半导体衬底，在衬底上包括第一金属的层以及在第一金属包含层内的合金材料层。合金材料层可以包括第一金属和不同于第一金属的第二金属。合金材料可以是金属间化合物。可以在合金层上形成导电连接。

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