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61. 发明专利

JP2001127467A PRINTED BOARD 失效
公开(公告)号：JP2001127467A
公开(公告)日：2001-05-11
申请号：JP30350399
申请日：1999-10-26
申请人： HITACHI LTD
发明人： YAMAMOTO MASAYUKI , TAKEWA HIDEHITO , KUROSAWA KENICHI
IPC分类号： G06F1/18 , H05K1/02 , H05K7/14
摘要： PROBLEM TO BE SOLVED: To provide a printed board which can be applied to both industrial personal computers and panel computers, thus saving time and cost for designing. SOLUTION: On a printed board 1, mounted with expansion board connectors and expansion card slots containing common signal line groups 4, 5 and 6, the line groups 4, 5, and 6 are arranged in an L-form and foot prints 3 and 10 for expansion card slots are arranged in both vertical and horizontal directions, so that the mounting positions of expansion card slots can be changed. Accordingly, the printed board 1 is made so that it can be applied to both industrial computers and panel computers.

62. 发明专利

JP2000330929A BURST TRANSFER CONTROL METHOD AND DATA TRANSFER SYSTEM 失效
公开(公告)号：JP2000330929A
公开(公告)日：2000-11-30
申请号：JP14459399
申请日：1999-05-25
申请人： HITACHI LTD
发明人： ISHIKURA HIDEJI , KUROSAWA KENICHI , TAKEWA HIDEHITO , OGURA MAKOTO
IPC分类号： G06F13/28
摘要： PROBLEM TO BE SOLVED: To improve the use efficiency of a bus by optimizing burst transfer size by a system which is variable in the maximum burst transfer quantity of a reception side. SOLUTION: When the number of pieces of transmit data stored in a memory 9 from an input/output device 3 exceeds burst transmission size (TXDC), an input/output controller 1 as an initiator sets the TXDC in a transmission counter 15 when a transmission is requested and actuates a PCI controller 11 to transfer the data to a target-side CPU 2 up to the transmission counter value successively by the data width of the PCI bus 5 at a time. To receiving a transmission, data are transferred similarly. If a disconnection request is made by the target side in burst transfer, the data transfer is interrupted, so the initiator size makes a restart. An MPU 9 monitors a PIC monitor 12 which counts the frequency of actuation and the frequency of disconnection separated by the transmission and reception and periodically repeats an updating processing for subtracting the bus data width from the TXDC (or RXDC) until the generation frequency of disconnection becomes a threshold less than the frequency of actuation.

63. 发明专利

JP2000013462A COMMUNICATION CONTROLLER 失效
公开(公告)号：JP2000013462A
公开(公告)日：2000-01-14
申请号：JP17434198
申请日：1998-06-22
申请人： HITACHI LTD
发明人： ISHIKURA HIDEJI , KUROSAWA KENICHI , OKURA TAKANORI , YAMADA TSUTOMU
IPC分类号： H04L29/06 , H04L12/40
摘要： PROBLEM TO BE SOLVED: To provide cyclic transfer which fully utilizes the performance of a transmission line by performing an operation by switching plural communication protocols that are completely different on the same transmission line. SOLUTION: This communication controller 8 switches the connection of a system bus 9 and a cyclic transfer data processing circuit 7 by means of a bus changeover switch 13. The controller 8 is a controller which performs communication protocol control conforming to IEEE802.3 and when it is connected to the bus 9, it performs data transmission and reception with many devices with an IEEE802.3 communication protocol in the control of an MPU 10 according to a control program stored in a memory 6 via a transmission line 1. Also, when it is connected to the circuit 7, it transmits frame data of a self-node which is transmitted from the circuit 7 in an IEEE802.3 physical specification from the line 1 by the control of the circuit 7.

64. 发明专利

JPH11338833A MULTIPROCESSOR TYPE CONTROLLER AND SCALABLE CONTROLLER SYSTEM 失效
公开(公告)号：JPH11338833A
公开(公告)日：1999-12-10
申请号：JP14078898
申请日：1998-05-22
申请人： HITACHI LTD
发明人： TAKEWA HIDEHITO , OGURA MAKOTO , ISHIKURA HIDEJI , MATSUDA KOJI , KUROSAWA KENICHI , TAKAHASHI YOSHIAKI
IPC分类号： G06F12/14 , G06F9/46 , G06F9/48 , G06F15/16
摘要： PROBLEM TO BE SOLVED: To improve independence between processors in the case of an interruption notice and to make compatible a common program in initializing processing and independence between processors. SOLUTION: Concerning the multiprocessor type controller equipped with plural processors 101-102 and a shared memory 112, this controller is provided with a boundary register for holding the boundaries of areas dividing the shared memory 112 for each processor, comparator for comparing the access address of the shared memory 112 with the boundary register, memory control part 107 for limiting the access of the processor based on the compared result of the comparator, interruption control part 106 for reporting interruption according to a mask register for masking an interruption factor for each processor, and identification register for returning a different value through the processor at the reading source. Thus, the independence of processors is improved by the selective notice of interruption while protecting the areas of the shared memory 112 in ordinary processing and the processing when started up can be made common by the identification register.

65. 发明专利

JPH11134251A SEQUENCE CONTROL METHOD AND DEVICE 失效
公开(公告)号：JPH11134251A
公开(公告)日：1999-05-21
申请号：JP29236097
申请日：1997-10-24
申请人： HITACHI LTD
发明人： OGURA MAKOTO , KUROSAWA KENICHI , OKAMOTO TADASHI
IPC分类号： G06F12/06
摘要： PROBLEM TO BE SOLVED: To provide a sequence controller capable of updating by latest data even in the case that the processing cycle of a sequence processing is short in the asynchronous parallel processings of an input/output processing and the sequence processing. SOLUTION: A dual port memory accessible from an input/output unit 9 and a CPU unit 1 is provided for plural banks 5-7 and a CPU 1 confirms the transfer completion of the input/output unit 9 at the end of the sequence processing and instructs bank changeover to a memory management unit 16. The memory management unit 16 is provided with a register 15 or the like for indicating the transfer completion by the input/output unit 9 and the register 4 provided with bank changeover logic and switches the addresses of the dual port memory accessed by the CPU unit 1 and the input/output unit 9 when a transfer completion flag is set and the bank changeover is instructed. Thus, even in the case that an input/output processing cycle is longer than a sequence processing cycle, the processing cycle of the latter is guaranteed to be long practically.

66. 发明专利

JPH1141178A OPTICAL COMMUNICATION METHOD, OPTICAL REPEATER AND OPTICAL COMMUNICATION SYSTEM 失效
公开(公告)号：JPH1141178A
公开(公告)日：1999-02-12
申请号：JP19699297
申请日：1997-07-23
申请人： HITACHI LTD
发明人： ARITA YUTAKA , NAKAMIGAWA TETSUAKI , KUROSAWA KENICHI , FUKUMARU HIROAKI , OGAWA HISAO
IPC分类号： H04B10/00 , H04B10/07 , H04B10/27 , H04L12/28 , H04L12/46 , H04B10/20 , H04B10/08 , H04B10/24
摘要： PROBLEM TO BE SOLVED: To improve a noise proofing property by partial optical communication in a network by matching driving states of two electric buses connected by an optical fiber with each other. SOLUTION: A bus 20a to connect nodes 30a, 30b is connected with a bus 20b to connect nodes 30c, 30d with optical bus bridge devices 10a, 10b by the optical fiber 50. ON states of the buses 20 (20a, 20b) are observed in a stand-by mode when the bus 20 is not driven by the optical bus bridge devices 10 (10a, 10b). When the bus 20a is changed to the ON state by being driven by the node 30a, the stand-by mode is transferred to an optical output mode and light is outputted from a photoelectric transducer 13a to the optical fiber 50. When the light outputted from the optical fiber 50 is received, the optical bus bridge device 10b is transferred from the stand-by mode to the bus drive mode and the state of the bus 20b is made coincide with that of the bus 20a by performing electric output from a bus driver circuit 11b by the optical bus bridge device 10b. The driving states of the buses 20a, 20b are fetched by the nodes 30b, 30c, 30d.

67. 发明专利

JPH1139253A BUS BRIDGE CIRCUIT AND INFORMATION PROCESSING SYSTEM USING THE CIRCUIT 失效
公开(公告)号：JPH1139253A
公开(公告)日：1999-02-12
申请号：JP19675497
申请日：1997-07-23
申请人： HITACHI LTD
发明人： NAKAMIGAWA TETSUAKI , ARITA YUTAKA , KUROSAWA KENICHI , FUKUMARU HIROAKI , OGAWA HISAO
IPC分类号： G06F13/36 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To accelerate the transmitting speed of an information processing system provided with a plurality of nodes which are connected to each other through buses. SOLUTION: Bus bridge circuits 10 and 20 provided with bus driver circuits for respectively driving buses A and B, photoelectric/electrooptic converters connected to optical fibers, and bus status discriminating circuits which respectively decide the statuses of the bus A and B by receiving signals from the bus driver circuits and the photoelectric/electrooptic converters couple the electric buses A and B with each other through an optical fiber 50 connected with a plurality of nodes 60, 70, 80, and 90.

68. 发明专利

JPH1097462A BIT OPERATION PROCESSOR AND COMPUTER SYSTEM 失效
公开(公告)号：JPH1097462A
公开(公告)日：1998-04-14
申请号：JP24938296
申请日：1996-09-20
申请人： HITACHI LTD
发明人： ARITA YUTAKA , NAKAMIGAWA TETSUAKI , KUROSAWA KENICHI , OKAMOTO TADASHI
IPC分类号： G06F7/38 , G06F7/493 , G06F9/305 , G06F12/02 , G06F15/16 , G06F15/177
摘要： PROBLEM TO BE SOLVED: To fast perform decimal to binary conversion by providing a decimal to binary converter with which an address calculating part converts decimal data into binary data. SOLUTION: A memory address calculating part 105 of a bit operation processor BPU (binary coded decimal) 10 has an operand register 105a and a decimal to binary converter 105b. After the converter 105b converts decimal data of BCD notation which is stored in the register 105a into binary data, the address of data RAM that shows the binary data is accessed by BP-D-ADR (data input signal) 703, and data which sent from the data RAM via BP-D-RDAT (address output signal) 704 is stored in the register 105a. After that, the data is sent to a bit operation executing part 107. Thereby, a user can handle the address of the data RAM in a decimal notation, and also, the control of a hardware can be simplified in comparison with a conventional computer system in which a decimal converter is connected through an I/O device.

69. 发明专利

JPH09245008A DUPLEX DATA MATCHING METHOD AND DUPLEX CONTROLLER 失效
公开(公告)号：JPH09245008A
公开(公告)日：1997-09-19
申请号：JP4734296
申请日：1996-03-05
申请人： HITACHI LTD
发明人： YAMADA TSUTOMU , KUROSAWA KENICHI , KAMINAGA YASUO , MASUI KOJI , OHASHI AKIHIRO
IPC分类号： G06F11/20 , G06F15/16
摘要： PROBLEM TO BE SOLVED: To provide a duplex controller without the need of considering the write timing of duplex data on a CPU side. SOLUTION: A duplex control part 5 is provided with a snoop part 53 for snooping the write data of the shared memory area of a CPU 4 by a branching signal line 30' and controlling transfer through the duplex data butter of plural stages, the arbiter 51 of an IO interface bus 9, an access control part 52 for limiting the bus request grant of the CPUs 1 and 2 and a transmission/reception part 54 for transmitting and receiving the duplex data or the like between a service system and a standby system. In the transfer of the duplex data, in the case that the snoop part 53 of the service system predicts the butter overflow of a first stage (low level), the arbiter 51 of the standby system is instructed to give the bus request of the duplex control part 5 in the standby system priority. Further, in the case of predicting the butter overflow of a second stage (high level), the CPUs 1 and 2 and the IO controller 8 of the present system are made to wait and butter data are transferred.

70. 发明专利

JPH0816474A MULTIPROCESSOR SYSTEM 失效
公开(公告)号：JPH0816474A
公开(公告)日：1996-01-19
申请号：JP14735494
申请日：1994-06-29
申请人： HITACHI LTD
发明人： MORIOKA MICHIO , KUROSAWA KENICHI , NAKAMIGAWA TETSUAKI , ISHIKAWA SUKETAKA
IPC分类号： G06F15/16 , G06F12/08 , G06F15/163 , G06F15/177
摘要： PURPOSE:To guarantee matching at a high speed by storing data information which is registered in other clusters among data in the local memory of own cluster and deciding a range wherein cache memory contents should be matched. CONSTITUTION:A cluster 100 is constituted by connecting plural processors 200 equipped with cache memories 250, a cluster communication controller 500 equipped with an export directory 600, and a local memory 400 to a processor memory interface device 300. Then plural clusters 100 are connected to a cluster bus 2200 through the cluster communication controller 500 to form large-scale multiprocessor constitution on the whole. When data in the local memory in own cluster 100 are registered in the cache memory 250 of another cluster, the address of the data is registered in the export directory 600 and on the basis of the storage contents, the range wherein the contents of the cache memory 250 are matched is decided.

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