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61. 发明专利

JPH01237766A DATA PROCESSOR AND PICTURE DATA PROCESSING SYSTEM USING DATA PROCESSOR 失效
公开(公告)号：JPH01237766A
公开(公告)日：1989-09-22
申请号：JP6324088
申请日：1988-03-18
申请人： HITACHI LTD
发明人： SAGESAKA YASUHIRO , KANEKO KENJI , NAKAGAWA TETSUYA , MIYAMOTO MASABUMI , HAGIWARA YOSHIMUNE
IPC分类号： G06F17/10 , G06T1/20
摘要： PURPOSE:To attain high speed arithmetic for the data of double accuracy by executing the prescribed connection of a data bus to a multiplexer for arithmetic and logic operation and selecting the data bus, etc., in a picture data system to execute the multiplication logic operation and multiplication processing of (n)-bit picture data. CONSTITUTION:The (n)-bit data from a data memory bank 104 through an (n)-bit data transferring bus 122 and 2n-bit output data from a general register 106 are inputted to a multiplexer 107. Then, the (n)-bit data through (n)-bit data transferring buses 121-123 and the 2n-bit data from an output register 110 of a multiplied result are added to a multiplexer 108. The outputs of these multiplexers 107 and 108 are obtained as an input and the arithmetic processing is executed by a arithmetic and logic computing element 105. For these multiplexers 107 and 108, a control signal 130 is controlled and the (n)-bit data or the 2n-bit data are selected and outputted. Then, without using the 2n-bit data through the register 110, the arithmetic and logic operation of the double accuracy data by the 2n-bit data can be executed at a high speed with one machine cycle.

62. 发明专利

JPH01166221A INFORMATION PROCESSOR 失效
公开(公告)号：JPH01166221A
公开(公告)日：1989-06-30
申请号：JP32411287
申请日：1987-12-23
申请人： HITACHI LTD
发明人： KIUCHI ATSUSHI , KANEKO KENJI , NAKAGAWA TETSUYA , UEDA HIROTADA , HAGIWARA YOSHIMUNE
IPC分类号： G06F9/22 , G06F9/28 , G06F9/30 , G06F9/38
摘要： PURPOSE:To improve information processing ability by dividing all control functions into those having the long periods of executing time and others having the short periods respectively and validating the field where the control functions of long periods are described at every other fixed interval of a program address space. CONSTITUTION:An instruction code 201 is divided into a 1st field 202 and a 2nd field 203. The control functions having the short period of executing time are described in the field 202 together with the control functions having the long periods described in the field 203 respectively. Thus the instruction executing intervals are different from each other at every field and therefore the address signals 112 and 113 supplied to address decoders 103 and 104 respectively have different types from each other. Furthermore the instruction codes 116 and 117 have different types of instruction executing timing for separate production of timing signals 115 and 114 respectively. In such a way, the executing speeds can be set at every field and therefore the overall processing speed is increased even with a parallel working processor having a long horizontal instruction code.

63. 发明专利

JPS63168045A GATE PROTECTIVE CIRCUIT 失效
公开(公告)号：JPS63168045A
公开(公告)日：1988-07-12
申请号：JP31313086
申请日：1986-12-29
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ISHIDA JUN , KANEKO KENJI , KIUCHI ATSUSHI , HAGIWARA YOSHIMUNE , UEDA HIROTADA
IPC分类号： H01L29/78 , H01L21/8234 , H01L27/02 , H01L27/088
摘要： PURPOSE:To prevent the electrostatic breakdown of gates by utilizing the ON resistances of MOSFETs. CONSTITUTION:Elements N1 and N2 are longitudinally connected, a MOSFET M1 or M2 is turned-ON according to whether the input potential of the N1 is high or low and the inverted signal of input is turned input to the gates of MOSFETs M3 and M4. The input to the gates of the M3 and the M4 has the ON resistances of the M1 and the M2 of several kOMEGA and these have a role for protecting the gates. The elements N1 and N2 are valid for an arbitrary logical element and the need to provide an exclusive protection against the inputs of the longitudinally connected elements in an integrated circuit is eliminated. Accordingly, the circuit to utilize the ON resistances of the MOSFETs has inevitably a function for protecting the gates from the viewpoint of its structure.

64. 发明专利

JPS63118878A LSI DESIGNING DEVICE 失效
公开(公告)号：JPS63118878A
公开(公告)日：1988-05-23
申请号：JP26373786
申请日：1986-11-07
申请人： HITACHI LTD
发明人： ISHII NAOKO , KANEKO KENJI , TAKAGI KATSUAKI , AOKI MASAO , MASUDA HIROO , MATSUO HITOSHI , SHIMADA SHOZO
IPC分类号： H03K19/00 , G06F17/50 , H01L21/82
摘要： PURPOSE:To design an LSI satisfying characteristic specifications in a short time by applying an optimum designing method to a logical design and function design that require extremely labor and time. CONSTITUTION:LSI characteristics (y) is approximated by a function formula including a design parameter (x) and the optimum design parameter satisfying the target specifications is extracted out of said function formula by a design means. A CAD system applying the maximum design parameter comprises a simulation means for timing, logic and function designs that require the largest manpower and the longest design period. Thus the LSI designing manpower and designing period are extraordinarily reduced. In this system, P pairs of LSI characteristics are obtained with respect to P pairs of design parameters given in the form of a design matrix produced by desired procedures. Thus a LSI characteristic simulator group is carried out by P times. Based on these execution results, a model parameter is produced for a function approximating expression of the characteristic (y) to the parameter (x).

65. 发明专利

JPS63113659A ELEMENT FOR MULTIPROCESSOR 失效
公开(公告)号：JPS63113659A
公开(公告)日：1988-05-18
申请号：JP25937586
申请日：1986-10-30
申请人： HITACHI LTD , HITACHI MAXELL , HITACHI VLSI ENG
发明人： KANEKO KENJI , UEDA HIROTADA , NAKAGAWA TETSUYA , KIUCHI ATSUSHI , HAGIWARA YOSHIMUNE , TAKAMORI HIROSHI , TOYOMASU NARUNORI
IPC分类号： G06F15/16 , G06F9/38 , G06F15/173 , G06F15/177 , G06F15/80 , G06T1/20
摘要： PURPOSE:To make simultaneous communications between a host processor and plural processors by comparing processor numbers with a number stored in a register, dimension by dimension, and receiving a command according to the comparison result. CONSTITUTION:A PE checks whether an (x)-directional number 502 and a (y)- directional number 503 sent from a host processor are zero or coincident with two-dimensional PE numbers 701 and 702 which are stored in reference registers respectively and assigned to the PE by using comparators 704 and 707. Namely, when the number 502 is zero or coincident with the numbers 502 and 701, a coincidence signal is outputted. Similarly, when the number 503 is zero or coincident with the numbers 502 and 702, the coincidence signal is outputted. Those coincidence signals are ANDed by an AND gate 709 to decide two-dimensional PE numbers in an (x)-row and (y)-column direction. Then, those coincidence signal are used to determine whether or not a command 504 from the host processor is inputted from an input part 710 or not.

66. 发明专利

JPS63100763A INTEGRATED CIRCUIT 失效
公开(公告)号：JPS63100763A
公开(公告)日：1988-05-02
申请号：JP24529686
申请日：1986-10-17
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG , HITACHI VLSI ENG , HITACHI MAXELL
发明人： NAKAGAWA TETSUYA , KANEKO KENJI , HAGIWARA YOSHIMUNE , KIUCHI ATSUSHI , SUZUKI NORIYASU , TOYOMASU TAKANO , TAKAMORI HIROSHI , KISHI KAZUMASA
IPC分类号： H01L27/04 , H01L21/822
摘要： PURPOSE:To lead out arbitrary input/output terminals to input terminals for a VLSI in a selected order by forming a peripheral bus along the outer circumference of a VLSI chip among input/output terminals and a plurality of sub-LSIs. CONSTITUTION:Subchips in the number of k of a VLSI chip 100 constituted of sub-LSIs 104-107 have n1-nk input/output signals respectively, and some of them are connected by an internal bus 103 through the interfaces. The chip 100 has a bus 102 going around the chip 100 among input/output devices 101 and the chips 104-107. The bus 102 is connected to all or one part of input/ output signals for the chips 1-k, and connected to pads or the devices 101 through a selector. Input/output signals for arbitrary subchips can be led out to the pads in a selected order by using the bus 102.

67. 发明专利

JPS639410B2 失效
公开(公告)号：JPS639410B2
公开(公告)日：1988-02-29
申请号：JP6232378
申请日：1978-05-26
申请人： HITACHI LTD
发明人： KANEKO KENJI , OKABE TAKAHIRO , NAGATA MINORU
IPC分类号： H03K19/091 , H03F3/04 , H03K5/02 , H03K17/60

68. 发明专利

JPS62285152A DATA PROCESSOR 失效
公开(公告)号：JPS62285152A
公开(公告)日：1987-12-11
申请号：JP12790586
申请日：1986-06-04
申请人： HITACHI LTD
发明人： KIUCHI ATSUSHI , KANEKO KENJI , NAKAGAWA TETSUYA , HAGIWARA YOSHIMUNE , SAWASE TERUMI , NAKAMURA HIDEO
IPC分类号： G06F9/32 , G06F12/02 , G06F12/06 , G06F13/16
摘要： PURPOSE:To minimize the unused area of a built-in memory by dividing the area of said memory into plural pages and providing a function to each page to designate the application for instruction or data. CONSTITUTION:A group of instructions to be executed are stored in an external memory 603. The output 604 of a program counter 602 is outputted to the outside and an instruction is fetched by an internal instruction bus 106 from the memory 603. When this instruction designates an instruction or data of a memory area, the instruction code on the bus 106 is decoded by a decoder 601 and the outputs are sent to the control outputs 109a-109e of a control circuit 108a. Thus the pages of a memory 104 can be optionally designated for instructions or data. Therefore, the memory areas can be properly distributed for application even though the buses of both instruction and data systems are set independently of each other and the memory areas to store instructions are separated from those to store data.

69. 发明专利

JPS622714A SYNCHRONOUS SEQUENCE CIRCUIT 失效
公开(公告)号：JPS622714A
公开(公告)日：1987-01-08
申请号：JP14039085
申请日：1985-06-28
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KIUCHI ATSUSHI , KANEKO KENJI , ISHIDA JUN , NAKAGAWA TETSUYA , SATOU TOMORU , HAGIWARA YOSHIMUNE
IPC分类号： H03K3/037 , H03K3/356
摘要： PURPOSE:To obtain a stable synchronous sequence circuit having high resistance to the hazard by giving a shift between a fetching time point of the input signal and a fixing time point of the output signal. CONSTITUTION:The logic circuits 102 and 104 form a holding circuit and a delay circuit 103 functions to produce a shift between a holding time point of the holding circuit and a fetching time point of an input signal. A synchronizing clock CLK1 decides the fetching time point of the input signal and a synchronizing clock CLK2 fixes the output signal and actuates the holding circuit. Both input signals S and R are not fixed yet before a time point 201 when the signal CLK1 is enable and the transition starts concurrently with the time point 201 of a synchronizing period. Even in such a case, the output signal Qn is fixed with the correct value as long as the transition is through and stable during a period 204. Thus the output signal Qn (or Qn) is fixed with the correct value even though an unstable state shown by 206 is caused immediately after synchronization. Then this synchronizing sequence circuit has no malfunction unlike a conventional case.

70. 发明专利

JPS61200459A SYSTEM FOR DETECTING FLAW OF MAGNETIC RECORDING MEDIUM 失效
公开(公告)号：JPS61200459A
公开(公告)日：1986-09-05
申请号：JP3874285
申请日：1985-03-01
申请人： HITACHI LTD
发明人： KANEKO KENJI , YAMADA FUJIO
IPC分类号： G01N27/82 , G01R33/12 , G11B5/00 , G11B5/84 , G11B20/18
摘要： PURPOSE:To reduce effect due to the irregularity of a read voltage value, by a method wherein reading voltage is compared at mutually different slice levels and the absence of a flaw is discriminated when said reading voltage is higher than the max. value of said levels and a registered flaw is discriminated when lower than the min. value and, when said voltage is the intermediate level, measurement is performed several times and flaw absence/registered flaw is discriminated by a majority theory. CONSTITUTION:Three different slice levels 21, 22, 23 are selected so as to be set to 1/2 quantity (x) of irregularity of reading voltage due to the imperfectness of the following capacity to the vibration or servo track of a magnetic head. With respect to an input wave higher than the slice level 21 or lower than the slice level 23, a result high in reproducibility can be obtained by one test and, even with the respect to the input wave being an intermediate level, a test result relatively high in reproducibility can be obtained by performing a test three times. Unless the number of times of an average test are increased to an individual magnetizing reversal position, certification high in reproducibility can be performed with respect to the irregularity of a read voltage value due to the vibration of a magnetic head or the following capacity of a servo system.

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