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1. 发明专利

JPS63100763A INTEGRATED CIRCUIT 失效
公开(公告)号：JPS63100763A
公开(公告)日：1988-05-02
申请号：JP24529686
申请日：1986-10-17
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG , HITACHI VLSI ENG , HITACHI MAXELL
发明人： NAKAGAWA TETSUYA , KANEKO KENJI , HAGIWARA YOSHIMUNE , KIUCHI ATSUSHI , SUZUKI NORIYASU , TOYOMASU TAKANO , TAKAMORI HIROSHI , KISHI KAZUMASA
IPC分类号： H01L27/04 , H01L21/822
摘要： PURPOSE:To lead out arbitrary input/output terminals to input terminals for a VLSI in a selected order by forming a peripheral bus along the outer circumference of a VLSI chip among input/output terminals and a plurality of sub-LSIs. CONSTITUTION:Subchips in the number of k of a VLSI chip 100 constituted of sub-LSIs 104-107 have n1-nk input/output signals respectively, and some of them are connected by an internal bus 103 through the interfaces. The chip 100 has a bus 102 going around the chip 100 among input/output devices 101 and the chips 104-107. The bus 102 is connected to all or one part of input/ output signals for the chips 1-k, and connected to pads or the devices 101 through a selector. Input/output signals for arbitrary subchips can be led out to the pads in a selected order by using the bus 102.

2. 发明专利

JPS62146008A SELECTING CIRCUIT 失效
公开(公告)号：JPS62146008A
公开(公告)日：1987-06-30
申请号：JP28819585
申请日：1985-12-20
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG , HITACHI VLSI ENG
发明人： KIUCHI ATSUSHI , ISHIDA JUN , KANEKO KENJI , NAKAGAWA TETSUYA , SATOU TOMORU , MASUMURA SHIGEKI , SUZUKI NORIYASU , HAGIWARA YOSHIMUNE
IPC分类号： H03K17/00 , H03K17/693
摘要： PURPOSE:To make a quick operation possible by selecting one signal in each period from (n-1)-number of input signals taken in from the external and one input signal, which is obtained by feeding back the output of the preceding period, to make it unnecessary to set the time when a decoding signal for control is settled. CONSTITUTION:(n-1)-Number of input signals out of n-number of input signals to be selected are input signals from the external, and remainder one is the signal obtained by feeding back the output of a selecting circuit 409 or a logic circuit 406 following the circuit 409. These n-number of input signals are controlled by a control signal C410 for selection. If any of (n-1)-number of external input signals is not selected, the control signal C410 selects certainly the feedback signal of the state in the preceding period. This feedback signal is selected then to eliminate the no-selection mode, and thereby, the output of the selecting circuit 409 is certainly outputted in each period. Thus, a preceding erroneous selecting signal is cancelled immediately with a correct selecting signal even if the erroneous signal is temporarily selected in the initials stage of synchronization.

3. 发明专利

JPS63113659A ELEMENT FOR MULTIPROCESSOR 失效
公开(公告)号：JPS63113659A
公开(公告)日：1988-05-18
申请号：JP25937586
申请日：1986-10-30
申请人： HITACHI LTD , HITACHI MAXELL , HITACHI VLSI ENG
发明人： KANEKO KENJI , UEDA HIROTADA , NAKAGAWA TETSUYA , KIUCHI ATSUSHI , HAGIWARA YOSHIMUNE , TAKAMORI HIROSHI , TOYOMASU NARUNORI
IPC分类号： G06F15/16 , G06F9/38 , G06F15/173 , G06F15/177 , G06F15/80 , G06T1/20
摘要： PURPOSE:To make simultaneous communications between a host processor and plural processors by comparing processor numbers with a number stored in a register, dimension by dimension, and receiving a command according to the comparison result. CONSTITUTION:A PE checks whether an (x)-directional number 502 and a (y)- directional number 503 sent from a host processor are zero or coincident with two-dimensional PE numbers 701 and 702 which are stored in reference registers respectively and assigned to the PE by using comparators 704 and 707. Namely, when the number 502 is zero or coincident with the numbers 502 and 701, a coincidence signal is outputted. Similarly, when the number 503 is zero or coincident with the numbers 502 and 702, the coincidence signal is outputted. Those coincidence signals are ANDed by an AND gate 709 to decide two-dimensional PE numbers in an (x)-row and (y)-column direction. Then, those coincidence signal are used to determine whether or not a command 504 from the host processor is inputted from an input part 710 or not.

4. 发明专利

JPH02288916A DIGITAL PEAK/VALLEY DETECTING CIRCUIT 失效
公开(公告)号：JPH02288916A
公开(公告)日：1990-11-28
申请号：JP3418990
申请日：1990-02-15
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： CHIYANDORABEDAN ENU PATERU , RICHIYAADO DABURIYUUEMU BURASU , KIUCHI ATSUSHI , INADA HIROMITSU
IPC分类号： G06F7/02 , G01R19/04
摘要： PURPOSE:To detect addresses of a peak value and a valley value by storing value data and its address data in a valley value data storage means and a valley value address storage means respectively at the time when supplied value data is smaller than a valley value. CONSTITUTION:A minimum value and a maximum value are initially set to a peak value data register 18 and a valley value data register 20 respectively, and contents of the peak value data register 18 are successively rewritten with the peak value of value data included in digital data when this digital data including address data and value data is successively supplied. In the same manner, contents of the valley value data register 20 are successively rewritten with the valley value of value data included in the digital data, and the value of a valley value address register 16 is updated to address data corresponding to stored valley value data. Thus, not only the peak value and the valley value but also addresses of the peak value and the valley value are detected.

5. 发明专利

JPH031229A ARITHMETIC UNIT 失效
公开(公告)号：JPH031229A
公开(公告)日：1991-01-07
申请号：JP12794490
申请日：1990-05-17
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： CHIYANDORABEDAN ENU PATERU , RICHIYAADO DABURIYUUEMU BURASU , KIUCHI ATSUSHI , INADA HIROMITSU
IPC分类号： G06F7/38 , G06F7/483 , G06F7/52 , G06F7/523 , G06F7/57 , G06F17/10
摘要： PURPOSE:To support the processing arithmetic operation of a high functional digital signal flexibly for manifold requests by employing a constitution capable of selecting and connecting the input/output of a multiplication means, an arithmetic and logic unit, a barrel shifting means, and a shifting means. CONSTITUTION:The constitution capable of selecting and connecting the input/ output of the multiplication means 2, the arithmetic and logic unit 12, the barrel shifting means 16, and the shifting means 8 and 10 functions so as to support the processing arithmetic operation of the high functional digital signal flexibly for the manifold requests based on control for the connecting state of the input/ output, etc. And it functions so as to support the processing arithmetic operation of a digital signal with high accuracy with a function proper to the individual functional block of the multiplication means 2, etc. In such a manner, it is possible to obtain an arithmetic unit for a digital processor capable of performing the multiplication processing of numbers with codes or without codes, or that of the number with the code and that without the code.

6. 发明专利

JPS63153636A INFORMATION PROCESSOR 失效
公开(公告)号：JPS63153636A
公开(公告)日：1988-06-27
申请号：JP19446987
申请日：1987-08-05
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KIUCHI ATSUSHI , KANEKO KENJI , ISHIDA JUN , NAKAGAWA TETSUYA , HAGIWARA YOSHIMUNE , UEDA HIROTADA
IPC分类号： G06F9/34 , G06F7/544 , G06F12/02 , G06F17/10 , H03H17/02
摘要： PURPOSE:To obtain an optional tap number by setting an initial address to an optional finite value except zero and returning the address to the initial value if the address is incremented in excess of the final address. CONSTITUTION:The initial address and a restoring address are set respectively to registers 102, 103. An address computing element 104 has a function of increment (+1) or decrement (-1). A comparison deciding circuit 105 compares contents of a register 103 with the output 108 of the arithmetic unit 104 and decides whether or not both are coincident and either the output 108 or the output 109 of the register 102 is selected based on the result of decision to control the outputted selector 106. Thus, after the initial address is set to an optional value except zero, the address computing element 104 executes sequentially the increment to the initial value so as to restore the address to the initial value automatically when the recurrent address is reached.

7. 发明专利

JPS63148346A INFORMATION PROCESSOR 失效
公开(公告)号：JPS63148346A
公开(公告)日：1988-06-21
申请号：JP29703686
申请日：1986-12-12
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KIUCHI ATSUSHI , KANEKO KENJI , ISHIDA JUN , NAKAGAWA TETSUYA , HAGIWARA YOSHIMUNE , AKAZAWA TAKASHI , SATOU TEN
IPC分类号： G06F9/22 , G06F9/30 , G06F9/32 , G06F9/38 , G06F12/06 , G06F15/78
摘要： PURPOSE:To access an incorporated program memory at high speed by making the frequency of operation clocks different at the use of the incorporated program memory and that of an external program memory with each other. CONSTITUTION:The address 106 of a program generated by a program counter 105 is inputted to an inside/outside discriminating circuit 115 to discriminate whether the address 106 is used for an incorporated memory 103 or an external extended memory 104. If it is used for the incorporated memory, pulses having a high frequency are supplied from a clock generating circuit 102 because an output 107 to the clock generating circuit 102 goes to the low level, and the incorporated memory 103 is quickly accessed. Meanwhile, if the address 106 is used for the external extended memory, pulses having a low frequency suitable for the access of the external extended memory are supplied from the clock generating circuit 102 because the output 107 goes to the high level.

8. 发明专利

JPH09311779A MULTIPLIER AND DIGITAL SIGNAL PROCESSOR USING THE SAME 失效
公开(公告)号：JPH09311779A
公开(公告)日：1997-12-02
申请号：JP12948396
申请日：1996-05-24
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： OGATA YASUHIRO , KIUCHI ATSUSHI , IMAI NORITSUGU , NISHIYAMA KUNIHIKO , NOGUCHI YOSHIKI
IPC分类号： G06F7/53 , G06F7/506 , G06F7/52 , G06F7/525 , G06F7/533
摘要： PROBLEM TO BE SOLVED: To speed up single-precision multiplication without increasing the amount of hardware, to process the multiplication (single-precision multiplication) of n-bits ×n-bits with one cycle and the multiplication (double-precision multiplication) of 2n-bits × 2n-bits with four cycles, for example. SOLUTION: A partial product generation circuit 301 having a first control mode (single-precision multiplication mode) generating n/2-pieces of partial products at once and a second control mode (double-precision multiplication mode) generating n/4-pieces of partial products at once from a multiplicand and a multiplier, adders 302 and 303 in a fist stage, which add the partial products generated in the partial product generation circuit 301, selection circuits 305-310 selecting the output of the adders 302 and 303 in the first stage based on the first control mode or the second control mode and adders 311 and 312 in a second stage, which add the outputs of the selection circuits 305-310 are provided.

9. 发明专利

JPH09305377A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH09305377A
公开(公告)日：1997-11-28
申请号：JP12306796
申请日：1996-05-17
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KIUCHI ATSUSHI , IMAI NORITSUGU , OGATA YASUHIRO , HATANO YUJI
IPC分类号： G06F7/00 , G06F15/78
摘要： PROBLEM TO BE SOLVED: To make a wiring distance or a layout area required for wiring small and to reduce the delay time of data transfer required for an arithmetic operation and power consumption by the level change of signals by performing layout so as to arrange a register at a center and to arrange a multiplier and an accumulator respectively on both sides. SOLUTION: The layout is performed so as to arrange the registers R1-R4 at the center and to arrange the multiplier MUL and the accumulator ACC respectively on both sides. Also, the registers R1 and R2 used only in the multiplier MUL in the plural registers R1-R4 are arranged on the side closer to the multiplier MUL further and the registers R3 and R4 used only in the accmulator ACC are arranged on the side closer to the accumulator ACC. Thus, the need of providing an area for unrelated wiring is eliminated. Further, since wires SL1 and SL2 for connecting the registers R1 and R2 used only in the multiplier MUL and the multiplier MUL are not wired to the accumulator ACC, the size of the entire module is reduced.

10. 发明专利

JPH07152557A DIGITAL SIGNAL PROCESSOR 失效
公开(公告)号：JPH07152557A
公开(公告)日：1995-06-16
申请号：JP29800293
申请日：1993-11-29
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： IMAI NORITSUGU , OGATA YASUHIRO , KIUCHI ATSUSHI , HATANO YUJI
IPC分类号： G06F9/32 , G06F9/38
摘要： PURPOSE:To perform many parallel processings by a single instruction, to decrease the number of processing steps, and to reduce the power consumption of a digital signal processor by decoding the instruction codes of different bit lengths and executing a prescribed processing. CONSTITUTION:An instruction memory 120 that undergone the bit extension is prepared only in a fixed address space of an existing instruction memory 110, and only the parts to be processed in parallel are stored in a memory area that undergone the bit extension. The instructions stored in a memory space of an existing instruction bit length are usually executed, and the parallel processing instructions are branched out to the prescribed addresses of the memory 120 as necessary and executed. Therefor, this processor is provided with a means 132 for detecting the bit length of an instruction code and a means 131 for decoding the instruction code and executing a prescribed processing. Furthermore the processor is provided with an operand field 102 for designating the head address of the memory stored with an instruction to be repetitively executed.

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