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61. 发明授权

US08013417B2 Low cost substrates and method of forming such substrates 有权
标题翻译：低成本基板和形成这种基板的方法
公开(公告)号：US08013417B2
公开(公告)日：2011-09-06
申请号：US12469436
申请日：2009-05-20
申请人： Bich-Yen Nguyen , Carlos Mazure
发明人： Bich-Yen Nguyen , Carlos Mazure
IPC分类号： H01L21/70
CPC分类号： H01L21/76256 , H01L21/76254 , Y10T428/24851
摘要： In one embodiment, the invention provides engineered substrates having a support with surface pits, an intermediate layer of amorphous material arranged on the surface of the support so as to at least partially fill the surface pits, and a top layer arranged on the intermediate layer. The invention also provides methods for manufacturing the engineered substrates which deposit an intermediate layer on a pitted surface of a support so as to at least partially fill the surface pits, then anneal the intermediate layer, then assemble a donor substrate with the annealed intermediate layer to form an intermediate structure, and finally reduce the thickness of the donor substrate portion of the intermediate structure in order to form the engineered substrate.
摘要翻译：在一个实施例中，本发明提供了具有表面凹坑的支撑件的工程衬底，布置在支撑件表面上以至少部分地填充表面凹坑的非晶材料的中间层以及布置在中间层上的顶层。本发明还提供了用于制造工程衬底的方法，其将中间层沉积在支撑体的凹坑表面上，以便至少部分地填充表面凹坑，然后退火中间层，然后将施加衬底与退火的中间层组装成形成中间结构，并且最终减小中间结构的施主衬底部分的厚度以形成工程衬底。

62. 发明申请

US20110170343A1 DRAM MEMORY CELL HAVING A VERTICAL BIPOLAR INJECTOR 有权
标题翻译：具有垂直双极性注射器的DRAM存储单元
公开(公告)号：US20110170343A1
公开(公告)日：2011-07-14
申请号：US12942754
申请日：2010-11-09
申请人： Carlos Mazure , Richard Ferrant
发明人： Carlos Mazure , Richard Ferrant
IPC分类号： G11C11/40 , H01L29/786
CPC分类号： H01L29/7841 , G11C11/404 , G11C2211/4016 , H01L27/0711 , H01L27/10802 , H01L29/086 , H01L29/7302
摘要： The invention relates to a memory cell having an FET transistor with a source, a drain and a floating body between the source and the drain, and an injector that can be controlled to inject a charge into the floating body of the FET transistor. The injector includes a bipolar transistor having an emitter, a base and a collector formed by the body of the FET transistor. Specifically, in the memory cell, the emitter of the bipolar transistor is arranged so that the source of the FET transistor serves as the base for the bipolar transistor. The invention also includes a memory array comprising a plurality of memory cells according to the first aspect of the invention, and to methods of controlling such memory cells.
摘要翻译：本发明涉及具有源极，漏极和源极和漏极之间的浮体的FET晶体管的存储单元，以及可以被控制以将电荷注入到FET晶体管的浮动体中的注入器。注射器包括具有由FET晶体管的主体形成的发射极，基极和集电极的双极晶体管。具体地说，在存储单元中，双极型晶体管的发射极配置成使FET晶体管的源极作为双极晶体管的基极。本发明还包括包括根据本发明的第一方面的多个存储器单元的存储器阵列以及控制这种存储器单元的方法。

63. 发明申请

US20110170327A1 DEVICES AND METHODS FOR COMPARING DATA IN A CONTENT-ADDRESSABLE MEMORY 有权
标题翻译：用于比较内容可寻址存储器中的数据的设备和方法
公开(公告)号：US20110170327A1
公开(公告)日：2011-07-14
申请号：US12974916
申请日：2010-12-21
申请人： Carlos Mazure , Richard Ferrant
发明人： Carlos Mazure , Richard Ferrant
IPC分类号： G11C15/04 , H01L27/12
CPC分类号： G11C15/046 , H04L45/7453
摘要： The invention provides a content-addressable memory cell formed by two transistors that are configured so that one of the transistors is for storing a data bit and the other for is storing the complement of the data bit. Each transistor has a back control gate that can be controlled to block the associated transistor. The device also includes a comparison circuit that is configured to operate the first and second transistors in read mode while controlling the back control gate of each of the transistors so as to block the passing transistor if a proposed bit and the stored bit correspond. Then, the presence or absence of current on a source line linked to the source of each of the transistors indicates whether the proposed bit and the stored bit are identical or not. The invention also provides methods for operating the content-addressable memory cells of this invention, as well as content-addressable memories having a plurality of the content-addressable memory cells of this invention.
摘要翻译：本发明提供一种由两个晶体管形成的可内容寻址的存储单元，其被配置为使晶体管中的一个用于存储数据位，而另一个用于存储数据位的补码。每个晶体管具有可控制的阻挡相关晶体管的反向控制栅极。该器件还包括比较电路，其被配置为在读取模式下操作第一和第二晶体管，同时控制每个晶体管的反向控制栅极，以便如果所提出的位和存储的位对应，则阻止通过晶体管。然后，连接到每个晶体管的源极的源极线上的电流的存在或不存在指示所提出的位和存储的位是否相同。本发明还提供了用于操作本发明的内容可寻址存储器单元的方法，以及具有多个本发明的可内容寻址存储单元的可内容寻址存储器。

64. 发明申请

US20110133776A1 ARRAYS OF TRANSISTORS WITH BACK CONTROL GATES BURIED BENEATH THE INSULATING FILM OF A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE 有权
标题翻译：具有后控制栅的晶体管阵列BENEATH BENEATH半导体绝缘体衬底的绝缘膜
公开(公告)号：US20110133776A1
公开(公告)日：2011-06-09
申请号：US12961293
申请日：2010-12-06
申请人： Carlos Mazure , Richard Ferrant
发明人： Carlos Mazure , Richard Ferrant
IPC分类号： H03K19/173 , H01L27/12 , H03K3/01
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/11807
摘要： This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate and including an array of patterns, each pattern being formed by at least one field-effect transistor, each FET transistor having, in the thin film, a source region, a drain region, a channel region, and a front control gate region formed above the channel region. The provided device further includes at least one FET transistor having a pattern including a back control gate region formed in the base substrate beneath the channel region, the back gate region being capable of being biased in order to shift the threshold voltage of the transistor to simulate a modification in the channel width of the transistor or to force the transistor to remain off or on whatever the voltage applied on its front control gate. This invention also provides methods of operating such semiconductor device structures.
摘要翻译：本发明提供了一种半导体器件结构，其形成在传统的绝缘体上半导体（SeOI）衬底上并且包括一组图案，每个图案由至少一个场效应晶体管形成，每个FET晶体管在薄膜中，源极区域，漏极区域，沟道区域和形成在沟道区域上方的前部控制栅极区域。所提供的器件还包括至少一个FET晶体管，其具有包括形成在沟道区域下方的基底衬底中的反向控制栅极区域的图案，所述背栅极区域能够被偏置以便移位晶体管的阈值电压以模拟晶体管的沟道宽度的修改或迫使晶体管保持关断或者在其前控制栅上施加的任何电压。本发明还提供了操作这种半导体器件结构的方法。

65. 发明申请

US20110042780A1 METHODS OF MANUFACTURING SEMICONDUCTOR STRUCTURES AND SEMICONDUCTOR STRUCTURES OBTAINED BY SUCH METHODS 审中-公开
标题翻译：制造半导体结构的方法和采用这种方法获得的半导体结构
公开(公告)号：US20110042780A1
公开(公告)日：2011-02-24
申请号：US12989532
申请日：2009-05-18
申请人： Bich-Yen Nguyen , Carlos Mazure
发明人： Bich-Yen Nguyen , Carlos Mazure
IPC分类号： H01L21/30 , H01L29/02
CPC分类号： H01L21/76254 , H01L21/76256
摘要： In preferred embodiments, this invention provides a semiconductor structure that has a semi-conducting support, an insulating layer arranged on a portion of the support and a semi-conducting superficial layer arranged on the insulating layer. Electronic devices can be formed in the superficial layer and also in the exposed portion of the semi-conducting bulk region of the substrate not covered by the insulating layer. The invention also provides methods of fabricating such semiconductor structures which, starting from a substrate that includes a semi-conducting superficial layer arranged on a continuous insulating layer both of which being arranged on a semi-conducting support, by transforming at least one selected region of a substrate so as to form an exposed semi-conducting bulk region of the substrate.
摘要翻译：在优选实施例中，本发明提供一种半导体结构，其具有半导电支撑件，布置在支撑件的一部分上的绝缘层和布置在绝缘层上的半导电表面层。电子器件可以形成在表面层中，也可以形成在衬底的半导体本体区域的未被绝缘层覆盖的露出部分中。本发明还提供了制造这样的半导体结构的方法，其从包括布置在连续绝缘层上的半导电表面层的衬底开始，两者均布置在半导电支撑件上，通过将至少一个选定区域基板，以形成基板的暴露的半导体本体区域。

66. 发明授权

US07799651B2 Method of treating interface defects in a substrate 有权
标题翻译：处理基材界面缺陷的方法
公开(公告)号：US07799651B2
公开(公告)日：2010-09-21
申请号：US12165365
申请日：2008-06-30
申请人： Carlos Mazure , Ian Cayrefourcq , Konstantin Bourdelle
发明人： Carlos Mazure , Ian Cayrefourcq , Konstantin Bourdelle
IPC分类号： H01L21/331
CPC分类号： H01L21/187 , H01L21/02381 , H01L21/02532 , H01L21/02667 , H01L21/26506 , H01L21/324 , H01L21/76254 , H01L29/045
摘要： The present invention relates to a method of treating a structure produced from semiconductor materials, wherein the structure includes a first and second substrates defining a common interface that has defects. The method includes forming a layer, called the disorganized layer, which includes the interface, in which at least a part of the crystal lattice is disorganized; and reorganizing the crystal lattice of the disorganized layer in order to force the defects back deeper into the first substrate.
摘要翻译：本发明涉及一种处理由半导体材料制成的结构的方法，其中该结构包括限定具有缺陷的公共接口的第一和第二基板。所述方法包括形成称为所述无组织层的层，所述层包括所述界面，其中所述晶格的至少一部分被混杂; 并重新组织无组织层的晶格，以迫使缺陷更深地进入第一衬底。

67. 发明授权

US07407867B2 Method for concurrently producing at least a pair of semiconductor structures that each include at least one useful layer on a substrate 失效
标题翻译：用于同时产生至少一对半导体结构的方法，每个半导体结构在衬底上包括至少一个有用层
公开(公告)号：US07407867B2
公开(公告)日：2008-08-05
申请号：US11509047
申请日：2006-08-24
申请人： Bruno Ghyselen , Cécile Aulnette , Benoĩt Bataillou , Carlos Mazure , Hubert Moriceau
发明人： Bruno Ghyselen , Cécile Aulnette , Benoĩt Bataillou , Carlos Mazure , Hubert Moriceau
IPC分类号： H01L21/20
CPC分类号： H01L21/76254 , Y10S438/977
摘要： A method for producing a semiconductor structure that includes at least one useful layer on a substrate. This method includes providing a source substrate with a zone of weakness therein that defines a relatively thick useful layer between the zone of weakness and a front face of the source substrate; bonding the front face of the source substrate to a support substrate and detaching the useful layer from the source substrate at the zone of weakness to transfer the useful layer to the support substrate; implanting atomic species into a free face of the useful layer to a controlled mean implantation depth therein to form a zone of weakness within the useful layer that defines front and rear useful layers, with the rear useful layer contacting the source substrate and the front useful layer containing a greater concentration of defects; bonding a stiffening substrate to the free face of the front useful layer after implantation of the atomic species; and detaching the front useful layer from the rear useful layer along the zone of weakness to form a semiconductor structure comprising the support substrate and the rear useful layer thereon. The structures obtained can be used in the fields of electronics, optoelectronics or optics.
摘要翻译：一种用于制造半导体结构的方法，所述半导体结构在衬底上包括至少一个有用层。该方法包括提供源极基底中的弱化区域，其在弱化区域和源极基底的前面之间限定相对较厚的有用层; 将源极基板的正面粘合到支撑基板上，并在弱化区域将有用层与源极基板分离，以将有用层转移到支撑基板; 将原子物质植入有用层的自由面中，以在其中形成受控的平均注入深度，以在限定前后有用层的有用层内形成弱化区，其中后部有用层与源极基底和前部有用层接触含有较大浓度的缺陷; 在加入原子物质之后将加强基底粘合到前有用层的自由面上; 并且沿着弱化区从后部有用层分离前部有用层，以形成包括支撑基板和其上的后部有用层的半导体结构。所获得的结构可用于电子学，光电子学或光学领域。

68. 发明授权

US07387947B2 Method for transferring a thin layer including a controlled disturbance of a crystalline structure 有权
标题翻译：用于转移包含晶体结构受控干扰的薄层的方法
公开(公告)号：US07387947B2
公开(公告)日：2008-06-17
申请号：US11305444
申请日：2005-12-16
申请人： Ian Cayrefourcq , Carlos Mazure , Konstantin Bourdelle
发明人： Ian Cayrefourcq , Carlos Mazure , Konstantin Bourdelle
IPC分类号： H01L21/20
CPC分类号： H01L21/76254
摘要： The present invention relates to a method for transferring a thin useful layer from a donor substrate having an ordered crystalline structure to a receiver substrate. The method includes creation of a weakened zone in the donor substrate to define the layer to be transferred from the donor substrate. The crystalline structure of a surface region of the donor substrate is disturbed so as to create a disturbed superficial region within the thickness of the donor substrate, and thus define a disturbance interface between the disturbed superficial region and a subjacent region of the donor substrate for which the crystalline structure remains unchanged. Next, the donor substrate is subjected to a recrystallization annealing in order to at least partial recrystallize of the disturbed region, starting from the crystalline structure of the subjacent region of the donor substrate, and to create a zone of crystalline defects in the plane of the disturbance interface. One or several species are introduced into the thickness of the donor substrate to create the weakened zone, with the species being introduced with introduction parameters that are adjusted to introduce a maximum number of species at the zone of crystalline defects.
摘要翻译：本发明涉及一种从具有有序晶体结构的施主衬底向接收衬底转移薄有用层的方法。该方法包括在施主衬底中产生弱化区以限定要从供体衬底转移的层。施主衬底的表面区域的晶体结构受到干扰，从而在施主衬底的厚度内产生干扰的表面区域，从而限定受干扰的表面区域和施主衬底的下部区域之间的扰动界面，晶体结构保持不变。接下来，对施主衬底进行再结晶退火，以便从施主衬底的下部区域的结晶结构开始至少部分地重新结晶受阻区域，并在该平面内产生晶体缺陷区域扰动界面。将一个或多个物质引入施主衬底的厚度以产生弱化区域，其中引入物质，引入参数被调整以在晶体缺陷区域引入最大数量的物质。

69. 发明申请

US20070023867A1 Film taking-off method 有权
标题翻译：电影起飞方式
公开(公告)号：US20070023867A1
公开(公告)日：2007-02-01
申请号：US11221045
申请日：2005-09-06
申请人： Cecile Aulnette , Ian Cayrefourcq , Carlos Mazure
发明人： Cecile Aulnette , Ian Cayrefourcq , Carlos Mazure
IPC分类号： H01L29/06 , H01L21/46
CPC分类号： H01L21/76254
摘要： The invention relates to a method of producing a film intended for applications in electronics, optics or optronics starting from an initial wafer, which includes a step of implanting atomic species through one of the faces of the wafer. This method includes forming a step of defined height around the periphery of the wafer, with the step having a mean thickness that is less than that of the wafer; and selectively implanting atomic species through a face of the wafer but not through the step to form an implanted zone at a defined implant depth with the film being defined between the face of the wafer and the implanted zone. The implantation of atomic species into the step can be prevented by forming a protective layer at least over the step or by masking the step. The invention also relates to a wafer obtainable by the method.
摘要翻译：本发明涉及一种从初始晶片开始制造用于电子学，光学或光电子学中的薄膜的方法，其包括通过晶片的一个表面注入原子物质的步骤。该方法包括：形成围绕晶片周边的限定高度的台阶，其平均厚度小于晶片的平均厚度; 并且通过晶片的表面选择性地注入原子物质，但不通过该步骤，以在限定的注入深度处形成植入区域，其中膜被限定在晶片的表面和植入区域之间。可以通过至少在该步骤上形成保护层或通过掩蔽该步骤来防止将原子物质注入到该步骤中。本发明还涉及可通过该方法获得的晶片。

70. 发明授权

US06964914B2 Method of manufacturing a free-standing substrate made of monocrystalline semi-conductor material 有权
标题翻译：制造由单晶半导体材料制成的独立基板的方法
公开(公告)号：US06964914B2
公开(公告)日：2005-11-15
申请号：US10349295
申请日：2003-01-22
申请人： Bruno Ghyselen , Fabrice Letertre , Carlos Mazure
发明人： Bruno Ghyselen , Fabrice Letertre , Carlos Mazure
IPC分类号： C30B29/38 , C23C16/01 , C23C16/34 , C30B25/02 , C30B29/04 , H01L21/20 , H01L21/762 , H01L21/30 , H01L21/46 , H01L21/76
CPC分类号： H01L21/76254 , Y10S438/977
摘要： A method for manufacturing a free-standing substrate made of a semiconductor material. A first assembly is provided and it includes a relatively thinner nucleation layer of a first material, a support of a second material, and a removable bonding interface defined between facing surfaces of the nucleation layer and support. A substrate of a relatively thicker layer of a third material is grown, by epitaxy on the nucleation layer, to form a second assembly with the substrate attaining a sufficient thickness to be free-standing. The third material is preferably a monocrystalline material. Also, the removable character of the bonding interface is preserved with at least the substrate being heated to an epitaxial growth temperature. The coefficients of thermal expansion of the second and third materials are selected to be different from each other by a thermal expansion differential, determined as a function of the epitaxial growth temperature or subsequent application of external mechanical stresses, such that, as the second assembly cools from the epitaxial growth temperature, stresses are induced in the removable bonding interface to facilitate detachment of the nucleation layer from the substrate.
摘要翻译：一种制造由半导体材料制成的自立式基板的方法。提供了第一组件，并且其包括第一材料的相对更薄的成核层，第二材料的支撑体和限定在成核层和支撑体的相对表面之间的可去除的结合界面。通过在成核层上外延生长相对较厚的第三材料层的衬底，以形成第二组件，其中衬底获得足够的厚度以使其独立。第三种材料优选是单晶材料。而且，至少将衬底加热到外延生长温度来保存接合界面的可去除特性。第二和第三材料的热膨胀系数被选择为相互不同的热膨胀差异，其被确定为外延生长温度的函数或随后的外部机械应力的应用，使得当第二组件冷却时从外延生长温度，在可除去的结合界面中诱发应力以促进成核层与基底的分离。

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