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61. 发明授权

US07594055B2 Systems and methods for providing distributed technology independent memory controllers 失效
标题翻译：提供分布式技术独立存储器控制器的系统和方法
公开(公告)号：US07594055B2
公开(公告)日：2009-09-22
申请号：US11420034
申请日：2006-05-24
申请人： Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
发明人： Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
IPC分类号： G06F13/14
CPC分类号： G06F13/4243 , G06F13/4247
摘要： Systems and methods for providing distributed technology independent memory controllers. Systems include a computer memory system for storing and retrieving data. The system includes a memory bus, a main memory controller, one or more memory devices characterized by memory device protocols and signaling requirements, and one or more memory hub devices. The main memory controller is in communication with the memory bus for generating, receiving, and responding to memory access requests. The hub devices are in communication with the memory bus and with the memory devices for controlling the memory devices responsively to the memory access requests received from the main memory controller and for responding to the main memory controller with state or memory data. The main memory controller and the hub devices communicate via the memory bus in messages in a message format and protocol for indicating memory read, memory write, memory system power management and control that is independent of the memory device protocols and signaling requirements.
摘要翻译：提供分布式技术独立存储器控制器的系统和方法。系统包括用于存储和检索数据的计算机存储器系统。该系统包括存储器总线，主存储器控制器，以存储器件协议和信令要求为特征的一个或多个存储器件，以及一个或多个存储器集线器设备。主存储器控制器与存储器总线通信，用于生成，接收和响应存储器访问请求。集线器设备与存储器总线和存储器设备通信，用于响应于从主存储器控制器接收的存储器访问请求来控制存储器件并且用状态或存储器数据对主存储器控制器进行响应。主存储器控制器和集线器设备通过消息中的消息格式和协议通过存储器总线进行通信，用于指示独立于存储器件协议和信令要求的存储器读取，存储器写入，存储器系统电源管理和控制。

62. 发明授权

US07581073B2 Systems and methods for providing distributed autonomous power management in a memory system 失效
标题翻译：在存储系统中提供分布式自主电源管理的系统和方法
公开(公告)号：US07581073B2
公开(公告)日：2009-08-25
申请号：US11463483
申请日：2006-08-09
申请人： Kevin C. Gower , Robert B. Tremaine
发明人： Kevin C. Gower , Robert B. Tremaine
IPC分类号： G06F12/00
CPC分类号： G06F1/3275 , G06F1/206 , G06F1/3225 , Y02D10/13 , Y02D10/14 , Y02D10/16
摘要： Systems and methods for providing distributed autonomous power management in a memory system. Embodiments include a memory system for storing and retrieving data for a processing system. The memory system includes a memory controller for receiving and responding to memory access requests, a memory bus in communication with the memory controller, a plurality of memory devices, and a control unit external to the memory controller. The memory devices are in communication with the memory controller via the memory bus, with one or more of the memory devices being associated with a group. The control unit autonomously manages power within and for the group of memory devices.
摘要翻译：在存储系统中提供分布式自主电源管理的系统和方法。实施例包括用于存储和检索用于处理系统的数据的存储器系统。存储器系统包括用于接收和响应存储器访问请求的存储器控制器，与存储器控制器通信的存储器总线，多个存储器件以及存储器控制器外部的控制单元。存储器设备经由存储器总线与存储器控制器通信，其中一个或多个存储器设备与组相关联。控制单元自主地管理存储器设备组内的功能。

63. 发明申请

US20090119443A1 METHODS FOR PROGRAM DIRECTED MEMORY ACCESS PATTERNS 失效
标题翻译：程序方向记忆访问模式的方法
公开(公告)号：US20090119443A1
公开(公告)日：2009-05-07
申请号：US12349269
申请日：2009-01-06
申请人： Robert B. Tremaine
发明人： Robert B. Tremaine
IPC分类号： G06F12/08
CPC分类号： G06F12/0607 , G06F12/10 , G06F13/28
摘要： Systems and methods for program directed memory access patterns including a memory system with a memory, a memory controller and a virtual memory management system. The memory includes a plurality of memory devices organized into one or more physical groups accessible via associated busses for transferring data and control information. The memory controller receives and responds to memory access requests that contain application access information to control access pattern and data organization within the memory. Responding to memory access request includes accessing one or more memory devices. The virtual memory management system includes: a plurality of page table entries for mapping virtual memory addresses to real addresses in the memory; a hint state responsive to application access information for indicating how real memory for associated pages is to be physically organized within the memory; and a means for conveying the hint state to the memory controller.
摘要翻译：用于程序定向存储器访问模式的系统和方法，包括具有存储器的存储器系统，存储器控制器和虚拟存储器管理系统。存储器包括被组织成一个或多个物理组的多个存储器件，可通过相关联的总线访问以传送数据和控制信息。存储器控制器接收并响应包含应用访问信息的存储器访问请求，以控制存储器内的访问模式和数据组织。响应于存储器访问请求包括访问一个或多个存储器设备。虚拟存储器管理系统包括：多个页表条目，用于将虚拟存储器地址映射到存储器中的实际地址; 响应于应用程序访问信息的指示状态，用于指示相关联的页面的实际存储器如何被物理地组织在存储器内; 以及用于将提示状态传送到存储器控制器的装置。

64. 发明授权

US07480759B2 System, method and storage medium for providing data caching and data compression in a memory subsystem 失效
标题翻译：用于在存储器子系统中提供数据缓存和数据压缩的系统，方法和存储介质
公开(公告)号：US07480759B2
公开(公告)日：2009-01-20
申请号：US11772922
申请日：2007-07-03
申请人： Kevin C. Gower , Mark W. Kellogg , Warren E. Maule , Thomas B. Smith, III , Robert B. Tremaine
发明人： Kevin C. Gower , Mark W. Kellogg , Warren E. Maule , Thomas B. Smith, III , Robert B. Tremaine
IPC分类号： G06F12/00
CPC分类号： G06F13/1684 , G06F12/0802 , G06F2212/401
摘要： A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the downstream memory bus and the upstream memory bus. The first memory module and the memory controller are in direct communication via the upstream memory bus and the downstream memory bus.
摘要翻译：包括存储器控制器，一个或多个存储器模块，上游存储器总线和下游存储器总线的级联互连系统。一个或多个存储器模块包括具有高速缓存数据的第一存储器模块。存储器模块和存储器控制器通过分组化的多传输接口经由下游存储器总线和上游存储器总线互连。第一存储器模块和存储器控制器经由上游存储器总线和下游存储器总线直接通信。

65. 发明申请

US20080301337A1 Memory Systems For Automated Computing Machinery 有权
标题翻译：自动计算机记忆系统
公开(公告)号：US20080301337A1
公开(公告)日：2008-12-04
申请号：US12185533
申请日：2008-08-04
申请人： Daniel M. Dreps , Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
发明人： Daniel M. Dreps , Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
IPC分类号： G06F13/00
CPC分类号： G06F13/1684 , G06F13/1673 , G06F13/1678 , Y02D10/14
摘要： Memory systems are disclosed that include a memory controller; an outbound link, the memory controller connected to the outbound link, the outbound link comprising a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer; and at least two memory buffer devices in a first memory layer, each memory buffer device in the first memory layer connected to the outbound link to receive memory signals from the memory controller.
摘要翻译：公开了包括存储器控制器的存储器系统; 出站链路，连接到出站链路的存储器控制器，出站链路包括将存储器信号从存储器控制器传送到第一存储器层中的存储器缓冲器设备的多个导电路径; 以及第一存储器层中的至少两个存储器缓冲器件，所述第一存储器层中的每个存储器缓冲器件连接到所述出站链路以从所述存储器控制器接收存储器信号。

66. 发明授权

US07451273B2 System, method and storage medium for providing data caching and data compression in a memory subsystem 有权
标题翻译：用于在存储器子系统中提供数据缓存和数据压缩的系统，方法和存储介质
公开(公告)号：US07451273B2
公开(公告)日：2008-11-11
申请号：US11780048
申请日：2007-07-19
申请人： Kevin C. Gower , Mark W. Kellogg , Warren E. Maule , Thomas B. Smith, III , Robert B. Tremaine
发明人： Kevin C. Gower , Mark W. Kellogg , Warren E. Maule , Thomas B. Smith, III , Robert B. Tremaine
IPC分类号： G06F12/00
CPC分类号： G06F13/1684 , G06F12/0802 , G06F2212/401
摘要： A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the downstream memory bus and the upstream memory bus. The first memory module and the memory controller are in direct communication via the upstream memory bus and the downstream memory bus.
摘要翻译：包括存储器控制器，一个或多个存储器模块，上游存储器总线和下游存储器总线的级联互连系统。一个或多个存储器模块包括具有高速缓存数据的第一存储器模块。存储器模块和存储器控制器通过分组化的多传输接口经由下游存储器总线和上游存储器总线互连。第一存储器模块和存储器控制器经由上游存储器总线和下游存储器总线直接通信。

67. 发明申请

US20080270741A1 STRUCTURE FOR PROGRAM DIRECTED MEMORY ACCESS PATTERNS 失效
标题翻译：程序方向记忆访问模式的结构
公开(公告)号：US20080270741A1
公开(公告)日：2008-10-30
申请号：US12126747
申请日：2008-05-23
申请人： Robert B. Tremaine
发明人： Robert B. Tremaine
IPC分类号： G06F12/00
CPC分类号： G06F12/0607 , G06F12/0215 , G06F12/10 , G06F13/28
摘要： Design structures for program directed memory access patterns. A design structure is embodied in a machine readable medium used in a design process, the design structure including a computer memory system for storing and retrieving data. The memory system includes a memory, a memory controller and a virtual memory management system. The memory includes a plurality of memory devices organized into one or more physical groups accessible via associated busses for transferring data and control information. The memory controller receives and responds to memory access requests that contain application access information to control access pattern and data organization within the memory. Responding to memory access request includes accessing one or more memory devices. The virtual memory management system includes: a plurality of page table entries for mapping virtual memory addresses to real addresses in the memory; a hint state responsive to application access information for indicating how real memory for associated pages is to be physically organized within the memory; and a means for conveying the hint state to the memory controller.
摘要翻译：程序定向内存访问模式的设计结构。设计结构体现在在设计过程中使用的机器可读介质中，该设计结构包括用于存储和检索数据的计算机存储器系统。存储器系统包括存储器，存储器控制器和虚拟存储器管理系统。存储器包括被组织成一个或多个物理组的多个存储器件，可通过相关联的总线访问以传送数据和控制信息。存储器控制器接收并响应包含应用访问信息的存储器访问请求，以控制存储器内的访问模式和数据组织。响应于存储器访问请求包括访问一个或多个存储器设备。虚拟存储器管理系统包括：多个页表条目，用于将虚拟存储器地址映射到存储器中的实际地址; 响应于应用程序访问信息的指示状态，用于指示相关联的页面的实际存储器如何被物理地组织在存储器内; 以及用于将提示状态传送到存储器控制器的装置。

68. 发明申请

US20080040562A1 SYSTEMS AND METHODS FOR PROVIDING DISTRIBUTED AUTONOMOUS POWER MANAGEMENT IN A MEMORY SYSTEM 失效
标题翻译：用于在存储系统中提供分布式自动电源管理的系统和方法
公开(公告)号：US20080040562A1
公开(公告)日：2008-02-14
申请号：US11463483
申请日：2006-08-09
申请人： Kevin C. Gower , Robert B. Tremaine
发明人： Kevin C. Gower , Robert B. Tremaine
IPC分类号： G06F13/00 , G06F1/32
CPC分类号： G06F1/3275 , G06F1/206 , G06F1/3225 , Y02D10/13 , Y02D10/14 , Y02D10/16
摘要： Systems and methods for providing distributed autonomous power management in a memory system. Embodiments include a memory system for storing and retrieving data for a processing system. The memory system includes a memory controller for receiving and responding to memory access requests, a memory bus in communication with the memory controller, a plurality of memory devices, and a control unit external to the memory controller. The memory devices are in communication with the memory controller via the memory bus, with one or more of the memory devices being associated with a group. The control unit autonomously manages power within and for the group of memory devices.
摘要翻译：在存储系统中提供分布式自主电源管理的系统和方法。实施例包括用于存储和检索用于处理系统的数据的存储器系统。存储器系统包括用于接收和响应存储器访问请求的存储器控制器，与存储器控制器通信的存储器总线，多个存储器件以及存储器控制器外部的控制单元。存储器设备经由存储器总线与存储器控制器通信，其中一个或多个存储器设备与组相关联。控制单元自主地管理存储器设备组内的功能。

69. 发明申请

US20070276976A1 SYSTEMS AND METHODS FOR PROVIDING DISTRIBUTED TECHNOLOGY INDEPENDENT MEMORY CONTROLLERS 失效
标题翻译：用于提供分布式技术独立存储器控制器的系统和方法
公开(公告)号：US20070276976A1
公开(公告)日：2007-11-29
申请号：US11420034
申请日：2006-05-24
申请人： Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
发明人： Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
IPC分类号： G06F13/14 , G06F12/00
CPC分类号： G06F13/4243 , G06F13/4247
摘要： Systems and methods for providing distributed technology independent memory controllers. Systems include a computer memory system for storing and retrieving data. The system includes a memory bus, a main memory controller, one or more memory devices characterized by memory device protocols and signaling requirements, and one or more memory hub devices. The main memory controller is in communication with the memory bus for generating, receiving, and responding to memory access requests. The hub devices are in communication with the memory bus and with the memory devices for controlling the memory devices responsively to the memory access requests received from the main memory controller and for responding to the main memory controller with state or memory data. The main memory controller and the hub devices communicate via the memory bus in messages in a message format and protocol for indicating memory read, memory write, memory system power management and control that is independent of the memory device protocols and signaling requirements.
摘要翻译：提供分布式技术独立存储器控制器的系统和方法。系统包括用于存储和检索数据的计算机存储器系统。该系统包括存储器总线，主存储器控制器，以存储器件协议和信令要求为特征的一个或多个存储器件，以及一个或多个存储器集线器设备。主存储器控制器与存储器总线通信，用于生成，接收和响应存储器访问请求。集线器设备与存储器总线和存储器设备通信，用于响应于从主存储器控制器接收的存储器访问请求来控制存储器件并且用状态或存储器数据对主存储器控制器进行响应。主存储器控制器和集线器设备通过消息中的消息格式和协议通过存储器总线进行通信，用于指示独立于存储器件协议和信令要求的存储器读取，存储器写入，存储器系统电源管理和控制。

70. 发明授权

US06665787B2 Very high speed page operations in indirect accessed memory systems 失效
公开(公告)号：US06665787B2
公开(公告)日：2003-12-16
申请号：US09795414
申请日：2001-02-28
申请人： Peter A. Franaszek , Charles O. Schulz , T. Basil Smith, III , Robert B. Tremaine , Michael Wazlowski
发明人： Peter A. Franaszek , Charles O. Schulz , T. Basil Smith, III , Robert B. Tremaine , Michael Wazlowski
IPC分类号： G06F1208
CPC分类号： G06F12/1009
摘要： A computing system and method employing a processor device for generating real addresses associated with memory locations of a real memory system for reading and writing of data thereto, the system comprising: a plurality of memory blocks in the real memory system for storing data, a physical memory storage for storing the pages of data comprising one or more real memory blocks, each real memory block partitioned into one or more sectors, each comprising contiguous bytes of physical memory; a translation table structure in the physical memory storage having entries for associating a real address with sectors of the physical memory, each translation table entry including one or more pointers for pointing to a corresponding sector in its associated real memory block, the table accessed for storing data in one or more allocated sectors for memory read and write operations initiated by the processor; and, a control device for directly manipulating entries in the translation table structure for performing page operations without actually accessing physical memory data contents. In this system, the actual data of the pages involved in the operation are never accessed by the processor and therefore is never required in the memory cache hierarchy, thus eliminating the cache damage normally associated with these block operations. Further the manipulation of the translation table will involve reading and writing a few bytes to perform the operation as opposed to reading and writing the hundreds or thousands of bytes in the pages being manipulated.

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