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61. 发明授权

US07532065B2 Analog amplifier having DC offset cancellation circuit and method of offset cancellation for analog amplifiers 有权
标题翻译：具有DC偏移消除电路的模拟放大器和模拟放大器的偏移消除方法
公开(公告)号：US07532065B2
公开(公告)日：2009-05-12
申请号：US11420177
申请日：2006-05-24
申请人： Jinghong Chen , Gregory W. Sheets , Joseph Anidjar , Robert J. Kapuschinsky , Lane A. Smith
发明人： Jinghong Chen , Gregory W. Sheets , Joseph Anidjar , Robert J. Kapuschinsky , Lane A. Smith
IPC分类号： H03F1/02
CPC分类号： H03F3/45973 , H03F3/45977 , H03F2203/45101 , H03F2203/45434 , H03F2203/45564 , H03F2203/45588 , H03F2203/45622
摘要： An amplifier having DC offset compensation includes at least one input node and a pair of differential output nodes, a biasing circuit coupled to the input node; and a plurality of current sources. Selected ones of said current sources are coupled to the input node to adjust a DC voltage at the input node to provide DC offset compensation for the amplifier
摘要翻译：具有DC偏移补偿的放大器包括至少一个输入节点和一对差分输出节点，偏置电路耦合到输入节点; 和多个电流源。所选择的所述电流源耦合到输入节点以调整输入节点处的DC电压，以为放大器提供DC偏移补偿

62. 发明授权

US07792234B2 Method and apparatus for integral state initialization and quality of lock monitoring in a clock and data recovery system 有权
标题翻译：用于整体状态初始化的方法和装置以及时钟和数据恢复系统中锁定监视的质量
公开(公告)号：US07792234B2
公开(公告)日：2010-09-07
申请号：US11414521
申请日：2006-04-28
申请人： Pervez M. Aziz , Gregory W. Sheets , Vladimir Sindalovsky
发明人： Pervez M. Aziz , Gregory W. Sheets , Vladimir Sindalovsky
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： H03L7/0807 , H03L7/087 , H03L7/093 , H04L7/0004 , H04L7/0331
摘要： Methods and apparatus are provided for improving the performance of second order CDR systems. The integral state of the CDR system is initialized to a value that is based on an expected frequency profile that may be known a priori for certain applications. One or more quality of lock (QOL) metrics are also monitored that are derived from the integral register state value. A quality of a locking between a received signal and a local clock generated by a Clock and Data Recovery (CDR) system is evaluated by monitoring a state value of an integral register in a digital loop filter of the CDR system; evaluating one or more predefined criteria based on the integral register state value; and identifying a poor lock condition if the one or more predefined criteria are not satisfied.
摘要翻译：提供了用于提高二级CDR系统的性能的方法和装置。 CDR系统的整体状态被初始化为基于对于某些应用可以是先验已知的预期频率分布的值。还监视从积分寄存器状态值导出的一个或多个锁定质量（QOL）度量。通过监视CDR系统的数字环路滤波器中的积分寄存器的状态值来评估由时钟和数据恢复（CDR）系统产生的接收信号和本地时钟之间的锁定的质量; 基于积分寄存器状态值来评估一个或多个预定标准; 并且如果不满足一个或多个预定标准，则识别差的锁定条件。

63. 发明授权

US08416907B2 Method and apparatus for integral state initialization and quality of lock monitoring in a clock and data recovery system 有权
标题翻译：用于整体状态初始化的方法和装置以及时钟和数据恢复系统中锁定监视的质量
公开(公告)号：US08416907B2
公开(公告)日：2013-04-09
申请号：US12846390
申请日：2010-07-29
申请人： Pervez M. Aziz , Gregory W. Sheets , Vladimir Sindalovsky
发明人： Pervez M. Aziz , Gregory W. Sheets , Vladimir Sindalovsky
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： H03L7/0807 , H03L7/087 , H03L7/093 , H04L7/0004 , H04L7/0331
摘要： Methods and apparatus are provided for improving the performance of second order CDR systems. The integral state of the CDR system is initialized to a value that is based on an expected frequency profile that may be known a priori for certain applications. One or more quality of lock (QOL) metrics are also monitored that are derived from the integral register state value. A quality of a locking between a received signal and a local clock generated by a Clock and Data Recovery (CDR) system is evaluated by monitoring a state value of an integral register in a digital loop filter of the CDR system; evaluating one or more predefined criteria based on the integral register state value; and identifying a poor lock condition if the one or more predefined criteria are not satisfied.
摘要翻译：提供了用于提高二级CDR系统的性能的方法和装置。 CDR系统的整体状态被初始化为基于对于某些应用可以是先验已知的预期频率分布的值。还监视从积分寄存器状态值导出的一个或多个锁定质量（QOL）度量。通过监视CDR系统的数字环路滤波器中的积分寄存器的状态值来评估由时钟和数据恢复（CDR）系统产生的接收信号和本地时钟之间的锁定的质量; 基于积分寄存器状态值来评估一个或多个预定标准; 并且如果不满足一个或多个预定标准，则识别差的锁定条件。

64. 发明申请

US20100026378A1 METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY 有权
标题翻译：设计采用电压整流的集成电路和集成电路设计方法
公开(公告)号：US20100026378A1
公开(公告)日：2010-02-04
申请号：US12364918
申请日：2009-02-03
申请人： James C. Parker , Vishwas M. Rao , Clayton E. Schneider, JR. , Gregory W. Sheets , Prasad Subbarao
发明人： James C. Parker , Vishwas M. Rao , Clayton E. Schneider, JR. , Gregory W. Sheets , Prasad Subbarao
IPC分类号： G05F1/10 , G06F17/50
CPC分类号： G06F17/505 , G01R31/31725 , G06F1/04 , G06F1/26 , G06F1/3203 , G06F17/5081 , H03K19/215
摘要： Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to implement a layout from the functional IC design that meets the performance objectives and (6) performing a timing signoff of the layout at the optimization target voltage.
摘要翻译：设计集成电路（IC）的方法的各种实施例。一种这样的方法的一个实施例包括：（1）产生IC的功能设计，（2）确定IC的性能目标，（3）确定IC的优化目标电压，（4）确定IC是否需要电压缩放以实现优化目标电压下的性能目标，如果是，是采用静态电压缩放还是采用自适应电压调整，（5）使用优化目标电压来实现功能IC设计中符合性能目标和（6）在优化目标电压下执行布局的定时签出。

65. 发明授权

US08806408B2 Methods for designing integrated circuits employing voltage scaling and integrated circuits designed thereby 有权
标题翻译：使用电压调节的集成电路设计方法和由此设计的集成电路
公开(公告)号：US08806408B2
公开(公告)日：2014-08-12
申请号：US12364918
申请日：2009-02-03
申请人： James C. Parker , Vishwas M. Rao , Clayton E. Schneider, Jr. , Gregory W. Sheets , Prasad Subbarao
发明人： James C. Parker , Vishwas M. Rao , Clayton E. Schneider, Jr. , Gregory W. Sheets , Prasad Subbarao
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G01R31/31725 , G06F1/04 , G06F1/26 , G06F1/3203 , G06F17/5081 , H03K19/215
摘要： Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to implement a layout from the functional IC design that meets the performance objectives and (6) performing a timing signoff of the layout at the optimization target voltage.
摘要翻译：设计集成电路（IC）的方法的各种实施例。一种这样的方法的一个实施例包括：（1）产生IC的功能设计，（2）确定IC的性能目标，（3）确定IC的优化目标电压，（4）确定IC是否需要电压缩放以实现优化目标电压下的性能目标，如果是，是采用静态电压缩放还是采用自适应电压调整，（5）使用优化目标电压来实现功能IC设计中符合性能目标和（6）在优化目标电压下执行布局的定时签出。

66. 发明授权

US07916822B2 Method and apparatus for reducing latency in a clock and data recovery (CDR) circuit 有权
标题翻译：用于减少时钟和数据恢复（CDR）电路中的延迟的方法和装置
公开(公告)号：US07916822B2
公开(公告)日：2011-03-29
申请号：US11367214
申请日：2006-03-03
申请人： Pervez M. Aziz , Gregory W. Sheets
发明人： Pervez M. Aziz , Gregory W. Sheets
IPC分类号： H03D3/24
CPC分类号： H03D13/003 , H03L7/081 , H03L7/0812 , H03L7/087 , H03L7/093 , H04L7/033
摘要： Disclosed is a system and method for a clock and data recovery (CDR) circuit. A phase selection circuit (PSC) generates a signal comprising frequency and phase. A voltage controlled oscillator (VCO) connected to the PSC generates a clock signal. The clock signal controls the frequency of the signal. The CDR circuit also includes a phase adjustment signal generator connected to the PSC for generating a phase adjustment signal. The phase adjustment signal controls the phase of the signal.
摘要翻译：公开了一种用于时钟和数据恢复（CDR）电路的系统和方法。相位选择电路（PSC）产生包括频率和相位的信号。连接到PSC的压控振荡器（VCO）产生时钟信号。时钟信号控制信号的频率。 CDR电路还包括连接到PSC的相位调整信号发生器，用于产生相位调整信号。相位调整信号控制信号的相位。

67. 发明申请

US20100290513A1 METHOD AND APPARATUS FOR INTEGRAL STATE INITIALIZATION AND QUALITY OF LOCK MONITORING IN A CLOCK AND DATA RECOVERY SYSTEM 有权
标题翻译：综合状态初始化和时钟和数据恢复系统中的监控质量的方法与装置
公开(公告)号：US20100290513A1
公开(公告)日：2010-11-18
申请号：US12846390
申请日：2010-07-29
申请人： Pervez M. Aziz , Gregory W. Sheets , Vladimir Sindalovsky
发明人： Pervez M. Aziz , Gregory W. Sheets , Vladimir Sindalovsky
IPC分类号： H04B17/00
CPC分类号： H03L7/0807 , H03L7/087 , H03L7/093 , H04L7/0004 , H04L7/0331
摘要： Methods and apparatus are provided for improving the performance of second order CDR systems. The integral state of the CDR system is initialized to a value that is based on an expected frequency profile that may be known a priori for certain applications. One or more quality of lock (QOL) metrics are also monitored that are derived from the integral register state value. A quality of a locking between a received signal and a local clock generated by a Clock and Data Recovery (CDR) system is evaluated by monitoring a state value of an integral register in a digital loop filter of the CDR system; evaluating one or more predefined criteria based on the integral register state value; and identifying a poor lock condition if the one or more predefined criteria are not satisfied.
摘要翻译：提供了用于提高二级CDR系统的性能的方法和装置。 CDR系统的整体状态被初始化为基于对于某些应用可以是先验已知的预期频率分布的值。还监视从积分寄存器状态值导出的一个或多个锁定质量（QOL）度量。通过监视CDR系统的数字环路滤波器中的积分寄存器的状态值来评估由时钟和数据恢复（CDR）系统产生的接收信号和本地时钟之间的锁定的质量; 基于积分寄存器状态值来评估一个或多个预定标准; 并且如果不满足一个或多个预定标准，则识别差的锁定条件。

68. 发明授权

US07400181B2 Method and apparatus for delay line control using receive data 有权
标题翻译：使用接收数据进行延迟线控制的方法和装置
公开(公告)号：US07400181B2
公开(公告)日：2008-07-15
申请号：US11241758
申请日：2005-09-30
申请人： Peter C. Metz , Gregory W. Sheets
发明人： Peter C. Metz , Gregory W. Sheets
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03L7/089 , H04L7/0037 , H04L7/0331
摘要： Methods and apparatus are provided for delay line control using receive data. A delay in a Delay-Locked-Loop circuit is controlled by obtaining a plurality of samples of one or more received signals for each unit interval; determining a data eye width in the one or more received signals; and adjusting a delay of at least one clock signal based on the data eye width. For example, the measured data eye width can be compared to a predefined value, such as a desired or ideal value. Generally, the delay is not adjusted in accordance with the present invention until the Delay-Locked-Loop circuit has reached a locked condition based on one or more predefined criteria.
摘要翻译：提供了使用接收数据进行延迟线控制的方法和装置。通过为每个单位间隔获得一个或多个接收信号的多个样本来控制延迟锁定环路电路中的延迟; 确定所述一个或多个接收信号中的数据眼宽; 以及基于数据眼睛宽度调整至少一个时钟信号的延迟。例如，可以将测量的数据眼睛宽度与诸如期望值或理想值的预定义值进行比较。通常，根据本发明，在延迟锁定环电路已经基于一个或多个预定准则达到锁定状态之前，延迟不被调整。

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