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1. 发明申请

US20090212856A1 ANALOG AMPLIFIER HAVING DC OFFSET CANCELLATION CIRCUIT AND METHOD OF OFFSET CANCELLATION FOR ANALOG AMPLIFIERS 有权
标题翻译：具有直流偏移消除电路的模拟放大器和模拟放大器偏移消除方法
公开(公告)号：US20090212856A1
公开(公告)日：2009-08-27
申请号：US12437860
申请日：2009-05-08
申请人： Jinghong Chen , Gregory W. Sheets , Joseph Anidjar , Robert J. Kapuschinsky , Lane A. Smith
发明人： Jinghong Chen , Gregory W. Sheets , Joseph Anidjar , Robert J. Kapuschinsky , Lane A. Smith
IPC分类号： H03F1/02
CPC分类号： H03F3/45973 , H03F3/45977 , H03F2203/45101 , H03F2203/45434 , H03F2203/45564 , H03F2203/45588 , H03F2203/45622
摘要： An amplifier having DC offset compensation includes at least one input node and a pair of differential output nodes, a biasing circuit coupled to the input node; and a plurality of current sources. Selected ones of said current sources are coupled to the input node to adjust a DC voltage at the input node to provide DC offset compensation for the amplifier
摘要翻译：具有DC偏移补偿的放大器包括至少一个输入节点和一对差分输出节点，偏置电路耦合到输入节点; 和多个电流源。所选择的所述电流源耦合到输入节点以调整输入节点处的DC电压，以为放大器提供DC偏移补偿

2. 发明授权

US07755421B2 Analog amplifier having DC offset cancellation circuit and method of offset cancellation for analog amplifiers 有权
标题翻译：具有DC偏移消除电路的模拟放大器和模拟放大器的偏移消除方法
公开(公告)号：US07755421B2
公开(公告)日：2010-07-13
申请号：US12437860
申请日：2009-05-08
申请人： Jinghong Chen , Gregory W. Sheets , Joseph Anidjar , Robert J. Kapuschinsky , Lane A. Smith
发明人： Jinghong Chen , Gregory W. Sheets , Joseph Anidjar , Robert J. Kapuschinsky , Lane A. Smith
IPC分类号： H03F1/02
CPC分类号： H03F3/45973 , H03F3/45977 , H03F2203/45101 , H03F2203/45434 , H03F2203/45564 , H03F2203/45588 , H03F2203/45622
摘要： An amplifier having DC offset compensation includes at least one input node and a pair of differential output nodes, a biasing circuit coupled to the input node; and a plurality of current sources. Selected ones of said current sources are coupled to the input node to adjust a DC voltage at the input node to provide DC offset compensation for the amplifier
摘要翻译：具有DC偏移补偿的放大器包括至少一个输入节点和一对差分输出节点，耦合到输入节点的偏置电路; 和多个电流源。所选择的所述电流源耦合到输入节点以调整输入节点处的DC电压，以为放大器提供DC偏移补偿

3. 发明授权

US07532065B2 Analog amplifier having DC offset cancellation circuit and method of offset cancellation for analog amplifiers 有权
标题翻译：具有DC偏移消除电路的模拟放大器和模拟放大器的偏移消除方法
公开(公告)号：US07532065B2
公开(公告)日：2009-05-12
申请号：US11420177
申请日：2006-05-24
申请人： Jinghong Chen , Gregory W. Sheets , Joseph Anidjar , Robert J. Kapuschinsky , Lane A. Smith
发明人： Jinghong Chen , Gregory W. Sheets , Joseph Anidjar , Robert J. Kapuschinsky , Lane A. Smith
IPC分类号： H03F1/02
CPC分类号： H03F3/45973 , H03F3/45977 , H03F2203/45101 , H03F2203/45434 , H03F2203/45564 , H03F2203/45588 , H03F2203/45622
摘要： An amplifier having DC offset compensation includes at least one input node and a pair of differential output nodes, a biasing circuit coupled to the input node; and a plurality of current sources. Selected ones of said current sources are coupled to the input node to adjust a DC voltage at the input node to provide DC offset compensation for the amplifier
摘要翻译：具有DC偏移补偿的放大器包括至少一个输入节点和一对差分输出节点，偏置电路耦合到输入节点; 和多个电流源。所选择的所述电流源耦合到输入节点以调整输入节点处的DC电压，以为放大器提供DC偏移补偿

4. 发明申请

US20100244937A1 Compensation Techniques for Reducing Power Consumption in Digital Circuitry 有权
标题翻译：降低数字电路功耗的补偿技术
公开(公告)号：US20100244937A1
公开(公告)日：2010-09-30
申请号：US12160373
申请日：2007-10-31
申请人： Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
发明人： Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： G05F1/10
CPC分类号： H03K19/00369
摘要： A compensation circuit for reducing power consumption in at least one digital circuit includes a first sample circuit connected to a first supply voltage, a second sample circuit connected to a second supply voltage, and a controller connected to the first and second sample circuits. The first and second sample circuits are substantially functionally equivalent to one another but optimized for different regions of operation within a specified range of PVT conditions. The controller is operative to receive respective output signals from the first and second sample circuits, to monitor a functionality of the second sample circuit relative to the first sample circuit, and to adjust a level of the second supply voltage to ensure correct operation of the second sample circuit throughout the specified range of PVT conditions. The digital circuit is operative from the second supply voltage.
摘要翻译：用于降低至少一个数字电路中的功耗的补偿电路包括连接到第一电源电压的第一采样电路，连接到第二电源电压的第二采样电路和连接到第一和第二采样电路的控制器。第一和第二采样电路基本上在功能上彼此相等，但是在PVT条件的指定范围内针对不同操作区域进行了优化。控制器可操作以从第一和第二采样电路接收相应的输出信号，以监测第二采样电路相对于第一采样电路的功能，并调整第二电源电压的电平，以确保第二采样电路的正常工作采样电路在指定的PVT条件范围内。数字电路从第二电源电压工作。

5. 发明授权

US07965133B2 Compensation techniques for reducing power consumption in digital circuitry 有权
标题翻译：用于降低数字电路功耗的补偿技术
公开(公告)号：US07965133B2
公开(公告)日：2011-06-21
申请号：US12160373
申请日：2007-10-31
申请人： Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
发明人： Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： G05F1/10
CPC分类号： H03K19/00369
摘要： A compensation circuit for reducing power consumption in at least one digital circuit includes a first sample circuit connected to a first supply voltage, a second sample circuit connected to a second supply voltage, and a controller connected to the first and second sample circuits. The first and second sample circuits are substantially functionally equivalent to one another but optimized for different regions of operation within a specified range of PVT conditions. The controller is operative to receive respective output signals from the first and second sample circuits, to monitor a functionality of the second sample circuit relative to the first sample circuit, and to adjust a level of the second supply voltage to ensure correct operation of the second sample circuit throughout the specified range of PVT conditions. The digital circuit is operative from the second supply voltage.
摘要翻译：用于降低至少一个数字电路中的功耗的补偿电路包括连接到第一电源电压的第一采样电路，连接到第二电源电压的第二采样电路和连接到第一和第二采样电路的控制器。第一和第二采样电路基本上在功能上彼此相等，但是在PVT条件的指定范围内针对不同操作区域进行了优化。控制器可操作以从第一和第二采样电路接收相应的输出信号，以监测第二采样电路相对于第一采样电路的功能，并调整第二电源电压的电平，以确保第二采样电路的正常工作采样电路在指定的PVT条件范围内。数字电路从第二电源电压工作。

6. 发明授权

US07923868B2 Method and apparatus for adjusting a power supply of an integrated circuit 有权
标题翻译：用于调整集成电路的电源的方法和装置
公开(公告)号：US07923868B2
公开(公告)日：2011-04-12
申请号：US12012761
申请日：2008-02-05
申请人： Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
发明人： Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： H02J3/00
CPC分类号： H03K19/0027 , G06F1/3203 , H03K19/00384 , Y10T307/74
摘要： Disclosed is a circuit configured to apply a supply voltage to a switching element (e.g., a transistor). The circuit includes a latch and a processor. The latch is configured to sample a voltage of an output signal of the switching element, and the processor is configured to generate a power adjustment signal to adjust the supply voltage based on the voltage sampled by the latch.
摘要翻译：公开了一种被配置为向开关元件（例如，晶体管）施加电源电压的电路。该电路包括一个锁存器和一个处理器。锁存器被配置为对开关元件的输出信号的电压进行采样，并且处理器被配置为产生功率调整信号，以基于由锁存器采样的电压来调节电源电压。

7. 发明申请

US20080191789A1 Method and apparatus for adjusting a power supply of an integrated circuit 有权
标题翻译：用于调整集成电路的电源的方法和装置
公开(公告)号：US20080191789A1
公开(公告)日：2008-08-14
申请号：US12012761
申请日：2008-02-05
申请人： Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
发明人： Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： G05F1/10
CPC分类号： H03K19/0027 , G06F1/3203 , H03K19/00384 , Y10T307/74
摘要： Disclosed is a circuit configured to apply a supply voltage to a switching element (e.g., a transistor). The circuit includes a latch and a processor. The latch is configured to sample a voltage of an output signal of the switching element, and the processor is configured to generate a power adjustment signal to adjust the supply voltage based on the voltage sampled by the latch.
摘要翻译：公开了一种被配置为向开关元件（例如，晶体管）施加电源电压的电路。该电路包括一个锁存器和一个处理器。锁存器被配置为对开关元件的输出信号的电压进行采样，并且处理器被配置为产生功率调整信号，以基于由锁存器采样的电压来调节电源电压。

8. 发明授权

US07560957B2 High-speed CML circuit design 有权
标题翻译：高速CML电路设计
公开(公告)号：US07560957B2
公开(公告)日：2009-07-14
申请号：US11421675
申请日：2006-06-01
申请人： Jinghong Chen , Gregory W. Sheets , Lane A. Smith
发明人： Jinghong Chen , Gregory W. Sheets , Lane A. Smith
IPC分类号： H03K17/16 , H03K19/003 , H03K19/0175 , H03K19/20 , H03K19/094
CPC分类号： H03K19/09432 , H03K19/01707
摘要： A current mode logic digital circuit is provided comprising a logic circuit component having at least one data input node and at least one output node. A load is coupled between a power supply node and the output node. The load comprises a folded active inductor coupled to the output node.
摘要翻译：提供了一种电流模式逻辑数字电路，包括具有至少一个数据输入节点和至少一个输出节点的逻辑电路组件。负载耦合在电源节点和输出节点之间。负载包括耦合到输出节点的折叠有源电感器。

9. 发明授权

US08219344B2 Method and apparatus for digital VCDL startup 失效
标题翻译：数字VCDL启动的方法和装置
公开(公告)号：US08219344B2
公开(公告)日：2012-07-10
申请号：US12789544
申请日：2010-05-28
申请人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
发明人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
IPC分类号： H03L7/06
CPC分类号： H03L7/0812
摘要： Methods and apparatus are provided for improved startup of a voltage controlled delay loop that has an injection clock and a return clock. A control signal is determined for a plurality of delay elements in a voltage controlled delay loop by obtaining a histogram count of a number of occurrences of at least one predefined logic value for a plurality of delay settings of the voltage controlled delay loop; determining a histogram count that approximately corresponds to an alignment of at least one edge in the injection and return clocks; and determining the control signal based on the determined histogram count that approximately corresponds to the alignment. The voltage controlled delay loop can be started using the determined control signal. The histogram count can be obtained for a plurality of PVT combinations and the control signal can then be determined for each PVT combination.
摘要翻译：提供了用于改进启动具有注入时钟和返回时钟的电压控制延迟回路的方法和装置。通过获得针对电压控制的延迟环路的多个延迟设置的至少一个预定逻辑值的出现次数的直方图计数，为电压控制的延迟环路中的多个延迟元件确定控制信号; 确定近似对应于所述注入和返回时钟中的至少一个边缘的对准的直方图计数; 以及基于大致对应于所述对准的所确定的直方图计数来确定所述控制信号。可以使用所确定的控制信号来开始压控延迟环路。可以为多个PVT组合获得直方图计数，然后可以为每个PVT组合确定控制信号。

10. 发明授权

US07706487B2 Method for training a transceiver for high speed communications 有权
标题翻译：用于训练用于高速通信的收发器的方法
公开(公告)号：US07706487B2
公开(公告)日：2010-04-27
申请号：US10964056
申请日：2004-10-12
申请人： Pervez Mirza Aziz , Donald Raymond Laturell , Mohammad Shafiul Mobin , Gregory W. Sheets , Lane A. Smith
发明人： Pervez Mirza Aziz , Donald Raymond Laturell , Mohammad Shafiul Mobin , Gregory W. Sheets , Lane A. Smith
IPC分类号： H04B1/10
CPC分类号： G01R31/31715 , H04B3/04 , H04L25/03038 , H04L2025/03356 , H04L2025/03477 , H04L2025/03617
摘要： In training a SERDES, a Common Electrical Interface (CEI) training frame, having certain bits of information embedded therein, is transmitted over a path which comprises transmitter, channel, and receiver components. The present invention analyzes the resulting received signal and determines the effective aggregate channel impulse response of these three components. The invention then determines an estimate of the inverse of this aggregate channel and uses this determination to reduce distortions that have been introduced into a signal that has been transmitted over the path.
摘要翻译：在训练SERDES时，通过包含发射机，信道和接收机组件的路径发送具有嵌入其中的某些信息位的公共电接口（CEI）训练帧。本发明分析所得到的接收信号并确定这三个分量的有效总信道脉冲响应。然后，本发明确定该聚合信道的逆的估计，并且使用该确定来减少已经被引入到已经通过该路径传输的信号中的失真。

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