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1. 发明申请

US20100026378A1 METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY 有权
标题翻译：设计采用电压整流的集成电路和集成电路设计方法
公开(公告)号：US20100026378A1
公开(公告)日：2010-02-04
申请号：US12364918
申请日：2009-02-03
申请人： James C. Parker , Vishwas M. Rao , Clayton E. Schneider, JR. , Gregory W. Sheets , Prasad Subbarao
发明人： James C. Parker , Vishwas M. Rao , Clayton E. Schneider, JR. , Gregory W. Sheets , Prasad Subbarao
IPC分类号： G05F1/10 , G06F17/50
CPC分类号： G06F17/505 , G01R31/31725 , G06F1/04 , G06F1/26 , G06F1/3203 , G06F17/5081 , H03K19/215
摘要： Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to implement a layout from the functional IC design that meets the performance objectives and (6) performing a timing signoff of the layout at the optimization target voltage.
摘要翻译：设计集成电路（IC）的方法的各种实施例。一种这样的方法的一个实施例包括：（1）产生IC的功能设计，（2）确定IC的性能目标，（3）确定IC的优化目标电压，（4）确定IC是否需要电压缩放以实现优化目标电压下的性能目标，如果是，是采用静态电压缩放还是采用自适应电压调整，（5）使用优化目标电压来实现功能IC设计中符合性能目标和（6）在优化目标电压下执行布局的定时签出。

2. 发明授权

US08806408B2 Methods for designing integrated circuits employing voltage scaling and integrated circuits designed thereby 有权
标题翻译：使用电压调节的集成电路设计方法和由此设计的集成电路
公开(公告)号：US08806408B2
公开(公告)日：2014-08-12
申请号：US12364918
申请日：2009-02-03
申请人： James C. Parker , Vishwas M. Rao , Clayton E. Schneider, Jr. , Gregory W. Sheets , Prasad Subbarao
发明人： James C. Parker , Vishwas M. Rao , Clayton E. Schneider, Jr. , Gregory W. Sheets , Prasad Subbarao
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G01R31/31725 , G06F1/04 , G06F1/26 , G06F1/3203 , G06F17/5081 , H03K19/215
摘要： Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to implement a layout from the functional IC design that meets the performance objectives and (6) performing a timing signoff of the layout at the optimization target voltage.
摘要翻译：设计集成电路（IC）的方法的各种实施例。一种这样的方法的一个实施例包括：（1）产生IC的功能设计，（2）确定IC的性能目标，（3）确定IC的优化目标电压，（4）确定IC是否需要电压缩放以实现优化目标电压下的性能目标，如果是，是采用静态电压缩放还是采用自适应电压调整，（5）使用优化目标电压来实现功能IC设计中符合性能目标和（6）在优化目标电压下执行布局的定时签出。

3. 发明授权

US07712066B2 Area-efficient power switching cell 失效
标题翻译：区域效率的电力开关电池
公开(公告)号：US07712066B2
公开(公告)日：2010-05-04
申请号：US11322103
申请日：2005-12-29
申请人： Martin J. Gasper, Jr. , James C. Parker , Clayton E. Schneider, Jr.
发明人： Martin J. Gasper, Jr. , James C. Parker , Clayton E. Schneider, Jr.
IPC分类号： G06F9/45 , G06F17/50 , G06F7/38 , H03K19/173
CPC分类号： H03K17/687
摘要： A power switching circuit is provided for use in an integrated circuit including at least a first voltage rail and a second voltage rail. The power switching circuit includes at least one MOS device having a first source/drain adapted for connection to the first voltage rail, a second source/drain adapted for connection to the second voltage rail, and a gate adapted for receiving a control signal. The MOS device selectively connects the first voltage rail to the second voltage rail in response to the control signal. The first and second voltage rails form a grid overlying the power switching circuit, the first and second voltage rails being formed in different planes relative to one another. The connection between the power switching circuit and the first voltage rail is made at an interface between the first and voltage rails.
摘要翻译：电源开关电路用于至少包括第一电压轨和第二电压轨的集成电路中。功率开关电路包括至少一个MOS器件，其具有适于连接到第一电压轨的第一源极/漏极，适于连接到第二电压轨的第二源/漏极和适于接收控制信号的栅极。 MOS器件响应于控制信号选择性地将第一电压轨连接到第二电压轨。第一和第二电压轨形成覆盖功率开关电路的电网，第一和第二电压轨相对于彼此形成在不同的平面中。电源开关电路和第一电压轨之间的连接在第一和电压轨之间的接口处形成。

4. 发明申请

US20130055175A1 SYSTEMATIC, NORMALIZED METRIC FOR ANALYZING AND COMPARING OPTIMIZATION TECHNIQUES FOR INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY 审中-公开
标题翻译：用于分析和比较采用电压调节的集成电路和集成电路的优化方法的系统，正则化公制
公开(公告)号：US20130055175A1
公开(公告)日：2013-02-28
申请号：US13599549
申请日：2012-08-30
申请人： Joseph J. Jamann , James C. Parker , Vishwas M. Rao
发明人： Joseph J. Jamann , James C. Parker , Vishwas M. Rao
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G01R31/31725 , G06F1/04 , G06F1/26 , G06F1/3203 , G06F17/5081 , H03K19/215
摘要： Various embodiments of methods of designing an integrated circuit (IC) are provided herein. One embodiment of one such method includes: (1) generating a functional IC design, (2) determining a target clock rate for the functional IC design, (3) generating a netlist from the functional IC design that meets the target clock rate, (4) determining a unitless performance/power quantifier from the netlist, (5) attempting to increase the unitless performance/power quantifier by changing at least one of a speed, an area and a power consumption in at least some noncritical paths in the netlist, wherein the attempting is performed by a processor and (6) generating a layout of the IC from the netlist.
摘要翻译：本文提供了设计集成电路（IC）的方法的各种实施例。一种这样的方法的一个实施例包括：（1）产生功能IC设计，（2）确定功能IC设计的目标时钟速率，（3）从满足目标时钟速率的功能IC设计生成网表（ 4）从网表确定无单位性能/功率量化器，（5）尝试通过改变网表中的至少一些非关键路径中的速度，面积和功率消耗中的至少一个来增加无单位性能/功率量化器，其中所述尝试由处理器执行，并且（6）从所述网表生成所述IC的布局。

5. 发明申请

US20110022996A1 METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING CONTEXT-SENSITIVE AND PROGRESSIVE RULES AND AN APPARATUS EMPLOYING ONE OF THE METHODS 有权
标题翻译：用于设计采用语境敏感和进步规则的集成电路的方法和使用方法之一的设备
公开(公告)号：US20110022996A1
公开(公告)日：2011-01-27
申请号：US12510122
申请日：2009-07-27
申请人： James C. Parker , Vishwas M. Rao , Lalita M. Satapathy , Todd M. Tope
发明人： James C. Parker , Vishwas M. Rao , Lalita M. Satapathy , Todd M. Tope
IPC分类号： G06F17/50
CPC分类号： G06F17/50
摘要： Methods of designing an IC and an apparatus are disclosed. In one embodiment, a method includes: (1) creating a functional circuit for a functional block of an IC design, (2) verifying said functional circuit satisfies a rule-set for said IC design, wherein said rule-set is context-based with respect to said design flow, (3) synthesizing a logical circuit based on the functional circuit; (4) verifying the logical circuit satisfies the rule set; (5) implementing a physical layout of the logical circuit; and (6) verifying the physical layout satisfies the rule set, wherein each step of the method is carried out by at least one EDA tool.
摘要翻译：公开了设计IC和装置的方法。在一个实施例中，一种方法包括：（1）创建用于IC设计的功能块的功能电路，（2）验证所述功能电路满足所述IC设计的规则集，其中所述规则集是基于上下文的相对于所述设计流程，（3）基于功能电路合成逻辑电路; （4）验证逻辑电路满足规则集; （5）实现逻辑电路的物理布局; 和（6）验证物理布局满足规则集，其中该方法的每个步骤由至少一个EDA工具执行。

6. 发明授权

US08281266B2 Systematic, normalized metric for analyzing and comparing optimization techniques for integrated circuits employing voltage scaling and integrated circuits designed thereby 失效
标题翻译：用于分析和比较采用电压缩放的集成电路和由此设计的集成电路的优化技术的系统的归一化度量
公开(公告)号：US08281266B2
公开(公告)日：2012-10-02
申请号：US12365010
申请日：2009-02-03
申请人： Joseph J. Jamann , James C. Parker , Vishwas M. Rao
发明人： Joseph J. Jamann , James C. Parker , Vishwas M. Rao
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G01R31/31725 , G06F1/04 , G06F1/26 , G06F1/3203 , G06F17/5081 , H03K19/215
摘要： Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to synthesize a layout from the functional IC design that meets the performance objectives by employing a unitless performance/power quantifier as a metric to gauge a degree of optimization thereof and (6) performing a timing signoff of the layout at the optimization target voltage.
摘要翻译：设计集成电路（IC）的方法的各种实施例。一种这样的方法的一个实施例包括：（1）产生IC的功能设计，（2）确定IC的性能目标，（3）确定IC的优化目标电压，（4）确定IC是否需要电压缩放以实现优化目标电压下的性能目标，如果是，则采用静态电压缩放或自适应电压缩放，（5）使用优化目标电压从功能IC设计中合成布局，满足通过采用无单位性能/功率量化器作为衡量其优化程度的度量的性能目标，以及（6）在优化目标电压下执行布局的定时签出。

7. 发明授权

US08689161B2 Methods for designing integrated circuits employing pre-determined timing-realizable clock-insertion delays and integrated circuit design tools 有权
标题翻译：使用预定时序可实现的时钟插入延迟和集成电路设计工具设计集成电路的方法
公开(公告)号：US08689161B2
公开(公告)日：2014-04-01
申请号：US12831038
申请日：2010-07-06
申请人： Vishwas M. Rao , James C. Parker
发明人： Vishwas M. Rao , James C. Parker
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/62
摘要： A method of designing an integrated circuit, an EDA tool, an apparatus and a computer-readable medium are disclosed herein. In one embodiment, the method includes: (1) generating a set of constraint equations representing clock-insertion delay values for the integrated circuit as variables, (2) determining bounds on each of the clock-insertion delay values based on the constraint equations and (3) generating a set of closing commands based on the bounds for driving a design of the integrated circuit to closure, wherein each step of the method is carried out by at least one EDA tool.
摘要翻译：本文公开了一种设计集成电路，EDA工具，装置和计算机可读介质的方法。在一个实施例中，该方法包括：（1）生成表示集成电路的时钟插入延迟值的一组约束方程作为变量，（2）基于约束方程确定每个时钟插入延迟值的边界;以及（3）基于用于驱动所述集成电路的设计以关闭的边界产生一组关闭命令，其中所述方法的每个步骤由至少一个EDA工具执行。

8. 发明授权

US08122422B2 Establishing benchmarks for analyzing benefits associated with voltage scaling, analyzing the benefits and an apparatus therefor 有权
标题翻译：建立用于分析与电压缩放相关的益处的基准，分析其优点及其设备
公开(公告)号：US08122422B2
公开(公告)日：2012-02-21
申请号：US12510082
申请日：2009-07-27
申请人： Vishwas M. Rao , James C. Parker , Stephen A. Masnica , Robert C. Sibert
发明人： Vishwas M. Rao , James C. Parker , Stephen A. Masnica , Robert C. Sibert
IPC分类号： G06F17/50
CPC分类号： G06F1/3203 , G01R19/0084 , G06F17/5045 , Y02D10/126
摘要： Methods for establishing benchmarks and for analyzing benefits associated with voltage scaling are provided. In one embodiment, the method for establishing benchmarks includes: (1) synthesizing a netlist from a RTL of a functional IC design; (2) implementing a layout of an IC from the netlist, wherein the synthesizing and the implementing are performed at designated voltages and frequencies over a voltage and a frequency range, the voltage range including a voltage scaling range and a voltage associated with a designated implementation of the IC; (3) obtaining measurements of at least one voltage scaling metric associated with the IC at each of the designated voltages and frequencies; and (4) normalizing measurements associated with the voltage scaling range to measurements associated with the designated implementation employing a processor to obtain normalized benchmarks for analyzing optimization of the IC associated with voltage scaling. EDA tools may be used for synthesizing, implementing and obtaining.
摘要翻译：提供了建立基准和分析与电压缩放有关的益处的方法。在一个实施例中，用于建立基准的方法包括：（1）从功能IC设计的RTL合成网表; （2）从网表实现IC的布局，其中在电压和频率范围上以指定的电压和频率执行合成和实现，所述电压范围包括电压缩放范围和与指定实现相关联的电压的IC; （3）在每个指定的电压和频率下获得与IC相关联的至少一个电压缩放度量的测量值; 和（4）将与电压缩放范围相关联的测量归一化为与使用处理器获得的用于分析与电压缩放相关联的IC的优化的归一化基准的相关测量。 EDA工具可用于合成，实施和获取。

9. 发明申请

US20110023004A1 ESTABLISHING BENCHMARKS FOR ANALYZING BENEFITS ASSOCIATED WITH VOLTAGE SCALING, ANALYZING THE BENEFITS AND AN APPARATUS THEREFOR 有权
标题翻译：建立与电压调节相关的优势分析基准，分析好处及其设备的基准
公开(公告)号：US20110023004A1
公开(公告)日：2011-01-27
申请号：US12510082
申请日：2009-07-27
申请人： Vishwas M. Rao , James C. Parker , Stephen A. Masnica , Robert C. Sibert
发明人： Vishwas M. Rao , James C. Parker , Stephen A. Masnica , Robert C. Sibert
IPC分类号： G06F17/50 , G01R19/00
CPC分类号： G06F1/3203 , G01R19/0084 , G06F17/5045 , Y02D10/126
摘要： Methods for establishing benchmarks and for analyzing benefits associated with voltage scaling are provided. In one embodiment, the method for establishing benchmarks includes: (1) synthesizing a netlist from a RTL of a functional IC design; (2) implementing a layout of an IC from the netlist, wherein the synthesizing and the implementing are performed at designated voltages and frequencies over a voltage and a frequency range, the voltage range including a voltage scaling range and a voltage associated with a designated implementation of the IC; (3) obtaining measurements of at least one voltage scaling metric associated with the IC at each of the designated voltages and frequencies; and (4) normalizing measurements associated with the voltage scaling range to measurements associated with the designated implementation employing a processor to obtain normalized benchmarks for analyzing optimization of the IC associated with voltage scaling. EDA tools may be used for synthesizing, implementing and obtaining.
摘要翻译：提供了建立基准和分析与电压缩放有关的益处的方法。在一个实施例中，用于建立基准的方法包括：（1）从功能IC设计的RTL合成网表; （2）从网表实现IC的布局，其中在电压和频率范围上以指定的电压和频率执行合成和实现，所述电压范围包括电压缩放范围和与指定实现相关联的电压的IC; （3）在每个指定的电压和频率下获得与IC相关联的至少一个电压缩放度量的测量值; 和（4）将与电压缩放范围相关联的测量归一化为与使用处理器获得的用于分析与电压缩放相关联的IC的优化的归一化基准的相关测量。 EDA工具可用于合成，实施和获取。

10. 发明申请

US20100037188A1 SYSTEMATIC, NORMALIZED METRIC FOR ANALYZING AND COMPARING OPTIMIZATION TECHNIQUES FOR INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY 失效
标题翻译：用于分析和比较采用电压调节的集成电路和集成电路的优化方法的系统，正则化公制
公开(公告)号：US20100037188A1
公开(公告)日：2010-02-11
申请号：US12365010
申请日：2009-02-03
申请人： Joseph J. Jamann , James C. Parker , Vishwas M. Rao
发明人： Joseph J. Jamann , James C. Parker , Vishwas M. Rao
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G01R31/31725 , G06F1/04 , G06F1/26 , G06F1/3203 , G06F17/5081 , H03K19/215
摘要： Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to synthesize a layout from the functional IC design that meets the performance objectives by employing a unitless performance/power quantifier as a metric to gauge a degree of optimization thereof and (6) performing a timing signoff of the layout at the optimization target voltage.
摘要翻译：设计集成电路（IC）的方法的各种实施例。一种这样的方法的一个实施例包括：（1）产生IC的功能设计，（2）确定IC的性能目标，（3）确定IC的优化目标电压，（4）确定IC是否需要电压缩放以实现优化目标电压下的性能目标，如果是，则采用静态电压缩放或自适应电压缩放，（5）使用优化目标电压从功能IC设计中合成布局，满足通过采用无单位性能/功率量化器作为衡量其优化程度的度量的性能目标，以及（6）在优化目标电压下执行布局的定时签出。

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