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61. 发明授权

US07026247B2 Nanocircuit and self-correcting etching method for fabricating same 失效
标题翻译：纳米电路及其自校正蚀刻方法
公开(公告)号：US07026247B2
公开(公告)日：2006-04-11
申请号：US10696686
申请日：2003-10-28
申请人： Omer H. Dokumaci , Oleg Gluschenkov
发明人： Omer H. Dokumaci , Oleg Gluschenkov
IPC分类号： H01L21/461
CPC分类号： H01L21/0332 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L21/82385 , Y10S438/947
摘要： A self-correcting etching (SCORE) process for fabricating microstructure is provided. The SCORE process of the present invention is particularly useful for reducing preselected features of a hard mask without degrading the variation of the critical dimension (CD) within each wafer. Alternatively, the CD variation of the hard mask features' produced during printing can be substantially reduced by applying SCORE. Hence, ultra-sub-lithographic features (e.g., nanostructures) can be reliably fabricated. Consequently, the method of the present invention can be used to increase the circuit performance, while improving the manufacturing yield.
摘要翻译：提供了用于制造微结构的自校正蚀刻（SCORE）工艺。本发明的SCORE方法对于降低硬掩模的预选特征而不降低每个晶片内的临界尺寸（CD）的变化特别有用。或者，通过应用SCORE可以显着地减少在打印期间产生的硬掩模特征的CD变化。因此，可以可靠地制造超亚光刻特征（例如，纳米结构）。因此，本发明的方法可以用于提高电路性能，同时提高制造成品率。

62. 发明授权

US06806534B2 Damascene method for improved MOS transistor 失效
标题翻译：改进MOS晶体管的镶嵌方法
公开(公告)号：US06806534B2
公开(公告)日：2004-10-19
申请号：US10342423
申请日：2003-01-14
申请人： Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens
发明人： Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L2976
CPC分类号： H01L29/66583 , H01L21/26586 , H01L21/28114 , H01L29/665 , H01L29/66553
摘要： A MOSFET fabrication methodology and device structure, exhibiting improved gate activation characteristics. The gate doping that may be introduced while the source drain regions are protected by a damascene mandrel to allow for a very high doping in the gate conductors, without excessively forming deep source/drain diffusions. The high gate conductor doping minimizes the effects of electrical depletion of carriers in the gate conductor. The MOSFET fabrication methodology and device structure further results in a device having a lower gate conductor width less than the minimum lithographic minimum image, and a wider upper gate conductor portion width which may be greater than the minimum lithographic image. Since the effective channel length of the MOSFET is defined by the length of the lower gate portion, and the line resistance is determined by the width of the upper gate portion, both short channel performance and low gate resistance are satisfied simultaneously.
摘要翻译： MOSFET制造方法和器件结构，表现出改进的栅极激活特性。当源极漏极区域被镶嵌心轴保护以允许栅极导体中的非常高的掺杂而不会过度地形成深的源极/漏极扩散时，可以引入栅极掺杂。高栅极导体掺杂最大限度地减小了栅极导体中载流子的电耗损的影响。 MOSFET制造方法和器件结构进一步导致具有小于最小光刻最小图像的较低栅极导体宽度的器件，以及可能大于最小光刻图像的较宽上部栅极导体部分宽度。由于MOSFET的有效沟道长度由下栅极部分的长度限定，并且线路电阻由上部栅极部分的宽度决定，所以同时满足短沟道性能和低栅极电阻。

63. 发明授权

US06803315B2 Method for blocking implants from the gate of an electronic device via planarizing films 失效
标题翻译：通过平坦化膜从电子设备的栅极阻挡植入物的方法
公开(公告)号：US06803315B2
公开(公告)日：2004-10-12
申请号：US10212938
申请日：2002-08-05
申请人： Omer H. Dokumaci , Bruce B. Doris
发明人： Omer H. Dokumaci , Bruce B. Doris
IPC分类号： H01L21302
CPC分类号： H01L29/66545 , H01L21/31051 , H01L21/31111 , H01L21/31116 , H01L21/312 , H01L21/3144 , H01L21/31612 , H01L21/3185
摘要： A method is provided for blocking implants from the gate electrode of an FET device. Form a first planarizing film covering the substrate and the gate electrode stack. The first planarizing film is planarized by either polishing or self-planarizing. For deposition by HDP or use of spin on materials, the film is self-planarizing. Where polishing is required, the first planarizing film is planarized by polishing until the top of the gate electrode is exposed. Etch back the gate electrode below the level of the upper surface of the first planarizing film. Then deposit a blanket layer of a second planarizing film and polish to planarize it to a level exposing the first planarizing film, forming the second planarizing film into an implantation block covering the top surface of the gate. Remove the first planarizing film. Form the counterdoped regions by implanting dopant into the substrate using the implantation block to block implantation of the dopant into the gate electrode. The implantation block protects the gate electrode of the FET from unwanted implanted impurities during implanting of the counterdoped regions. The first planarizing film is composed of a material selected from the group consisting of HDP (high density plasma) silicon oxide and HDP silicon nitride, an interlevel-dielectric layer material including ONO, and photoresist. The gate electrode is composed of a material selected from the group consisting of polysilicon and metal. The second planarizing film comprises a material such as HDP oxide, HDP nitride, and an organic layer including ARCs. The second planarizing film comprises a different material from the first planarizing film.
摘要翻译：提供了一种用于阻挡来自FET器件的栅电极的植入物的方法。形成覆盖基板和栅极电极堆叠的第一平坦化膜。第一平面化膜通过抛光或自平面平坦化。为了通过HDP沉积或者在材料上使用旋涂，该膜是自平面化的。在需要抛光的情况下，第一平面化膜通过抛光进行平坦化，直到栅电极的顶部露出。在第一平面化膜的上表面的水平面下方蚀刻栅电极。然后沉积第二平坦化膜和抛光剂的覆盖层以将其平坦化至暴露第一平坦化膜的水平，将第二平坦化膜形成为覆盖栅极顶表面的注入块。取下第一个平面化膜。通过使用注入块将掺杂剂注入衬底来形成反向掺杂区域，以阻止掺杂剂注入到栅电极中。注入块在植入反向掺杂区域期间保护FET的栅电极免受不希望的注入杂质。第一平面化膜由选自HDP（高密度等离子体）氧化硅和HDP氮化硅的材料，包含ONO的层间介电层材料和光致抗蚀剂组成。栅电极由选自多晶硅和金属的材料组成。第二平面化膜包括诸如HDP氧化物，HDP氮化物和包括ARC的有机层的材料。第二平面化膜包括与第一平坦化膜不同的材料。

64. 发明授权

US06569781B1 Method of forming an ultra-thin oxide layer on a silicon substrate by implantation of nitrogen through a sacrificial layer and subsequent annealing prior to oxide formation 有权
标题翻译：通过在牺牲层上注入氮并随后在氧化物形成之前退火在硅衬底上形成超薄氧化物层的方法
公开(公告)号：US06569781B1
公开(公告)日：2003-05-27
申请号：US10054078
申请日：2002-01-22
申请人： Omer H. Dokumaci , Richard D. Kaplan , Mukesh V. Khare , Suryanarayan G. Hegde
发明人： Omer H. Dokumaci , Richard D. Kaplan , Mukesh V. Khare , Suryanarayan G. Hegde
IPC分类号： H01L21265
CPC分类号： H01L21/28211 , H01L21/26506 , H01L21/2822 , H01L21/28238 , H01L29/518
摘要： A method for forming an oxide layer on a silicon substrate includes forming a sacrificial oxide layer on the silicon substrate, implanting nitrogen into the silicon substrate, annealing the silicon substrate having implanted nitrogen, removing the sacrificial oxide layer from the silicon substrate, and forming an oxide layer on the silicon substrate. The dose of nitrogen implanted into silicon is preferably higher than 1e14 cm31 2. The annealing process is preferably performed at temperatures in a range from about 550° C. to about 1000° C. and for a time period between about 1 second and about 2 hours.
摘要翻译：在硅衬底上形成氧化物层的方法包括在硅衬底上形成牺牲氧化物层，将氮注入到硅衬底中，退火具有注入氮的硅衬底，从硅衬底去除牺牲氧化层，硅衬底上的氧化物层。植入硅中的氮的剂量优选高于1e14cm31 2.退火过程优选在约550℃至约1000℃的温度下进行约1秒至约2秒的时间小时。

65. 发明授权

US08633071B2 Silicon device on Si: C-oi and Sgoi and method of manufacture 有权
标题翻译： Si：C-oi和Sgoi上的硅器件及其制造方法
公开(公告)号：US08633071B2
公开(公告)日：2014-01-21
申请号：US13278667
申请日：2011-10-21
申请人： Duresti Chidambarrao , Omer H. Dokumaci , Oleg G. Gluschenkov
发明人： Duresti Chidambarrao , Omer H. Dokumaci , Oleg G. Gluschenkov
IPC分类号： H01L21/8238
CPC分类号： H01L29/1608 , H01L21/8213 , H01L21/823412 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/1054 , H01L29/1095 , H01L29/66651 , H01L29/7378 , H01L29/7843 , H01L29/7846 , H01L29/7849 , H01L29/8086
摘要： A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.
摘要翻译：提供半导体结构和制造方法。制造方法包括在衬底中形成浅沟槽隔离（STI），并在衬底上提供第一材料和第二材料。第一材料和第二材料通过热退火工艺混合到衬底中，以分别在nFET区和pFET区形成第一岛和第二岛。在第一岛和第二岛上形成不同材料的层。科学技术组织放松并促进第一个岛屿和第二个岛屿的放松。可以将第一材料沉积或生长Ge材料，并且第二材料可以沉积或生长Si：C或C.在第一岛和第二岛中的至少一个上形成应变Si层。

66. 发明授权

US07816237B2 Ultra shallow junction formation by epitaxial interface limited diffusion 有权
标题翻译：通过外延界面限制扩散的超浅结结形成
公开(公告)号：US07816237B2
公开(公告)日：2010-10-19
申请号：US12132698
申请日：2008-06-04
申请人： Huajie Chen , Omer H. Dokumaci , Oleg G. Gluschenkov , Werner A. Rausch
发明人： Huajie Chen , Omer H. Dokumaci , Oleg G. Gluschenkov , Werner A. Rausch
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/26533 , H01L21/02238 , H01L21/26513 , H01L21/31654 , H01L21/31675 , H01L21/324 , H01L29/0847 , H01L29/66636
摘要： A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.
摘要翻译：形成场效应晶体管的方法产生更浅和更尖的结，同时在与当前制造技术一致的工艺中最大化掺杂剂活化。更具体地，本发明增加了硅衬底的顶表面的氧含量。优选在增加硅衬底的顶表面的氧含量之前清洁硅衬底的顶表面。硅衬底的顶表面的氧含量高于硅衬底的其它部分，但低于防止外延生长的量。这允许本发明在硅衬底的顶表面上外延生长硅层。此外，增加的氧含量基本上限制外延硅层内的掺杂剂移动到硅衬底中。

67. 发明申请

US20090294854A1 HALO-FIRST ULTRA-THIN SOI FET FOR SUPERIOR SHORT CHANNEL CONTROL 有权
标题翻译：用于超级短路信道控制的HALO-FIRST ULTRA-THIN SOI FET
公开(公告)号：US20090294854A1
公开(公告)日：2009-12-03
申请号：US12538111
申请日：2009-08-08
申请人： Omer H. Dokumaci , John M. Hergenrother , Shreesh Narasimha , Jeffrey W. Sleight
发明人： Omer H. Dokumaci , John M. Hergenrother , Shreesh Narasimha , Jeffrey W. Sleight
IPC分类号： H01L29/786
CPC分类号： H01L29/66628 , H01L29/458 , H01L29/66772 , H01L29/78621 , H01L29/78696
摘要： Superior control of short-channel effects for an ultra-thin semiconductor-on-insulator field effect transistor (UTSOI-FET) is obtained by performing a halo implantation immediately after a gate reoxidation step. An offset is then formed and thereafter an extension implantation process is performed. This sequence of processing steps ensures that the halo implant is laterally separated from the extension implant by the width of the offset spacer. This construction produces equivalent or far superior short channel performance compared to conventional UTSOI-FETs. Additionally, the above processing steps permit the use of lower halo doses as compared to conventional processes.
摘要翻译：通过在栅极再氧化步骤后立即进行晕圈注入，可获得对超薄绝缘体上的场效应晶体管（UTSOI-FET）的短沟道效应的优异控制。然后形成偏移，然后执行延伸注入工艺。这个处理步骤的顺序确保了晕轮植入物与延伸植入物横向分离偏移间隔物的宽度。与传统的UTSOI-FET相比，这种结构产生等效或远优于短沟道性能。另外，与常规方法相比，上述处理步骤允许使用较低的光晕剂量。

68. 发明申请

US20090261425A1 FINFETs SINGLE-SIDED IMPLANT FORMATION 有权
标题翻译： FINFET单面植入物形成
公开(公告)号：US20090261425A1
公开(公告)日：2009-10-22
申请号：US12106476
申请日：2008-04-21
申请人： Brent A. Anderson , Andres Bryant , Josephine B. Chang , Omer H. Dokumaci , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Josephine B. Chang , Omer H. Dokumaci , Edward J. Nowak
IPC分类号： H01L29/78 , H01L21/336 , H01L21/84
CPC分类号： H01L21/26513 , H01L21/26586 , H01L29/66803 , H01L29/785
摘要： A method patterns pairs of semiconducting fins on an insulator layer and then patterns a linear gate conductor structure over and perpendicular to the fins. Next, the method patterns a mask on the insulator layer adjacent the fins such that sidewalls of the mask are parallel to the fins and are spaced from the fins a predetermined distance. The method performs an angled impurity implant into regions of the fins not protected by the gate conductor structure and the mask. This process forms impurity concentrations within the fins that are asymmetric and that mirror one another in adjacent pairs of fins.
摘要翻译：一种方法在绝缘体层上形成一对半导体翅片，然后在鳍片上并垂直于翅片形成线性栅极导体结构。接下来，该方法在与鳍片相邻的绝缘体层上形成掩模，使得掩模的侧壁平行于翅片并与翅片间隔预定距离。该方法对未被栅极导体结构和掩模保护的鳍片的区域进行倾斜的杂质注入。该方法在翅片内形成不对称的杂质浓度，并且在相邻的翅片对中彼此相互镜像。

69. 发明授权

US07476946B2 Backgated FinFET having different oxide thicknesses 有权
标题翻译：背衬FinFET具有不同的氧化物厚度
公开(公告)号：US07476946B2
公开(公告)日：2009-01-13
申请号：US11427222
申请日：2006-06-28
申请人： Andres Bryant , Omer H. Dokumaci , Hussein I Hanafi , Edward J. Nowak
发明人： Andres Bryant , Omer H. Dokumaci , Hussein I Hanafi , Edward J. Nowak
IPC分类号： H01L27/088
CPC分类号： H01L29/785 , H01L29/42368 , H01L29/42384 , H01L29/66795 , H01L29/7856
摘要： A method of producing a backgated FinFET having different dielectric layer thickness on the front and back gate sides includes steps of introducing impurities into at least one side of a fin of a FinFET to enable formation of dielectric layers with different thicknesses. The impurity, which may be introduced by implantation, either enhances or retards dielectric formation.
摘要翻译：在前栅侧和后栅极侧制造具有不同介电层厚度的背景FinFET的方法包括将杂质引入FinFET的鳍的至少一侧的步骤，以形成不同厚度的电介质层。可以通过注入引入的杂质增强或延迟电介质形成。

70. 发明授权

US06878582B2 Low-GIDL MOSFET structure and method for fabrication 失效
公开(公告)号：US06878582B2
公开(公告)日：2005-04-12
申请号：US10876873
申请日：2004-06-25
申请人： Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens
发明人： Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78 , H01L21/8238
CPC分类号： H01L29/4983 , H01L21/26586 , H01L21/28105 , H01L29/66484 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7831 , H01L29/7836 , Y10S257/90
摘要： A low-GIDL current MOSFET device structure and a method of fabrication thereof which provides a low-GIDL current. The MOSFET device structure contains a central gate conductor whose edges may slightly overlap the source/drain diffusions, and left and right side wing gate conductors which are separated from the central gate conductor by a thin insulating and diffusion barrier layer.

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