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    • 64. 发明授权
      US07737748B2 Level shifter of semiconductor device and method for controlling duty ratio in the device 有权
    • Level shifter of semiconductor device and method for controlling duty ratio in the device
    • 半导体器件的电平移位器和装置中占空比的控制方法
    • US07737748B2
    • 2010-06-15
    • US11986841
    • 2007-11-27
    • Jin-Gook Kim , Seung-Jun Bae , Dae-Hyun Chung
    • Jin-Gook Kim , Seung-Jun Bae , Dae-Hyun Chung
    • H03K3/017
    • H03K3/35613 , H03K3/017
    • A level shifter of a semiconductor device and method of controlling a duty ratio are provided. The level shifter includes first and second PMOS transistors having sources to which a power supply voltage is applied, first and second NMOS transistors having sources to which a ground voltage is applied, third and fourth NMOS transistors having sources connected to drains of the first and second NMOS transistors and gates to which the power supply voltage is applied; and a voltage controlled delay unit for receiving an input signal applied to a gate of the first NMOS transistor, inverting a level of the input signal, determining whether a voltage of an inverted input signal should be charged in response to a voltage control signal, outputting the voltage of the inverted input signal of which delay time is controlled, and applying the inverted input signal to a gate of the second NMOS transistor.
    • 提供半导体器件的电平移位器和控制占空比的方法。 电平移位器包括具有施加电源电压的源的第一和第二PMOS晶体管，具有施加接地电压的源的第一和第二NMOS晶体管，具有连接到第一和第二漏极的漏极的源的第三和第四NMOS晶体管 施加电源电压的NMOS晶体管和栅极; 以及电压控制延迟单元，用于接收施加到第一NMOS晶体管的栅极的输入信号，反相输入信号的电平，确定反相输入信号的电压是否应当响应于电压控制信号而被充电，输出 控制延迟时间的反相输入信号的电压，并将反相输入信号施加到第二NMOS晶体管的栅极。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 65. 发明申请
      US20080186075A1 Level shifter of semiconductor device and method for controlling duty ratio in the device 有权
    • Level shifter of semiconductor device and method for controlling duty ratio in the device
    • 半导体器件的电平移位器和装置中占空比的控制方法
    • US20080186075A1
    • 2008-08-07
    • US11986841
    • 2007-11-27
    • Jin-Gook Kim , Seung-Jun Bae , Dae-Hyun Chung
    • Jin-Gook Kim , Seung-Jun Bae , Dae-Hyun Chung
    • H03L5/00
    • H03K3/35613 , H03K3/017
    • A level shifter of a semiconductor device and method of controlling a duty ratio are provided. The level shifter includes first and second PMOS transistors having sources to which a power supply voltage is applied, first and second NMOS transistors having sources to which a ground voltage is applied, third and fourth NMOS transistors having sources connected to drains of the first and second NMOS transistors and gates to which the power supply voltage is applied; and a voltage controlled delay unit for receiving an input signal applied to a gate of the first NMOS transistor, inverting a level of the input signal, determining whether a voltage of an inverted input signal should be charged in response to a voltage control signal, outputting the voltage of the inverted input signal of which delay time is controlled, and applying the inverted input signal to a gate of the second NMOS transistor.
    • 提供半导体器件的电平移位器和控制占空比的方法。 电平移位器包括具有施加电源电压的源的第一和第二PMOS晶体管，具有施加接地电压的源的第一和第二NMOS晶体管，具有连接到第一和第二漏极的漏极的源的第三和第四NMOS晶体管 施加电源电压的NMOS晶体管和栅极; 以及电压控制延迟单元，用于接收施加到第一NMOS晶体管的栅极的输入信号，反相输入信号的电平，确定反相输入信号的电压是否应当响应于电压控制信号而被充电，输出 控制延迟时间的反相输入信号的电压，并将反相输入信号施加到第二NMOS晶体管的栅极。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 66. 发明申请
      US20080100357A1 Delay locked loop circuit, semiconductor device having the same and method of controlling the same 有权
    • Delay locked loop circuit, semiconductor device having the same and method of controlling the same
    • 延迟锁定环电路，具有相同的半导体器件及其控制方法
    • US20080100357A1
    • 2008-05-01
    • US11978636
    • 2007-10-30
    • Seung-Jun Bae
    • Seung-Jun Bae
    • H03L7/06
    • H03L7/0814 , H03L7/0812 , H03L7/0818 , H03L7/087 , H03L7/10
    • A delay locked loop (DLL) circuit includes a basic loop, a coarse loop, a delay model and a fine loop. The basic loop generates a plurality of first clock signals, based at least in part on an input clock signal, a feedback clock signal and a fine loop output signal. The first clock signals respectively have a phase difference. The coarse loop generates a plurality of output clock signals, based at least in part on the input clock signal, the feedback clock signal and the first clock signals. The plurality of output clock signals respectively have a phase difference. The delay model generates the feedback clock signal by delaying one of the output clock signals by a first time period. The fine loop generates the fine loop output signal, based at least in part on the input clock signal and the feedback clock signal.
    • 延迟锁定环（DLL）电路包括基本循环，粗循环，延迟模型和精细循环。 至少部分地基于输入时钟信号，反馈时钟信号和精细回路输出信号，基本回路产生多个第一时钟信号。 第一时钟信号分别具有相位差。 至少部分地基于输入时钟信号，反馈时钟信号和第一时钟信号，粗略回路产生多个输出时钟信号。 多个输出时钟信号分别具有相位差。 延迟模型通过将输出时钟信号之一延迟第一时间段来产生反馈时钟信号。 至少部分地基于输入时钟信号和反馈时钟信号，精细循环产生精细环路输出信号。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 67. 发明申请
      US20070242508A1 Low power balance code using data bus inversion 有权
    • Low power balance code using data bus inversion
    • 低功耗平衡码使用数据总线反演
    • US20070242508A1
    • 2007-10-18
    • US11730795
    • 2007-04-04
    • Seung-Jun Bae
    • Seung-Jun Bae
    • G11C11/34
    • G11C7/1006 , G11C7/02 , G11C7/1048 , G11C11/406
    • A method and apparatus for reducing power consumption needed to refresh a memory may receive data having been encoded using data bus inversion (DBI), the DBI data having a first delta between a number of zeros for different cases between zero and a DBI maximum, balance code the DBI data to balance the number of zeros across the DBI data, and output data having a number of zeros for different cases between a minimum number greater than zero and less than or equal to the DBI maximum and a maximum number equal to the minimum number plus a second delta, the second delta being less than the first delta.
    • 用于减少刷新存储器所需的功率消耗的方法和装置可以接收已经使用数据总线反转（DBI）编码的数据，DBI数据具有在零和DBI最大值之间的不同情况下的零个数之间的第一增量，余额 对DBI数据进行编码以平衡DBI数据上的零数，并且输出具有大于零且小于或等于DBI最大值的最小数量和等于最小值的最大数量的不同情况下的零个数的数据 数字加上第二个delta，第二个delta小于第一个delta。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 68. 发明申请
      US20070206428A1 HIGH-SPEED PHASE-ADJUSTED QUADRATURE DATA RATE (QDR) TRANSCEIVER AND METHOD THEREOF 有权
    • HIGH-SPEED PHASE-ADJUSTED QUADRATURE DATA RATE (QDR) TRANSCEIVER AND METHOD THEREOF
    • 高速相位调整数据速率（QDR）收发器及其方法
    • US20070206428A1
    • 2007-09-06
    • US11612800
    • 2006-12-19
    • Seung-Jun Bae , Seong-Jin Jang , Kwang-II Park , Sang-Woong Shin , Ho-Young Song
    • Seung-Jun Bae , Seong-Jin Jang , Kwang-II Park , Sang-Woong Shin , Ho-Young Song
    • G11C7/00
    • G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C11/4096
    • A high-speed double or quadrature data rate interface semiconductor device and a method thereof are provided. A transmitter (e.g., a data transmitting semiconductor device) for high-speed data transmission transmits a first strobe signal and a second strobe signal, which have a phase difference of 90 degrees there-between, a first group (byte of) data, and a second group (byte of) data. The transmitter adjusts the phase of at least one of the first and second strobe signals based on phase-error information fed back from a receiver and then transmits the phase-adjusted strobe signal to the receiver. The receiver receives the first and second strobe signals from the transmitter and receives the first group (byte of) data and the second group (byte of) data using the first and second strobe signals. The receiver does not require a phase-locked loop (PLL) or a delay-locked loop (DLL), thereby decreasing the circuit area and power consumption of the receiver. In addition, since source synchronization is realized using a strobe signal, phase noise can be efficiently removed.
    • 提供了一种高速双倍或正交数据速率接口半导体器件及其方法。 用于高速数据传输的发射机（例如，数据传输半导体器件）发送第一选通信号和第二选通信号，第一选通信号和第二选通信号之间具有90度的相位差，第一组（字节）数据和 第二组（字节）数据。 发射机基于从接收机反馈的相位误差信息来调节第一和第二选通信号中的至少一个的相位，然后将相位调整的选通信号发送到接收机。 接收机从发送器接收第一和第二选通信号，并使用第一和第二选通信号接收数据的第一组（字节）和第二组（字节）数据。 接收机不需要锁相环（PLL）或延迟锁定环（DLL），从而减少接收机的电路面积和功耗。 此外，由于使用选通信号实现源同步，因此可以有效地去除相位噪声。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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