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61. 发明授权

US06512861B2 Packaging and assembly method for optical coupling 有权
标题翻译：光耦合的封装和组装方法
公开(公告)号：US06512861B2
公开(公告)日：2003-01-28
申请号：US09892921
申请日：2001-06-26
申请人： Kishore K. Chakravorty , Ian A. Young , Joseph F. Ahadian , Johanna Marie Swan
发明人： Kishore K. Chakravorty , Ian A. Young , Joseph F. Ahadian , Johanna Marie Swan
IPC分类号： G02B612
CPC分类号： G02B6/43 , G02B6/42 , G02B6/4206 , G02B6/4212 , G02B6/4214 , G02B6/4231 , H05K1/0274 , H05K3/3436 , H05K2201/10121 , H05K2201/10734
摘要： A package allowing both electrical and optical coupling between one or more integrated circuits and a printed circuit board (PCB) has optical waveguide structures in addition to electrical connections. An optically active device may be flip-bonded directly to an integrated circuit using solder bump technology. The integrated circuit then flip-bonded or wire-bonded to a BGA package. The package has alignment rails or balls and V-grooves to anchor the alignment rails/balls to align the BGA package to the PCB. The BGA package is bonded to the PCB using solder reflow technology.
摘要翻译：允许一个或多个集成电路和印刷电路板（PCB）之间的电和光耦合的封装除了电连接之外还具有光波导结构。光学活性器件可以使用焊料凸点技术直接触发到集成电路。然后将集成电路翻转或引线接合到BGA封装。该包装具有对准轨道或球和V形槽，以锚定对准轨道/球以将BGA封装对准PCB。使用焊锡回流技术将BGA封装结合到PCB。

62. 发明授权

US06303464B1 Method and structure for reducing interconnect system capacitance through enclosed voids in a dielectric layer 失效
标题翻译：用于通过电介质层中的封闭空隙减小互连系统电容的方法和结构
公开(公告)号：US06303464B1
公开(公告)日：2001-10-16
申请号：US08774382
申请日：1996-12-30
申请人： Eng T. Gaw , Quat T. Vu , David B. Fraser , Chien Chiang , Ian A. Young , Thomas N. D. Marieb
发明人： Eng T. Gaw , Quat T. Vu , David B. Fraser , Chien Chiang , Ian A. Young , Thomas N. D. Marieb
IPC分类号： H01L2176
CPC分类号： H01L21/7682
摘要： A reduced capacitance interconnect system. A first metal layer is formed to a predetermined level above a first dielectric layer which is formed on a semiconductor substrate. The first metal layer level forms multiple interconnect lines wherein each interconnect line is separated from each adjacent interconnect line by a trench including a trench having a highest aspect ratio. A second dielectric layer is formed on the first metal layer and in the trenches between the interconnect lines such that an enclosed void having a void tip substantially level with the top of the metal layer is formed in at least each trench having an aspect ratio above a predetermined minimum aspect ratio, wherein the enclosed void in the trench having the highest aspect ratio has a void volume which is at least 15% of the volume of the trench.
摘要翻译：降低电容互连系统。第一金属层形成在形成在半导体衬底上的第一介电层上方的预定水平。第一金属层级形成多个互连线，其中每个互连线通过包括具有最高纵横比的沟槽的沟槽与每个相邻的互连线分开。在第一金属层和互连线之间的沟槽中形成第二电介质层，使得具有空隙尖端的封闭空隙与金属层的顶部基本一致地形成在至少每个沟槽中，其纵横比高于预定的最小纵横比，其中具有最高纵横比的沟槽中的封闭空隙具有至少占沟槽体积的15％的空隙体积。

63. 发明授权

US6081141A Hierarchical clock frequency domains for a semiconductor device 失效
标题翻译：半导体器件的分层时钟频域
公开(公告)号：US6081141A
公开(公告)日：2000-06-27
申请号：US979998
申请日：1997-11-26
申请人： Ian A. Young
发明人： Ian A. Young
IPC分类号： H03B19/00
CPC分类号： G06F1/10 , G06F1/08 , H03L7/18
摘要： The invention in one embodiment is a semiconductor device including a logic unit capable of receiving a first clock signal having a first frequency and generating from the first clock signal a second clock signal having a second frequency higher than the first frequency.
摘要翻译：在一个实施例中的本发明是一种半导体器件，其包括能够接收具有第一频率的第一时钟信号的逻辑单元，并且从第一时钟信号产生具有高于第一频率的第二频率的第二时钟信号。

64. 发明授权

US5235549A Semiconductor device with apparatus for performing electrical tests on single memory cells 失效
标题翻译：具有用于在单个存储器单元上执行电测试的装置的半导体器件
公开(公告)号：US5235549A
公开(公告)日：1993-08-10
申请号：US814401
申请日：1991-12-23
申请人： Ian A. Young , Ananda G. Sarangi
发明人： Ian A. Young , Ananda G. Sarangi
IPC分类号： G11C29/02 , G11C29/50
CPC分类号： G11C29/022 , G11C29/02 , G11C29/50 , G11C2029/5006
摘要： A memory device having test circuitry incorporated into its design to enable direct external access to the bit lines of a single cell is described. When the device is put in test mode by applying external control signals, peripheral I/O circuitry is disabled. Once the I/O circuitry is disabled the test circuitry selects and enables the section of the array in which the selected cell is located through transfer circuits. The enabled transfer circuit for the selected section couples data between the selected cell and a set of predetermined I/O terminals.
摘要翻译：描述了具有并入其设计中的测试电路以使得能够直接外部访问单个单元的位线的存储器件。当外部控制信号通过外部控制信号进入测试模式时，外设I / O电路被禁止。一旦I / O电路被禁止，测试电路通过传输电路选择和启用所选单元所在阵列的部分。所选部分的使能传输电路将所选择的单元和一组预定的I / O端子之间的数据进行耦合。

65. 发明授权

US4796230A Folded-cascode configured differential current steering column decoder circuit 失效
标题翻译：折叠共源共栅配置差动电流转向柱解码电路
公开(公告)号：US4796230A
公开(公告)日：1989-01-03
申请号：US65930
申请日：1987-06-24
申请人： Ian A. Young
发明人： Ian A. Young
IPC分类号： G11C11/417 , G11C7/00 , G11C7/10
CPC分类号： G11C7/00 , G11C7/1006
摘要： A folded cascode configured current steering decoder circuit for coupling a column of memory cells of a static random access memory for reading by a sense amplifier. A pair of cascode configured p-channel transistors turn on to couple memory bit lines to output lines so that the sense amplifier can provide the reading of contents of the selected memory cell. A second pair of p-channel transistors are each coupled to each of the bit lines for providing a steady state current source when the first pair of transistors are turned on for transferring information from the bit line to the output line pairs. The cascode configured transistors are MOSFET switches which are biased to cause a current inbalance when data from the memory cell are placed on the bit lines. The inbalanced current passing through the cascoded transistor pairs causes a current difference which can then sensed by a low input impedence sense amplifier. The cascoded MOSFETS provide for an isolation of the bit line capacitance from the output line capacitance to reduce the amount of time required for transferring information from the bit line to the sense amplifier.
摘要翻译：折叠共源共栅配置的当前导向解码器电路，用于耦合静态随机存取存储器的存储单元列，以供读出放大器读取。一对共源共栅配置的p沟道晶体管导通以将存储器位线耦合到输出线，使得读出放大器可以提供对所选存储单元的内容的读取。当第一对晶体管导通以将信息从位线传输到输出线对时，第二对p沟道晶体管分别耦合到每个位线以提供稳态电流源。串联配置的晶体管是MOSFET开关，当来自存储器单元的数据被放置在位线上时，MOSFET开关被偏置以导致电流不平衡。通过级联三极管对的不平衡电流导致电流差，然后可以由低输入阻抗读出放大器感测。级联MOSFETs提供了与输出线电容隔离的位线电容，以减少将信息从位线传输到读出放大器所需的时间。

66. 发明授权

US4379267A Low power differential amplifier 失效
标题翻译：低功率差分放大器
公开(公告)号：US4379267A
公开(公告)日：1983-04-05
申请号：US252972
申请日：1980-06-25
申请人： Ian A. Young
发明人： Ian A. Young
IPC分类号： H03F3/30 , H03F3/345 , H03F3/45 , H03F3/16
CPC分类号： H03F3/45179 , H03F3/3023 , H03F3/345 , H03F3/45183 , H03F2203/30018 , H03F2203/30087 , H03F2203/45192 , H03F2203/45454 , H03F2203/45456 , H03F2203/45508 , H03F2203/45658 , H03F2203/45668
摘要： A differential amplifier (24, 26, 10 and 12) having a feedback network (30, 34, 32, 36 and 38) for increasing common output without loss of gain. Also disclosed is a constant current source (60), and a level shifting network (48, 50, 52 and 54) for shifting the D.C. level of the output signal to a D.C. voltage substantially near that of second current source (44). An output stage (84, 86, 90, 92 and 94) provides low output impedance, low D.C. bias power consumption and high current drive capability.
摘要翻译： PCT No.PCT / US80 / 00805 Sec。 371日期1980年6月25日第 102（e）日期1980年6月25日PCT Filed 1980年6月25日PCT出版社 WO82 / 00071 PCT出版物具有用于增加公共输出而不损失增益的反馈网络（30,34,32,36和38）的差分放大器（24,26,10和12）。还公开了一种恒定电流源（60）和用于将输出信号的直流电平移动到基本上接近第二电流源（44）的直流电压的电平移动网络（48,50,52和54）。输出级（84,86,90,92和94）提供低输出阻抗，低直流偏置功率消耗和高电流驱动能力。

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